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This paper investigates a Vienna rectifier as a charger for series-connected battery packs. Focusing on carrier-based pulsewidth modulation (CBPWM), the ripple current flowing through the neutral point (NP) results in the voltage oscillation if the loads are resistive. To reduce the ripple of average NP current with mitigated distortion under balanced and unbalanced dc-link voltages conditions, a novel CBPWM with segmented component injection scheme (SCIS) is proposed in this paper. After dc component injection, continuous intervals for optimized component injection and clamping intervals for compensation component injection are identified. Optimized components are calculated originally based on unbalanced factor to make the average NP current zero-size in one switching period. Moreover, unique compensation components generate suitable NP current to shape the sinusoidal input currents according to the circuit analysis. In consequence, the SCIS not only keeps the input current with low-harmonic distortion, but also minimizes the oscillation of dc-link voltage under balanced and unbalanced conditions. In addition, the value of the NP current during the clamping intervals is analyzed under various operating conditions. The effectiveness and the performance of the proposed SCIS are verified by simulation and experiments. [ABSTRACT FROM AUTHOR]

The six-phase asymmetrical induction motors (SPIMs) are employed for high power medium voltage drive due to its attractive features of reduced stator copper loss, lower torque pulsation, higher torque per ampere, and higher reliability. In this paper, analysis of carrier-comparison-based pulse width modulation (PWM) techniques namely sinusoidal PWM and double zero-sequence injection PWM are carried out from a space vector perspective. Furthermore, new space vector pulsewidth modulation (SVPWM) techniques are developed by modifying the switching sequences of carrier-based PWM techniques. A comprehensive analysis of these PWM techniques is carried out in terms of harmonic flux trajectories, squared harmonic flux, and harmonic distortion factor (HDF). As a result, modified SVPWM technique namely 6ΦSVM3 is found superior to aforesaid PWM techniques, which significantly reduces HDF and provides lower current total harmonic distortion (THD). The experimental results of aforementioned PWM techniques are obtained and verified from six phase asymmetrical induction motor fed by dual two-level 3ΦVSIs. This paper is also accompanied by a video file of experimental test setup recorded while 6ΦSVM2 is running on SPIM. [ABSTRACT FROM AUTHOR]

This paper proposes a novel discontinuous pulse-width modulation (DPWM) method to reduce the current harmonics and improve the system efficiency for a single-phase three-level neutral-point clamped inverter. In single-phase inverters, the unipolar pulse-width modulation (UP-PWM) method is commonly used. However, this method has the disadvantage of power losses due to numerous switching operations. Conventional DPWM methods reduce the power losses and improve efficiency but increase the current total harmonic distortion (THD). To overcome these weaknesses, this paper proposes a hybrid DPWM switching method combining two PWM methods: the UP-PWM method and the conventional DPWM method called one-pole clamped PWM method. Since the proposed DPWM method offers all the advantages of both PWM methods, the optimal performance—with regard to the power losses and current THD—is obtained. The combination of two PWM methods is investigated by analyzing the power losses and current THD. Based on the analysis, the process determining the optimal operating condition is introduced. The effectiveness of the proposed DPWM method is demonstrated through simulations and experiments. [ABSTRACT FROM AUTHOR]

This paper proposes an active switching harmonic current reduction method within the dc-link capacitor of two-level, three-phase, back-to-back converters. This method is based on the derived analytical solution for switching harmonic currents in the dc-link. It is shown that by controlling the pulse width modulation carrier waveform's phase angles, the harmonics in the second carrier band of the rectifier and the inverter can be synchronized such that cancellation occurs in the dc-link capacitor. This synchronization is provided by harmonic phase feedback control. The feasibility of the proposed approach has been verified experimentally and results are presented in this paper. [ABSTRACT FROM PUBLISHER]

This paper presents a new feed-forward strategy for suppressing low-order harmonic circulating currents in pulsewidth-modulated (PWM) based modular multilevel converters (MMCs). The approach is based on the new average model approach established in this paper, which identifies cross-coupling interactions between the system-level and submodule elements using decomposed dependent sources. As well as improving the damping of the system, the major advantage of this approach is that it maintains the natural DC bus balance property of a PWM modulated MMC by considering the upper and lower arms together (unlike existing feed-forward schemes which treat each MMC arm independently). Moreover, unlike existing direct control resonant strategies, which require careful gain tuning and are highly dependent on the ac system frequency, the proposed approach achieves wideband circulating current ripple suppression without requiring knowledge of the circulating current harmonic frequencies and needs only a simple proportional–integral (PI) controller to regulate the circulating current dc component for power balance. This makes it particularly suitable for use in multifrequency or variable-frequency ac systems. Extensive simulation and matching experimental results, including steady-state and transient responses compared against existing circulating current suppression approaches, validate the effectiveness and benefits of this new feed-forward compensation technique. [ABSTRACT FROM PUBLISHER]

The performance of modular multilevel converters (MMCs) in medium-voltage applications, where the number of required submodules is not high, can be improved utilizing low switching frequency modulations such as (2N+1) selective harmonic elimination-pulse width modulation (SHE-PWM), which provides tight control of lower order harmonics and low switching losses. This paper proposes a calculation method, which is based on a novel formulation, to solve the SHE-PWM problem. In particular, MMCs with (2N+1) phase output voltage levels are considered, obtaining a (2N+1) SHE-PWM waveform. This method utilizes a unique system of equations that is valid for any possible waveform. Therefore, it is able to calculate simultaneously, without predefined waveforms, both the switching patterns and the associated firing angles that solve the (2N+1) SHE-PWM problem. Consequently, the search process is simplified and optimized. Furthermore, this paper also proposes a circulating current control technique, which can be applied along with (2N+1) SHE-PWM without disturbing the phase output voltage. Simulation results and experimental tests obtained with a single-phase laboratory prototype prove the validity of the novel (2N+1) SHE-PWM implementation method and the proposed circulating current control technique. [ABSTRACT FROM PUBLISHER]

Wide bandgap semiconductor switches have been increasingly utilized to improve the power density and efficiency of power converters, as such devices are able to operate at very high frequencies, e.g., up to 100 MHz, with reduced power losses. However, such a high-frequency operation may impose a challenge to the digital control system, and the system clock frequency should be up to 100 GHz in high-precision applications, which is difficult to realize in low-cost microprocessors. Instead of using extremely high-frequency clocks, preprocessing-based solutions that utilize digital pulse-width-modulated (DPWM) dither techniques can also enhance the DPWM resolution with moderate frequency clocks. Unfortunately, this is usually achieved at the expense of introducing low-frequency harmonics, which may complicate system controller and output filter design. In this paper, an optimal dither technique is proposed to enhance the resolution of DPWM power converters. The concepts of positive dither and negative dither are first proposed in this paper. Furthermore, vector-diagram-based analysis indicates that with proper utilization of positive dithers and negative dithers and carefully selected dither sequences, the lowest order harmonic introduced by the conventional dither technique can be completely eliminated when the dither period is multiples of six switching periods. In other cases, the proposed optimal dither technique can produce minimized lowest order harmonic. Finally, experimental results obtained from a Gallium Nitride (GaN) devices-based synchronous buck converter validate the feasibility of the proposed dither technique. [ABSTRACT FROM PUBLISHER]

This paper presents a novel approach to derive a pulsewidth modulation (PWM) technique for the generalized multi-phase drive. This novel approach is called a phase traversing principle. The given phase traversing principle is applied to the proposed PWM technique for five-phase open-end winding induction motor drive fed from a single dc source. The proposed PWM technique has the benefits of phase clamping, symmetrical operation of inverters, and common-mode current (CMC) elimination. Thus, it reduces the switching losses and also minimizes the issue of the CMC. The symmetrical operation of dual inverters further helps in the even distribution of losses. Also, the proposed PWM technique gives a good harmonic performance. The performance of the proposed PWM technique is analyzed using the switching loss function and harmonic flux trajectory methods. The first analysis gives justification of the reduced switching losses. While the second analysis gives the deviations in the motor flux with respect to variation in. modulation indices The proposed PWM technique is verified with both simulation and hardware results. [ABSTRACT FROM AUTHOR]

This paper proposes a new pulse amplitude width modulation (PAWM) procedure for cascaded H-bridge multilevel inverters fed by dc voltage sources with unequal amplitudes. With proposed procedure, the generated output voltage is obtained modulating a sinusoidal reference signal at the desired fundamental frequency with equally spaced switching angles. It has been analytically demonstrated that, under these assumptions, all harmonics except those of order $n=2kl\pm 1$ , $k=1,2,\ldots$ are deleted from the output voltage waveform. After a detailed description of the method and a comparative analysis with others existing in the literature, its harmonics elimination capability has been experimentally verified with 5-, 7-, 9-, and 11-level cascaded H-bridge inverters, moreover, it has been mathematically demonstrated that it reduces total harmonic distortion below 5% with a 17-level inverter and it is capable of eliminating the first 49 harmonics considered by standards with a 27-level inverter. [ABSTRACT FROM AUTHOR]

In this paper, the near-state pulsewidth modulation (NSPWM), adapted to be implemented in dual-voltage-source inverter (VSI) fed open-end motor, is proposed with the aim of mitigating low-order harmonics (which lead to current total harmonic distortion (THD) minimization). The following two proposed methods are studied in detail: 1) fixing phase angle displacement (PAD) between two VSIs to 120° while adjusting the modulation index (MI); and 2) fixing MI to the predetermined value (wherein low-order harmonics are highly mitigated) while adjusting PAD. Furthermore, the proposed approaches enhance efficiency by limiting the number of commutations within the switching interval. The paper also presents the mathematical approaches to accurately determine low-order harmonic components and switching losses for dual-VSI structure. The experimental setup, including dual-VSI and open-end induction motor, is assembled in the laboratory to evaluate performance of the proposed method. Finally, the simulation results, carried out in the MATLAB/Simulink environment, are found to be in close agreement with experimental data. [ABSTRACT FROM AUTHOR]

The paper proposes a method of active switching harmonics current reduction in the dc-link capacitor of a two-level, three-phase, back-to-back converter. Based on the derived analytical solution for switching harmonic currents in the dc-link, it is shown that by specific control over the pulsewidth-modulated (PWM) carriers’ phase angles, the targeted harmonics of the rectifier and the inverter can be synchronized in phase such that their cancellation occurs in the dc-link capacitor. This synchronization is provided by harmonic phase feedback control. A three-step procedure to implement the method is detailed in the paper. The effectiveness of the proposed approach is verified experimentally. [ABSTRACT FROM AUTHOR]

This paper proposed a novel hybrid random pulsewidth modulation (HRPWM) technique based on the modified space vector PWM for three-phase voltage source inverters to eliminate the PWM acoustic noise. Due to PWM technique and switching losses considerations, ear-piercing high-frequency noise from motor is common. The proposed HRPWM technique is able to remove the high-frequency unpleasant acoustic noise more effectively than the conventional RPWM with lower switching losses and shorter random frequency range. In addition, the PWM harmonics in phase voltage and phase current are reduced significantly. The HRPWM method is simple to implement and does not employ additional circuits in drive system. Finally, the effectiveness of the proposed approach has been confirmed by detailed experimental results. [ABSTRACT FROM AUTHOR]

The dead-time elimination pulsewidth modulation (PWM) enables the drive pulses of the upper and the lower switching devices to alternate according to the current polarity, thus abandoning the dead time and essentially avoiding the dead-time effect in power converters. However, the current zero crossing will be distorted by the current jump generated by the drive-pulse alternation, and the current zero-crossing distortion will be further intensified if errors exist in the detected current polarity. Thanks to the noise-attenuation and frequency-adaptability characteristics of the double second-order generalized integrator frequency-locked loop (DSOGI-FLL), it can obtain accurate current polarities even in harmonic and unbalanced conditions. A DSOGI-FLL-based dead-time elimination PWM is, therefore, proposed in this paper, and several improvements are made to minimize the current zero-crossing distortion. An underlap period is added when alternating the upper and lower drive pulses to smooth the current jump at zero crossing, and a delay compensation term is inserted in the DSOGI-FLL to compensate both the current measurement delay and the control delay. The effectiveness of the proposed DSOGI-FLL-based dead-time elimination PWM has been validated by experiments, respectively, in the unbalanced-current, power-change, and frequency-variation conditions with an RL load, as well as in a grid-connected converter. [ABSTRACT FROM AUTHOR]

This paper has focused on the novel space vector pulse-width modulation (SVPWM) strategy for the two-level three-phase inverter, which could eliminate the harmonics nearby pulse width modulation (PWM) frequency. Ear-piercing high-frequency electromagnetic noise from motor is common due to PWM technique. The proposed SVPWM is able to remove the high-frequency harmonics located nearby the PWM frequency and other odd multiples by changing the original switching states. The unpleasant acoustic noise could be removed with the novel strategy whose PWM frequency is selected near 10 kHz. By comparison, it is near 20 kHz for conventional SVPWM to achieve the similar performance. Therefore, the switching losses are significantly reduced using the novel method. Furthermore, the proposed technique neither changes the characteristics of the fundamental wave nor employs the additional circuits in the drive. At last, the effectiveness of proposed strategy is verified by simulation and experiment. [ABSTRACT FROM AUTHOR]

Modulation schemes can significantly change the performance of a converter in the steady state. They have, thus, been extensively studied, but directed more at three-phase topologies, where triplen offsets are added. Single-phase systems, including ac–dc–ac, are less widely pursued, even though various topologies have since been proposed. The intention of this paper is, thus, to study two promising single-phase ac–dc–ac converters using reduced number of switches, and subsequently proposes modulation schemes for them. The proposed schemes help the converters to achieve better thermal spread among their switches, while keeping their dc-link voltages low. Single points of failure are thus minimized, allowing the converters to have longer lifetimes. Simulation and experimental results have demonstrated the intended performances, hence verifying the analyses presented in this paper. [ABSTRACT FROM PUBLISHER]

Many publications have been presented on the modulation and control of the modular multilevel converter, some of which are based on phase-shifted carrier modulation. This paper presents an analysis of how the switching frequency affects the capacitor voltages, circulating currents, and alternating voltages using phase-shifted carrier modulation. It is found that switching frequencies that are integer multiples of the fundamental frequency should be avoided as they can cause the capacitor voltages to diverge. Suitable switching frequencies are derived for which the arm and line quantities will be periodic with symmetric operating conditions in the upper and lower arms. Thus, the practical outcome of this paper is a detailed description of how the switching frequency should be chosen in order to achieve advantageous operating conditions. The theoretical results from the analysis are validated by both simulations and experimental results. [ABSTRACT FROM AUTHOR]

This paper presents a new multilevel selective harmonic elimination pulse-width modulation (MSHE-PWM) technique for transformerless static synchronous compensator (STATCOM) system employing cascaded H-bridge inverter (CHI) configuration. The proposed MSHE-PWM method optimizes both the dc-voltage levels and the switching angles, enabling more harmonics to be eliminated without affecting the structure of the inverter circuit. The method provides constant switching angles and linear pattern of dc-voltage levels over the modulation index range. This in turns eliminates the tedious steps required for manipulating the offline calculated switching angles and therefore, easing the implementation of the MSHE-PWM for dynamic systems. Although the method relies on the availability of the variable dc-voltage levels which can be obtained by various topologies, however, the rapid growth and development in the field of power semiconductor devices led to produce high-efficiency dc-dc converters with a relatively high-voltage capacity and for simplicity, a buck dc-dc converter is considered in this paper. Current and voltage closed loop controllers are implemented for both the STATCOM and the buck converter to meet the reactive power demand at different loading conditions. The technique is further compared with an equivalent conventional carrier-based pulse-width modulation to illustrate its enhanced characteristics. The effectiveness and the theoretical analysis of the proposed approach are verified through both simulation and experimental studies. [ABSTRACT FROM AUTHOR]

Conventional voltage-source inverters used for induction motor drives generate a hexagonal space vector structure. In the overmodulation range, the hexagonal space vector structure generates low-order harmonics in the phase voltage resulting in low-order torque ripple in the motor. Inverter topologies with an octadecagonal (18 sided) space vector structure eliminate fifth-, seventh-, eleventh-, and thirteenth-order harmonics from the phase voltage, and hence, the dominant sixth- and twelfth-order torque ripple generation is eliminated. Octadecagonal space vector structures proposed in the past require multiple dc sources, which makes four-quadrant operation of the drive system difficult and costly. In this paper, the formation of a multilevel nine-concentric octadecagonal space vector structure using a single dc source is proposed. Detailed experimental results, using open-loop $V/f$ control and rotor field-oriented control, are presented to validate the effectiveness of the proposed drive scheme. [ABSTRACT FROM PUBLISHER]

The six-step operation of surface-mounted permanent magnet machine drives in a flux weakening region has many advantages compared to the pulse width modulation mode, such as the reduced switching loss and fully utilized inverter output voltage. However, if the ratio of the sampling frequency to the fundamental frequency is low in fixed sampling system, the low-frequency oscillation in the current can be incurred in the six-step operation. The low-frequency current causes a system stability problem and reduces system efficiency due to an excessive heat and high power loss. Therefore, this paper proposes the variable time step controller for six-step operation. By updating an output voltage, sampling phase currents, and executing the digital controller synchronized with the variable sampling time, the turn on and off switch signals for six-step operation can be generated at the exact moment. As a result, the low-frequency oscillation in the phase current can be eliminated. In addition, the system transfer function of the proposed control method is discussed for the system stability and system dynamic analysis. The effectiveness of the proposed method is verified by the comparative simulation and experimental results. [ABSTRACT FROM AUTHOR]

This paper presents a model predictive switching pattern control (MPSPC) for a current-source converter (CSC), which achieves superb low-order harmonics elimination performance in steady state and improved transient responses. Based on a proposed space-vector-based selective harmonic elimination (SHE) method and prediction of load current at the next sampling instant, MPSPC prefers to following a precalculated SHE-pulse width modulation (PWM) pattern in steady state, and governing the CSC through a model predictive control (MPC) approach during transients. In comparison with existing schemes, the advantages of MPSPC are threefold: First, quantization error, introduced by a constant sampling frequency in MPC and degrading steady-state low-order harmonic elimination, is mitigated in the proposed scheme. Second, there is no weighting factor in the cost function, as used in existing schemes. Finally, MPSPC is totally realized based on one-step prediction, which simplifies the structure of the scheme. Both simulation and experimental results verify the steady state and dynamic performance of MPSPC with different SHE-PWM patterns. [ABSTRACT FROM AUTHOR]

A new zero-sequence circulating current (ZSCC) reduction method for multimodule voltage source inverters (MVSIs) consisting of P three-phase inverters that are connected in parallel is proposed in this paper. Four-switch inverter modules are used instead of the conventional six-switch modules to reduce the cost. In this paper, the effectiveness of the proposed ZSCC reduction method is studied using selective harmonic elimination pulse width modulation. The proposed ZSCC reduction method can remove about P times the number of harmonics using the same switching frequency as compared to more conventional methods, as explained later in this paper. The concepts discussed in the paper are confirmed with results obtained from an MVSI experimental prototype. [ABSTRACT FROM AUTHOR]

Distributed energy resources (DERs) are expected to provide ancillary functions including reactive power generation and harmonics compensation. Meanwhile, multilevel inverters and two-level converters with optimal pulsewidth modulation (OPWM) will be commonly used for DERs at high power levels. The challenge is to realize harmonic compensation with limited switching angles. This paper presents an online solution to realize the selective harmonics compensation (SHC), and power generation with DERs. For harmonics compensation, the selective harmonic components in the load current are detected. Then, the harmonic voltages are provided with DERs to cancel out these detected components. Since the power converter is requested to realize both harmonics filtering and power generation, limitations on harmonics compensation at the given power are discussed. Power hardware-in-the-loop-based online verifications are shown at the end of the paper. [ABSTRACT FROM AUTHOR]

PWM techniques for a full-bridge dc/dc converter are investigated and a new random PWM technique is proposed in this paper. Three PWM techniques with constant switching frequency are discussed and the related random PWM techniques which spread the harmonic clusters and give constant average inductor current to reduce the output voltage ripple are discussed. The pros and cons of three constant switching frequency PWM techniques and the related random counterparts are investigated. Experimental results show that there is a significant efficiency drop of the random PWM technique due to significant increase of switching counts. Therefore, this paper presents a new random PWM technique to significantly reduce the harmonic intensity while not causing relevant impact on the efficiency. An FPGA-based digital-controlled isolated full-bridge dc/dc converter prototype is built to verify the performance of conventional and proposed PWM techniques. The specifications of the converter include the following: input voltage = 400 V, output voltage = 12 V, output power = 528 W, and switching frequency = 100 kHz. Measured efficiency and harmonic spread factor will be used for the evaluation of these PWM techniques. [ABSTRACT FROM AUTHOR]

Multilevel inverters with hexagonal and dodecagonal voltage space vector structures have improved harmonic profile compared to two-level inverters. Further improvement in the quality of the waveform is possible using multilevel octadecagonal (18-sided polygon) voltage space vectors. This paper proposes an inverter circuit topology capable of generating multilevel octadecagonal voltage space vectors, by cascading two asymmetric three-level inverters. By the proper selection of dc-link voltages and the resultant switching states for the inverters, voltage space vectors, whose tips lie on three concentric octadecagons, are obtained. The advantages of octadecagonal voltage space vector-based pulsewidth modulation (PWM) techniques are the complete elimination of fifth, seventh, eleventh, and thirteenth harmonics in phase voltages and the extension of linear modulation range. In this paper, a simple PWM timing calculation method is also proposed. Experimental results have been presented in this paper to validate the proposed concept. [ABSTRACT FROM PUBLISHER]

This paper investigates the suitability of selective harmonic elimination (SHE) for low-loss multimegawatt grid-connected photovoltaic (PV) inverters. The proposed system is able to meet utilities regulations, IEEE and IEC standards. In an attempt to substantiate the potential superiority of SHE over carrier-based or space-vector pulsewidth modulation (PWM), this paper demonstrates that SHE may allow grid-connected PV inverters to be controlled using a switching frequency of less than 1 kHz, while the inverter is still able to provide necessary operation features such as independent control of active and reactive powers and operation control simplicity. For system validation, experimental results with SHE are compared to the case when the inverter is controlled using third-harmonic injection PWM, with a 2-kHz switching frequency. Furthermore, the paper proposes a new implementation technique for SHE that utilizes the third harmonics to spread the switching angles over 90° instead of being located in a narrow range as generated when using conventional techniques, along with increases in modulation index. The advantages of the proposed technique include simplicity in implementation and flexibility in PWM waveforms. Simulation and experimentation demonstrate agreement, which validates the practicability of the proposed system. [ABSTRACT FROM AUTHOR]

An open-winding power conversion system with two conventional six-switch voltage-source converters (VSC) affords operation with a lower volt-ampere (VA) rating of each device for a given power rating, as well as a degree of fault tolerance. The disadvantages of such a configuration include a higher total device VA rating and increased conduction loss as compared to a single Y/Δ-connected VSC. In certain ac-dc applications, such as telecommunications, wind, and aerospace generator drives, it is desired to have regulated input currents and output voltage, but regenerative operation is either not required or prohibited. For such applications, an alternative open-winding power converter is proposed in this paper where half-controlled converter (HCC) is employed at each end of an open-winding structure. The resultant total switch count and total VA rating are reduced by half, compared to using full bridges. Besides, the basic advantages of an open-winding configuration, use of HCCs also guarantees immunity to dc-bus shootthrough and simplifies the gate drive circuit. The total VA rating of the proposed topology is found to be 42% less than a six-switch VSC. The operating principle, control method, and analysis with simulation and experimental results of the proposed topology in both a grid-tied rectifier application and a PM generator application are illustrated in this paper. [ABSTRACT FROM AUTHOR]

This paper addresses the inverter nonlinearity of a three-level T-type inverter. The main causes of the nonlinearity are pulse shaping, pulse skipping due to narrow pulses for the dead time, and voltage drop of the switching devices. Although the same causes have existed in two-level inverters, the pulse skipping phenomenon and results are quite different in the case of the three-level T-type inverter. The effects of pulse shaping and skipping have been investigated and discussed. In addition, the voltage drop of the switching devices has been considered in conjunction with the conduction path of the T-type inverter. Compensation methods based on the pulse width modulation (PWM) of T-type inverter to alleviate the inverter nonlinearity have been proposed from research results. The proposed methods could be easily implemented by adding appropriate offset voltages to the voltage references of the inverter in PWM. Furthermore, a neutral voltage balancing method of a three-level T-type inverter has been proposed in conjunction with the proposed PWM methods using offset voltage. Through extensive experimental tests, the fifth- and seventh-harmonic components of the current are conspicuously reduced along with the even harmonics. The neutral voltage of the inverter can be balanced effectively with the proposed offset voltage adjustments as well. [ABSTRACT FROM AUTHOR]

This paper investigates a control method to significantly reduce the low-frequency current oscillation for six-step operation of a three-phase inverter. The six-step operation of an ac electric machine drive system under high speeds has a few advantages compared with pulse width modulation (PWM) operation including reduced switching losses, a better utilization of the dc bus voltage, and an enhanced speed capability. In digital implementation of the six-step control, power electronics may not be able to switch on and off exactly at the zero crossing points of reference voltages, which will result in a dc offset in phase voltages and cause a low-frequency oscillation in phase currents. The low-frequency oscillation will create issues such as higher power losses, lower efficiency, and excessive heat that may demagnetize magnets on the rotor for a permanent magnet synchronous machine. This research presents a control algorithm using asymmetric PWM to ensure that power electronics switch on and off exactly at the reference voltage zero crossing points. Both simulation and experimental results demonstrate the algorithm can reduce the low-frequency oscillation in phase currents by more than 90%. [ABSTRACT FROM AUTHOR]

The purpose of this paper is to investigate the impact of switching harmonics on the instantaneous power distribution in the cells of a cascaded H-bridge-based STATCOM when using phase-shifted pulse width modulation. The case of high- and low-switching frequency for the converter cells is investigated and the interaction between voltage and current harmonics is analyzed. It is shown that in both cases, this interaction results in an uneven power distribution among the cells in the same phase leg, leading to drifting of the dc-capacitor voltages and thereby the need for proper stabilization control loops. It is also shown that the selected frequency modulation ratio affects the active power distribution among the cells. In particular, the selection of a noninteger frequency modulation ratio helps in providing a more uniform power distribution among cells of the same phase leg, thus contributing to the capacitors balancing. A methodology for optimal selection of the frequency modulation ratio is given. Theoretical conclusions are validated through simulation and experimental results. [ABSTRACT FROM AUTHOR]

The device switching frequency of current source converters (CSCs) in high-power medium-voltage (MV) drive applications is normally around 500 Hz. Conventional space vector modulation (SVM) features fast dynamic response but its output contains low-order harmonics with high magnitudes. In this paper, a natural-sampling-based SVM (NS-SVM) scheme is proposed to substantially suppress the low-order harmonics in practical CSC-based drives. This study proposes an equivalent discretization of NS-SVM wherein natural sampling pulse width modulation performance can be achieved with regular sampling frequency (same as a conventional SVM) instead of a high or even infinite sampling frequency. Equations for natural-sampling-based dwell time calculations for each selected vector are developed. The corresponding simplified but precise enough equations are derived on the basis of the Newton–Raphson algorithm to achieve fast online digital implementation. The proposed NS-SVM features superior low-order harmonic performance and inherits the high dynamic response and low sampling frequency of conventional SVM. Simulations and experiments are provided to verify the proposed NS-SVM scheme. [ABSTRACT FROM AUTHOR]

This paper presents the Bee optimization method for harmonic elimination in a cascaded multilevel inverter. The main objective in selective harmonic elimination pulsewidth modulation strategy is eliminating low-order harmonics by solving nonlinear equations, while the fundamental component is satisfied. In this paper, the Bee algorithm (BA) is applied to a 7-level inverter for solving the equations. The algorithm is based on the food foraging behavior of a swarm of a honeybees and it performs a neighborhood search combined with a random search. This method has higher precision and probability of convergence than the genetic algorithm (GA). MATLAB software is used for optimization and comparison of GA and BA. Simulation results show superiority of BA over GA in attaining accurate global minima and higher convergence rate. Also, its performance in 10 times run is the same as in 1 time run. Finally, for verifying purposes, an experimental study is performed. [ABSTRACT FROM AUTHOR]

This paper provides theoretical and experimental discussions on an optimal carrier frequency for a phase-shifted pulsewidth modulation modular multilevel cascade converter for grid connections. The theoretical discussion concludes that a ratio of the optimal carrier frequency with respect to the supply (ac) frequency is 5/2. A three-phase downscaled front-to-front system is designed, constructed, and tested to confirm validity of the theoretical discussion. It consists of a pair of three-phase modular multilevel cascade converters rated at 400 Vdc and 10 kW, where the carrier frequency is set to 450 Hz and the ac frequency to 180 Hz, that is, their ratio is equal to 5/2. Moreover, simulated waveforms are compared to experimental ones under the same operating conditions. Both experimental and simulated waveforms agree well with each other not only in steady states but also in transient states. [ABSTRACT FROM AUTHOR]

This paper provides a theoretical and experimental discussion about the performance, availability, and flexibility of a battery energy storage system (BESS) using a modular multilevel cascaded converter based on single-star bridge cells (MMCC-SSBC). The SSBC-based BESS produces three-phase multilevel voltage waveforms, and eliminates both harmonic filters and a complicated zig-zag transformer from the ac side. The circuit modularity of the SSBC enables the usage of multiple individual low-voltage battery modules. Along with control strategy based on zero-sequence-voltage injection, this modularity enhances the availability and flexibility of the BESS. A three-phase laboratory downscaled system rated at 140 V, 10 kW, and 21 kW·h is designed, constructed, and tested to verify the operating principles and performance. The tested BESS produces a current total harmonic distortion (THD) of 3.0% even when it operates with different active-power commands for individual bridge cells. In addition, zero-voltage ride-through capability is verified for the severest single-phase, two-phase, and three-phase voltage sags. Mathematical analysis and experimental verification validate the downscaled system and performance, making the BESS prospective. [ABSTRACT FROM PUBLISHER]

In this paper, three control schemes with variable switching frequencies are proposed and analyzed for the paralleled voltage source inverters (VSIs) fed permanent magnet synchronous motor (PMSM) drive. The proposed schemes could be applied in the low-speed operation region of high-power drive system, where the frequency modulation index is high. First, the field-oriented control (FOC) with phase-shifted chaotic space vector modulation (SVM) under synchronous frame and the FOC with phase-shifted chaotic sinusoidal pulse width modulation under stationary frame is proposed for the paralleled VSIs fed PMSM drive. The proposed phase-shifted chaotic PWM schemes not only eliminate specific switching harmonics completely but also suppress all remaining switching harmonic peaks in the spectrum. The avoidance of inherent circulating current is also considered in designing these two schemes. Second, the direct torque control (DTC) for the paralleled VSIs fed PMSM drive is proposed with circulating current suppression. Besides inheriting the advantages of DTC, the output currents of paralleled VSIs are kept balanced. The working principles of these three methods are presented in detail. Experimental results on a laboratory prototype are given to verify the validity of the three proposed control schemes for the paralleled VSIs fed PMSM with variable switching frequencies. [ABSTRACT FROM PUBLISHER]

This paper demonstrates for the first time the use of a very large secure digital card flash memory to the design of a three-phase pulse width modulation (PWM) generator and describes the hardware and software used for implementation. The new digital architecture differs from the conventional counter-based implementation, and it follows a preprogrammed optimal PWM pattern that is read from memory with magnitude and phase as coordinates. This architecture allows the inclusion of multiple optimization criteria within the PWM pattern. This digital architecture becomes valuable since the switching instants can be set in any conceivable manner, away from the rigid constraint of a repetitive sequence of states on each PWM period. Experimental results validate that the proposed new architecture allows simple and low cost implementation of complicated PWM patterns with harmonic reductions that could not otherwise be achieved for low cost. [ABSTRACT FROM AUTHOR]

Modulating the output of a voltage source inverter (VSI) inherently causes current distortions on the load side due to the switching behavior of the inverter. This paper describes a method to reduce these distortions for a drive setup with six phases. The setup consists of a six-phase machine connected to two three-leg two-level VSIs. The phases within the machine are symmetrically arranged and spatially shifted by $60^\circ$ . The phases are grouped so that two conventional three-phase sets are formed, each fed by one inverter. The output of each inverter leg is modulated by comparing a triangle carrier waveform with the desired fundamental wave. Arranged in this way, the drive setup offers an additional degree of freedom, the phase shift of the two carrier waveforms. It is shown that, depending on the machine parameters, there exists an optimal angle, which reduces the harmonic losses of the drive for a certain amplitude of the fundamental wave. The resulting overall current distortion can even be lower compared to a conventional three-phase drive with a two- or three-level inverter topology. For three different modulation techniques, the optimal phase shift angles are derived in an exact form, naturally, symmetrical regular and asymmetrical regular sampled pulse width modulation. An approximation with reasonable accuracy is achieved out of the exact solution. Simulations and experimental tests validate the theoretical considerations. [ABSTRACT FROM AUTHOR]

An algebraic method is proposed for selective harmonic elimination PWM (SHEPWM). By computing its Groebner bases under the pure lexicographic monomial order, the nonlinear high-order SHE equations are converted to an equivalent triangular form, and then a recursive algorithm is used to solve the triangular equations one by one. Based on the proposed method, a user-friendly software package has been developed and some computation results are given. Unlike the commonly used numerical and intelligent methods, this method does not need to choose the initial values and can find all the solutions. Also, this method can give a definite answer to the question of whether the SHE equations have solutions or not, and the accuracy of the solved switching angles are much higher than that of the reference method. Compared with the existing algebraic methods, such as the resultant elimination method, the calculation efficiency is improved. Experimental verification is also shown in this paper. [ABSTRACT FROM AUTHOR]

This paper proposes a resonant dual-active bridge (DAB) converter, which uses a tuned capacitor–inductor–capacitor network. In comparison to the conventional DABs, the proposed topology significantly reduces the bridge currents, lowering both conduction and switching losses and improving the bridge power factors. A mathematical model, which predicts the behavior of the proposed system, is presented to show that both the magnitude and direction of the power flow can be controlled through either relative phase angle or pulse width modulation of voltages produced by the bridges. The viability of the proposed concept is verified through simulation. Experimental results of a 4- kW prototype converter, which has an efficiency of 95% at rated power, are also presented with discussions to demonstrate the improved performance of this topology. [ABSTRACT FROM AUTHOR]

In this paper, an analysis and calculation of the dc-link current and voltage ripples are presented for a three-phase inverter with unbalanced load. A comparison of the dc-link average and root-mean-square (rms) currents between considering and ignoring high frequency harmonics of the output current is drawn. It is shown that high frequency harmonic currents have little effect on the dc-link current, and therefore, they can be ignored. Based on the symmetrical components method, the dc-link average and harmonic rms currents are derived, and the dc-link voltage ripple is compared between the balanced and unbalanced loads. It can be found that the dc-link current and voltage ripples consist of not only high frequency harmonics but also the double fundamental frequency harmonic, and the voltage ripple is independent of the positive-sequence component and determined by the negative-sequence component, under the unbalanced load. Experimental results are shown to verify the accuracy of the theoretical analysis. [ABSTRACT FROM AUTHOR]

Pulse width modulation schemes are aimed at adjusting the fundamental component while reducing the harmonic content of an inverter output voltage or current. This paper addresses the topic of optimal inverter operation in reference to a given objective function. The objective function could embody either a single performance criterion, such as voltage or current total harmonic distortion (THD), or a weighted sum of multiple criteria. The proposed method ensures primacy of the chosen solution while imposing no restriction over its modulation index. In particular, operating the inverter by the chosen solution would result in performances superior to any other modulation scheme commutating in an equal number of switching angles per fundamental cycle. The proposed method allows for the consideration of practical inverter constraints and prevents the possibility of impractical switching sequence. A detailed investigation of the method is given, accompanied by two practical cases minimizing, respectively, phase-voltage THD and line-current THD of a three-level inverter. Selected simulation and experimental results are presented to validate the theoretical part. [ABSTRACT FROM AUTHOR]

This paper proposes a new modulated carrier control method for an interleaved continuous conduction mode (CCM) power factor correction (PFC) boost converter. The proposed method allows precise sinusoidal line current shaping for a PFC boost converter operating in CCM. This is accomplished by simply comparing modulated carrier signal with switch current, such that inner current loop compensation design and rectified line voltage sensing are not required. The proposed control method greatly simplifies current sensing and control circuitry of multiphase converters since average current control is available by just sensing the switch current for each module. This also enables simple current balancing between parallel converters by employing modulated carrier signals with same amplitude. The principle of the control method is presented. The performance of the proposed control method is experimentally verified on a 600-W PFC converter. The measured power factor remains above 94.9% down to 20% of a full load for 110-Vrms and 220-Vrms line voltages. The line current harmonics also meet the IEC61000-3-2 Class D standard. [ABSTRACT FROM AUTHOR]

The analysis and assessment of the pulsewidth modulation (PWM) techniques is commonly based on the comparison of the total harmonic distortion (THD) results. THD is usually calculated by application of the Fourier transformation and by taking a limited number of harmonics into the consideration. In this paper, derivation of analytical formulas for the phase voltage THD is presented. The considered system is a symmetrical multiphase star-connected load, supplied from a multilevel pulsewidth-modulated voltage-source inverter (VSI, three-phase case is also covered). The solution is based on the Parseval's theorem, which links frequency spectrum and time domain through the average power (i.e., root-mean-square (rms) squared value) of the signal. The assumption throughout the derivations is that the ratio of the switching to fundamental frequency is high. Derivations are based on the integration of the power of the PWM signal in a single switching period over the fundamental period of the signal. Only ideal sinusoidal reference voltages are analyzed, and no injection of any type is considered. Formulas for phase voltage THD for any number of phases are derived for two- and three-level cases, for the most commonly used carrier-based methods. Comparison of the analytically obtained curves with simulation and experimental results shows a high level of agreement and validates the analysis and derivations. [ABSTRACT FROM AUTHOR]

In this paper, a generalized switching technique for cascaded H -bridge (CHB) converters is proposed. To take advantage of both low- and high-frequency modulation techniques, a hybrid modulation method is utilized. The proposed technique employs the low-frequency switching for voltage balancing of the dc-link capacitors, and the high-frequency sinusoidal pulse-width modulation switching for shaping the input ac current. Using the proposed technique, the stable operating region of CHB converters is extended. The proposed technique is capable of maintaining the dc voltages balanced even under critical operating conditions in which the load of one H-bridge cell is removed. The validity and effectiveness of the proposed method is confirmed by several simulation and experimental tests on a seven-level CHB rectifier. [ABSTRACT FROM AUTHOR]

Dodecagonal (12-sided) space vector pulsewidth modulation (PWM) schemes are characterized by the complete absence of (6n ± 1)th-order harmonics (for odd n) in the phase voltages, within the linear modulation range and beyond, including overmodulation. This paper presents a new topology suitable for the realization of such multilevel inverter schemes for induction motor (IM) drives, by cascading two-level inverters with flying-capacitor-inverter fed floating H-bridge cells. Now, any standard IM may be used to get the dodecagonal operation which hitherto was possible only with open-end winding IM. To minimize the current total harmonic distortion (THD), a strategy for synchronous PWM is also proposed. It is shown that the proposed method is capable of obtaining better THD figures, compared to conventional dodecagonal schemes. The topology and the PWM strategy are validated through analysis and subsequently verified experimentally. [ABSTRACT FROM AUTHOR]

This paper further develops a model predictive control (MPC) scheme which is able to exploit the large number of redundant switching states available in a multilevel H-bridge StatCom (H-StatCom). The new sections of the scheme provide optimized methods to tradeoff the harmonic performance with converter switching losses and capacitor voltage ripple. Varying the pulse placement within the modulation scheme and modifying the heuristic model of the voltage balancing characteristics allows the MPC scheme to achieve superior performance to that of the industry standard phase shifted carrier modulation technique. The effects of capacitor voltage ripple on the lifetime of the capacitors are also investigated. It is shown that the MPC scheme can reduce capacitor voltage ripple and increase capacitor lifetime. Simulation and experimental results are presented that confirm the correct operation of the control and modulation strategies. [ABSTRACT FROM PUBLISHER]

The dual-half-controlled-converter (DHCC) is a voltage-source active rectifier which can be considered as a potential alternative to the conventional three-phase six-switch boost rectifier. The DHCC is attractive due to its lower component current rating, immunity to shoot-through, simpler gate drive circuitry, lower semiconductor losses, and fault redundancy. Compared to a six-switch voltage-source-converter and a diode rectifier with a shunt active filter, DHCC presents some advantages and has good potentials for grid-tied and generator-tied applications. In the previous literature, the DHCC was controlled through a hysteresis regulator. This paper discusses in detail the current compensation and harmonic cancellation methodologies and presents improved control techniques for the three-phase three-wire DHCC using interleaved pulsewidth modulation (PWM). Compared with the existing hysteresis controller, the proposed fixed-frequency PWM controllers require smaller filtering elements and/or a lower sampling frequency. Both simulation and experimental results are presented to demonstrate the superiority of the proposed PWM control algorithm. The impacts of input reactor sizing and dc-link voltage rating are analyzed and discussed. [ABSTRACT FROM AUTHOR]

This paper presents a multilevel inverter topology suitable for the generation of dodecagonal space vectors instead of hexagonal space vectors as in the case of conventional schemes. This feature eliminates all the 6n ± 1 (n = odd ) harmonics from the phase voltages and currents in the entire modulation range with an increase in the linear modulation range. The topology is realized by flying capacitor-based three-level inverters feeding from two ends of an open-end winding induction motor with asymmetric dc links. The flying capacitor voltages are tightly controlled throughout the modulation range using redundant switching states for any load power factor. A simple and fast carrier-based space-vector pulsewidth modulation (PWM) scheme is also proposed for the topology which utilizes only the sampled amplitudes of the reference wave for the PWM timing computation. [ABSTRACT FROM AUTHOR]

Sliding mode control (SMC) is recognized as robust controller with a high stability in a wide range of operating conditions, although it suffers from chattering problem. In addition, it cannot be directly applied to multiswitches power converters. In this paper, a high performance and fixed switching frequency sliding mode controller is proposed for a single-phase unipolar inverter. The chattering problem of SMC is eliminated by smoothing the control law in a narrow boundary layer, and a pulsewidth modulator produces the fixed frequency switching law for the inverter. The smoothing procedure is based on limitation of pulsewidth modulator. Although the smoothed control law limits the performance of SMC, regulation and dynamic response of the inverter output voltage are in an acceptable superior range. The performance of the proposed controller is verified by both simulation and experiments on a prototype 6-kVA inverter. The experimental results show that the total harmonic distortion of the output voltage is less than 1.1% and 1.7% at maximum linear and nonlinear load, respectively. Furthermore, the output dynamic performance of the inverter strictly conforms the standard IEC62040-3. Moreover, the measured efficiency of the inverter in the worst condition is better than 95.5%. [ABSTRACT FROM AUTHOR]

Bitstream-based control, which uses one-bit-wide signals to control power electronics applications, is a new approach for controller design. Bit-Stream signals can be directly applied to control electronic devices, but the high-frequency nature of bitstream signals can lead to excessive switching losses. Thus, it is essential to downsample bitstream signals to reduce switching losses to acceptable levels. This paper presents a novel modulator, which downsamples high-frequency bitstreams to low-frequency switching signals that are suitable for driving two-level half-bridge or three-level full-bridge inverters. Methods for compensating for switch dead time and balancing switching losses of the inverter legs are presented, and the performance of the proposed modulators are compared to the standard pulse width modulation strategies. Simulation and experimental results of a 2-kW single-phase inverter show that the proposed bitstream modulators consume fewer logic resources, produce spread-spectrum output currents, and can deliver lower total harmonic distortion than similar fixed-frequency pulse width modulators. [ABSTRACT FROM AUTHOR]

A modified single-phase quasi-Z-source ac-ac converter is proposed in this paper. The proposed converter has the main features in that the output voltage can be bucked or boosted and be both in-phase and out-of-phase with the input voltage. The input voltage and output voltage share the same ground, the size of a converter is reduced, and it operates in a continuous current mode. A safe-commutation strategy for the modified single-phase quasi-Z-source ac-ac converter is used instead of a snubber circuit. The operating principles and a steady-state analysis are presented. A laboratory prototype, tested using a resistive load, a passive load, and a nonlinear load, was constructed that used an input voltage of 70 Vrms /60 Hz in order to verify the performance of the modified single-phase quasi-Z-source ac-ac converter. The experimental results verified that the converter has a lower input current total harmonic distortion, a higher input power factor, and a higher efficiency in comparison to a conventional single-phase Z-source ac-ac converter. In addition, the experimental results show that the use of the safe-commutation strategy is a significant improvement, as it makes it possible to avoid voltage spikes on the switches. [ABSTRACT FROM AUTHOR]