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The three-level neutral point-clamped (NPC) converter has attracted much attention in high-power medium-voltage applications, but it is well-known that the NPC topology suffers from unequal power loss distribution among its semiconductor devices. The power loss unbalance problem becomes especially severe when the converter is operating at low fundamental frequencies. To overcome the loss unbalance problem of the NPC converter, the active NPC (ANPC) technique was introduced. However, it is demonstrated in this paper that in many cases, the conventional modulation method for the ANPC converter only marginally relieves the loss unbalance problem. This paper proposes a new modulation scheme (named the adaptive doubled frequency modulation) for the three-level ANPC converter, which significantly improves the power loss and thermal sharing among the semiconductor devices. The basic idea of the proposed scheme is adaptively adjusting the duty cycles of the switching states for every switching cycle, so as to optimize the power loss distribution. Simulation and experimental results verify this new method. [ABSTRACT FROM AUTHOR]

Direct power control (DPC) has attracted wide attention due to its advantages of simple structure, quick response, strong robustness, and elimination of current regulation/pulse width modulation blocks. However, conventional table-based DPC cannot work well when the grid voltages are unbalanced. Some work has been done on DPC to mitigate the influence of grid unbalance by adding power compensations to the original power references. However, they are usually complicated due to the positive/negative-sequence extraction of grid voltage and/or currents. Furthermore, applying only one voltage vector during one control period leads to high steady-state power ripples. This paper proposes an improved DPC by using a new definition of instantaneous reactive power. As a result, the distortion in grid current is eliminated, and constant active power and new reactive power are obtained. Neither complicated calculation of power compensation nor positive/negative-sequence extraction of grid voltage/current is required. The corresponding switching table suitable to regulate both active power and the new reactive power is established. Furthermore, the concept of duty cycle control is introduced to further improve the steady-state performance. Both simulation and experimental results are presented to confirm the theoretical study and the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

This paper presents a pulse width modulation (PWM) technique for the minimization of the leakage current in the grid-connected/stand-alone transformerless photovoltaic (PV)-cascaded multilevel inverter (CMLI). The proposed PWM technique is integrated with the MPPT algorithm and is applied to the five-level CMLI. Furthermore, using the proposed PWM technique the high-frequency voltage transitions in the terminal and common mode voltages are minimized. Thus, the proposed PWM technique minimizes the leakage current of the PV array and electromagnetic interference filter requirement in the system without addition of any extra switches. Furthermore, this paper also presents the analysis for the terminal voltage across the PV array and the common mode voltage of the inverter based on the switching function. Using the given analysis, the effect of the PWM technique can be analyzed, as it directly links the switching function with the common mode voltage and leakage current. Also, the proposed PWM technique requires reduced number of carrier waves compared to the conventional sinusoidal pulse width modulation technique for the given CMLI. Complete details of the working principle and analysis with the support of simulation and experimental results of the proposed PWM technique are presented in this paper. [ABSTRACT FROM PUBLISHER]

In transformerless high-power pulse width modulation (PWM) current-source drives, common-mode inductor is implemented to attenuate the common-mode voltage (CMV). However, the common-mode inductor is bulky and costly, so that scaling down the size of the common-mode inductor can achieve the system size reduction and efficiency enhancement. The size of the common-mode inductor is mainly related to the maximum common-mode current, which occurs at the resonant frequency of the common-mode circuit when motor speed is low. Previous research demonstrates that 3-segment average-value-reduction (AVR) space vector modulation (SVM) has good common-mode resonance suppression performance by attenuating the third-order CMV from the inverter. However, as studied in this paper, when modulation index of the inverter is lower than 0.4, the performance of 3-segment AVR SVM is affected as the dwell time of zero vector becomes too long to effectively compensate the CMV introduced by the active vectors. To overcome this problem, three modified AVR SVM schemes are proposed in this paper, where the single long zero vector is separated into two segments in the PWM sequence. The working principles, CMV reduction performance, harmonic performance, and switching frequency analysis of the proposed SVM methods are presented in detailed. Experiments are conducted to verify the effectiveness of the proposed methods. [ABSTRACT FROM PUBLISHER]

In this paper, the near-state pulsewidth modulation (NSPWM), adapted to be implemented in dual-voltage-source inverter (VSI) fed open-end motor, is proposed with the aim of mitigating low-order harmonics (which lead to current total harmonic distortion (THD) minimization). The following two proposed methods are studied in detail: 1) fixing phase angle displacement (PAD) between two VSIs to 120° while adjusting the modulation index (MI); and 2) fixing MI to the predetermined value (wherein low-order harmonics are highly mitigated) while adjusting PAD. Furthermore, the proposed approaches enhance efficiency by limiting the number of commutations within the switching interval. The paper also presents the mathematical approaches to accurately determine low-order harmonic components and switching losses for dual-VSI structure. The experimental setup, including dual-VSI and open-end induction motor, is assembled in the laboratory to evaluate performance of the proposed method. Finally, the simulation results, carried out in the MATLAB/Simulink environment, are found to be in close agreement with experimental data. [ABSTRACT FROM AUTHOR]

Magnetically coupled impedance-source (MCIS) networks are recently introduced impedance networks intended for various high-boost applications. It employs coupled magnetic in the circuit to achieve higher voltage gain. Various MCIS networks have been proposed in the literature for myriad applications; however, due to effective role of system modeling in the closed-loop controller design, this paper is allocated to small-signal modeling and analysis of MCIS converters. The modeling is performed by means of the circuit averaging and averaged switch technique. A generalized small-signal derivation is demonstrated for pulse width modulation (PWM) MCIS converters and it is shown that the derived transfer functions can simply be applied to Y-source, Γ-source, and T-source impedance networks. Various transfer functions for capacitor voltage, output voltage, magnetizing current, input and output impedance are derived and have been validated through frequency and dynamic responses of computer simulation results. In addition, a comprehensive analysis has been done for all mentioned PWM MCIS converters regarding their circuit parameters. Furthermore, the effect of considering the equivalent series resistances of capacitor and inductor on the stability margin of MCIS converters is revealed in this paper. Finally, in order to validate the derived transfer functions and to consolidate the perfumed analysis, experimental results are presented for all mentioned MCIS converters. [ABSTRACT FROM PUBLISHER]

This paper extends the high-frequency transformer isolation concept to the Z-source (ZS) ac–ac converters and introduces a new family of high-frequency transformer isolated (HFTI) ZS ac–ac converters. The proposed HFTI-ZS converters retain all the benefits of their existing nonisolated counterparts, such as providing a larger range of output voltage with buck–boost functionality, reversing or maintaining the phase angle, reducing the in-rush and harmonic currents, and improving reliability. In addition to these benefits, the high-frequency (20 kHz) transformer (HFT) in the proposed ZS ac–ac converters provides the electrical isolation and safety with high power density as it eliminates the need for bulky and heavy line frequency (50 or 60 Hz) transformer for galvanic isolation, in applications such as dynamic voltage restorers, etc. The dc-blocking capacitor added in series with the HFT results in only ac voltage applied across its windings, which avoids its saturation. Various ZS-based HFTI ac–ac converters are proposed in this paper, and to verify their operation and advantages, example of quasi-ZS (qZS)-based isolated ac–ac converter is considered in detail. The commutation strategy is also developed to achieve the safe commutation, which avoids the current and voltage spikes without using any RC snubber. A 200-W laboratory prototype of HFTI-qZS ac–ac converter is fabricated and experiments are performed to validate the advantages of the proposed ac–ac converters. [ABSTRACT FROM PUBLISHER]

Based on the Z-source inverter, this paper proposes a novel commutation torque ripple reduction strategy for brushless DC motor (BLDCM). The proposed strategy employs the same modulation mode in both the normal conduction period and the commutation period, and the commutation torque ripple is reduced by regulating the shoot-through vector and active vector duty cycles. The proposed detection method acquires the end point of commutation by comparing the clamped terminal voltages with reference zero level, and the signal-noise-ratio of the detection is improved by avoiding the attenuation of the terminal voltages. Furthermore, a certain pulse width of the shoot-through vector can not only reduce the commutation torque ripple but also provide a new opportunity to detect the end point of commutation. Moreover, Z-source inverter provides the buck–boost ability for BLDCM drive system, then the dc voltage utilization can be improved, and the safety of the drive system can also be improved. In addition, this paper analyzes the terminal voltages during each vector. The experimental results verify the correctness of the theories and the effectiveness of the proposed approach. [ABSTRACT FROM PUBLISHER]

AC voltage regulation is required in both the domestic and industrial sectors to avoid undesired effects from random voltage variations of the power supply. The paper introduces an ac voltage stabilizer/converter (ACVS) that is based on a controllable autotransformer technology. The proposed ACVS offers a specified strategy of voltage regulation, less harmonics, and low cost. The paper explains the operating principle of the ACVS and derives its nonlinear mathematical model. To ensure the desired performance of the ACVS while it is subject to uncertain input voltage and load variations, an optimal control strategy is designed. It is achieved via transforming the ACVS model extending with fictive axis emulation into a rotating reference frame and the linearization of the model via specific orientation of the reference frame and introducing a linear control action. Operation of the ACVS is simulated under different disturbances due to load and grid voltage changes, and compared to voltage stabilization with application of I and PI controllers. Experimental results are presented to demonstrate the voltage regulation technology. [ABSTRACT FROM PUBLISHER]

In several electrical dc–ac power conversions, the ac output voltage is higher than the input voltage. If a voltage-source inverter (VSI) is used, then an additional dc–dc boosting stage is required to overcome the step-down VSI limitations. Recently, several impedance source converters are gaining higher attentions [1], [2], as they are able to provide buck-boost capability in a single conversion stage. This paper proposes the merging of the boost stage and the VSI stage in a single stage dc–ac power conversion, denoted as split-source inverter (SSI). The proposed topology requires the same number of active switches of the VSI, three additional diodes, and the same eight states of a conventional space-vector modulation. It also shows some merits compared to Z-source inverters, especially in terms of reduced switch voltage stress for voltage gains higher than 1.15. This paper presents the analysis of the SSI and compares different modulation schemes. Moreover, it presents a modified modulation scheme to eliminate the low frequency ripple in the input current and the voltage across the inverter bridge. The proposed analysis has been verified by simulation and experimental results on a 2.0-kW prototype. [ABSTRACT FROM PUBLISHER]

This paper presents a novel spectral analysis technique for multilevel modulation. Conventionally, such analyses use a double Fourier series technique, but this approach can become intractable when complex reference waveforms (e.g., multilevel space vector offsets) and regular sampling processes are considered. In contrast, the strategy proposed in this paper separates the multilevel pulse width modulation (PWM) waveform into a spectral image of the reference, and sideband basis functions which are then expanded using a one-dimensional Fourier series. The coefficients of this Fourier series are defined by a one-dimensional Fourier integral that is simpler in form compared to the corresponding double integral associated with the double Fourier series. This analysis technique naturally incorporates regular sampling, and a discrete formulation is developed that enables complex PWM reference waveforms, including centered space vector offsets, to be solved. Results of this analysis are validated against previously published multilevel inverter double Fourier series results and matching switched simulations. [ABSTRACT FROM AUTHOR]

The increasing interest in multiphase drive systems has led to the extension of inverter topologies and pulse width modulation (PWM) methods from three-phase to multiphase occasions. Carrier-based PWM (CPWM) dominates space vector PWM when the phase number increases, because of its simple computation and modular implementation. Although intensive work has been done on modifying PWM methods to reduce the common-mode voltage (CMV), not enough work has been done on CPWM methods with CMV reduction for multiphase drives. This paper extends the phase-shifted sinusoidal PWM (PS-SPWM) method for five-phase and six-phase two-level voltage-source inverters (VSI) and employs the intersection-plotting method and Fourier analysis to reveal the nature of the CMV. Both experiment and simulation results comply with theoretical analysis that compared with the conventional SPWM, the PS-SPWM can effectively reduce the CMV in peak-to-peak value and RMS value, though it leads to a higher phase current distortion. In addition, the hardware realization of PS-SPWM for multiphase inverters by a distributed control system is presented in this paper. [ABSTRACT FROM AUTHOR]

There have been several advanced topologies proposed by the community for micro-inverter applications. However, many such applications suffer from unwanted second-order harmonic current ripple at dc input. Moreover, in the absence of suitable passive filter or ripple compensator, the second-order harmonics ripple may propagate into the dc source. This results in several problems to the system, related to system efficiency, life, cost, size, reliability, and stability. This paper proposes an adaptive sliding-mode controller to shape the output impedance of the boost-circuit of quasi-switched boost inverter such that the propagation of the ripple from dc link to the dc-input source is resisted. The quasi-switched boost inverter is one of the advanced and suitable topologies for the micro-inverter applications. The adaptive nature of the proposed controller improves the transient performance of the system at the line–load transients unlike some existing solutions, which affects dynamics adversely to achieve ripple mitigation objective. The controller ensures voltage regulation within ${5\%}$ at dc link. The proposed control technique is verified using a lab-prototype of 500 W quasi-switched boost inverter. [ABSTRACT FROM AUTHOR]

In this paper, a new class of bidirectional partial-resonance power converters is presented. The proposed family can be configured to interface single- or multi-port dc, single- or multi-phase ac systems at input-side and/or output-side. The proposed family offers a very modular structure, which can lead to cost reduction from a common designed module. In this converter, which accomplishes power conversion in a single stage, a small inductor placed in series with the input and output switch-bridges forms the link. This small link inductor is responsible for transferring power between different ports of the system. The proposed topologies can operate in buck, boost, and buck–boost modes of operation to step up and/or step down the voltage. In buck–boost mode of operation, the converter is controlled such that the power is entirely transferred through the link inductor; whereas, in buck or boost modes of operation only a fraction of the power is transferred through the link inductor, and the remaining power is directly transferred from input phases to the output phases. Galvanic isolation, which is typically a prominent factor contributing to power density of a converter, can be provided by means of a compact and lightweight single-phase high-frequency transformer added to the link. In comparison with earlier generations of partial-resonance inductive-link power converters, in the proposed converter, the level of link peak current and consequently power-loss, as well as voltage and current stress of switches are dramatically decreased. A very small film capacitor can be placed in parallel with the link inductor to facilitate zero-voltage-switching (ZVS) operation for all the switches/diodes. Apart from increasing the overall efficiency, minimized dv/dt stress and improvement in power density are achieved by adding the link capacitor. The proposed converter employs four-quadrant switches, i.e., bidirectional-conducting bidirectional-blocking switches, and charges the link inductor in both positive and negative directions in each cycle. In view of this, better utilization of the link inductor and lower total harmonic distortion (THD) are offered. Furthermore, two distinct switching algorithms are developed for the proposed family of converters. In this paper, the detailed behavior of the proposed family is investigated analytically, and simulation and experimental results are presented to evaluate the performance and effectiveness of the proposed converter. A low-power proof-of-concept prototype with input voltage of 59 V/161 V, load voltage of 178 V/73.5 V, maximum switching frequency of 4.9 kHz/3.65 kHz at 215 W/450 W in a step-up/step-down operation is considered for the experimental verification. [ABSTRACT FROM AUTHOR]

High step-down dc/dc converters are widely utilized in telecom and modern industrial applications. Due to the high step-down ratio, conventional Buck converter cannot provide satisfactory performance. To solve this problem, quite a few new topologies have been proposed to improve the performance of high step-down dc/dc converters, such as series-capacitor Buck (SC-Buck) converter, 3-level Buck converters, tapped inductor Buck converters, and LLC resonant converters. In this paper, the twice step-down benefit of SC-Buck converter and the zero-voltage switching benefit of series-capacitor tapped Buck (SC-TaB) converter are combined together to propose a new topology: interleaved series-capacitor tapped Buck (ISC-TaB) converter. To analyze the performance of the proposed ISC-TaB converter, the operation principles are discussed and the voltage conversion ratio is derived. In addition, to guide the design procedure and optimization, the current waveforms and voltage waveforms of the proposed ISC-TaB are derived. In order to verify the performance of the proposed ISC-TaB, hardware prototype of the proposed ISC-TaB converter and conventional two-phase series-capacitor tapped Buck converter (2ph-TaB) are designed and tested. The application is targeted at telecom with 48-V input and 3.3 V/20 A output. The test results are compared between these two converters. A peak efficiency of 95.6% is achieved on the proposed ISC-TaB and the efficiency of the ISC-TaB over all load range is at least 1% higher than that of 2ph-TaB. [ABSTRACT FROM AUTHOR]

This paper presents a straight-forward method to compensate baseband distortion for regularly sampled pulsewidth modulation, for both sawtooth and triangular carrier, aimed at high-precision power electronics applications such as medical MRI and semiconductor lithography. The method adds correction signals to the modulator input to mitigate the distortion, which is computationally lightweight, and pseudo-code is given to simplify implementation. Measurements are conducted, which confirm the improvements offered by the method. It is shown that baseband distortion can be reduced by upto 60 dB. This improves the linearity and reduces audible noise of power converters. [ABSTRACT FROM AUTHOR]

In a three-stage cascaded modular solid state transformer (CMSST), unbalanced dc bus voltages at the output of cascaded multilevel rectifier is a common issue due to inevitable parameter mismatch in stage-2. To balance the dc bus voltages, either voltage balance control (VBC) in stage-1 or power balance control (PBC) in stage-2 is necessary. In this paper, an in-depth theoretical analysis to investigate the input power quality of the CMSST in the presence of voltage and PBC schemes is presented. The grid-side multilevel voltage of the CMSST is analyzed to highlight the limitation of using VBC in stage-1. It is then mathematically proven that the switching frequency based harmonics in the grid current are significantly reduced by using the PBC in stage-2. Simulation studies of a 3.3-kV, 50-kVA CMSST are carried out using the PLECS software to substantiate the proposed analysis. Experimental verifications are performed on a 750-VA single-phase CMSST laboratory prototype for a 20% parameter mismatch in stage-2. It is found that the grid current total harmonic distortion (THD) is reduced from 6.65% to 3.8% at 50% load by using PBC in stage-2. This paper provides guidelines for the designer to choose appropriate balance controllers for the CMSST. [ABSTRACT FROM AUTHOR]

The six-phase asymmetrical induction motors (SPIMs) are employed for high power medium voltage drive due to its attractive features of reduced stator copper loss, lower torque pulsation, higher torque per ampere, and higher reliability. In this paper, analysis of carrier-comparison-based pulse width modulation (PWM) techniques namely sinusoidal PWM and double zero-sequence injection PWM are carried out from a space vector perspective. Furthermore, new space vector pulsewidth modulation (SVPWM) techniques are developed by modifying the switching sequences of carrier-based PWM techniques. A comprehensive analysis of these PWM techniques is carried out in terms of harmonic flux trajectories, squared harmonic flux, and harmonic distortion factor (HDF). As a result, modified SVPWM technique namely 6ΦSVM3 is found superior to aforesaid PWM techniques, which significantly reduces HDF and provides lower current total harmonic distortion (THD). The experimental results of aforementioned PWM techniques are obtained and verified from six phase asymmetrical induction motor fed by dual two-level 3ΦVSIs. This paper is also accompanied by a video file of experimental test setup recorded while 6ΦSVM2 is running on SPIM. [ABSTRACT FROM AUTHOR]

Core loss estimation of filter inductors is increasingly important for modeling and optimizing high-frequency, high-efficiency, and high-density pulsewidth modulation (PWM) power electronic converters. However, data provided by inductor core manufacturers are insufficient for core loss estimation in PWM converters, particularly in the case of customized gapped inductors. This paper presents a whole process of characterizing and estimating the core loss of a customized high-current gapped inductor for PWM converters. To excite the inductor for the B–H loop measurement, a test circuit formed by a half-bridge structure is proposed, which has the ability to compensate the asymmetric rectangular voltage on the inductor caused by the device voltage drops. To overcome the other challenges raised by a high excitation current, a refined discontinuous test procedure, triple pulse test, is proposed to reduce the requirements of the high-current test setup (thermal stress, current–time stress for current probes, capacity of dc sources, etc.). For practical purposes, a user-friendly loss map approach is proposed involving only time-domain and electrical variables to replace magnetic variables to enable the straightforward loss mapping process and core loss calculations. Presented experimental results show consistency between the estimated inductor loss and measured values. Overall, the proposed testing approach can be easily implemented on the user's side to develop a loss map of a given inductor. The established core loss map enables the users to accurately and rapidly estimate the core loss of a tested inductor for given PWM waveforms. [ABSTRACT FROM AUTHOR]

This paper proposes a novel four-leg converter topology and the corresponding SVPWM strategy for a reluctance machine with DC-biased sinusoidal winding current. Compared with the traditional open-winding inverter topology, the number of the power devices and gate driver required for the four-leg converter topology are reduced by one-third, and the power loss is reduced. With the proposed four-leg converter, the cost of the motor drive is reduced and the power density is improved. The vector control and modulation models of the proposed four-leg converter are presented to control the winding current with both AC and DC components. With the proposed four-leg SVPWM strategy, the four-leg converter can achieve the same DC voltage utilization as an open-winding inverter. In addition to the ability to generate αβ-axis voltages, as same with conventional SVPWM, the proposed SVPWM can also generate γ-axis voltages without generating additional zero-sequence alternating voltages on the stator windings. The validity of the proposed converter and the corresponding modulation strategy has been demonstrated by simulation and experiment. The power loss and performance of the four-leg converter are compared with the traditional converter. Contrasting experiments show that the proposed topology can reduce power loss by about 15% at rated operation and achieve the same performance as open-winding inverters. [ABSTRACT FROM AUTHOR]

Inductor current is an important feedback parameter in synchronous buck converters (SBCs). It is used for overcurrent protection, current sharing among interleaved modules, and current-mode feedback regulation, among others. While implementing a digital controller, inductor current is sensed and fed into the controller through a high sampling frequency analog to digital converter (ADC). As the switching frequency of the converter becomes higher, the need for an even higher sampling frequency ADC also goes up, which is a distinct disadvantage in terms of the overall cost. This paper discusses a simple current estimation technique that avoids use of any expensive current sensor and high sampling frequency ADCs. The paper shows that in a buck converter, inductor current can be estimated by tracking the width of the switch node voltage. Implementation and limitations of the proposed current estimation scheme are discussed in detail. The proposed method is validated using a 3.3 V–15 A SBC prototype and results show the estimation technique is accurate within 5% with a converter switching frequency of 800 kHz. In order to prove the effectiveness of the technique in feedback regulation, the current estimation technique is used to implement average current mode and hysteretic current mode control on a SBC. To prove the effectiveness of the proposed current estimation scheme, it is used in closed-loop control of the SBC to verify the dynamic responses, such as start-up transient, step change in load, and reference. [ABSTRACT FROM AUTHOR]

This paper presents new space vector pulsewidth modulation (PWM) strategies for a single-phase three-level buck-boost neutral point clamped inverter coupled with impedance-source (IS) network. These strategies can be implemented for systems with any IS network with neutral point. The case study system is based on the quasi-Z-source inverter with continuous input current. To demonstrate an improved performance, the strategies are compared with a traditional PWM strategy. The advantages lie in reduced switching number, without output voltage quality distortion. The simulation and experimental results confirm the theoretical predictions. [ABSTRACT FROM AUTHOR]

This paper presents a novel bidirectional series resonant converter for energy storage systems (ESS). Conversion between a dc energy storage device and an ac grid has grown in importance because of the renewable energy generators and ESS used in microgrids, which usually use batteries or supercapacitors as storage devices in order to provide different services and improve the quality and reliability of the grid. This novel converter avoids the need to have two converting stages: one for converting the energy from the storage device to a regulated dc value, and the other for converting the regulated dc to the ac output. Conversion occurs via a modified dc/dc dual-bridge series resonant converter. The output bridge of the converter is attached to the input bridge through a resonant branch and a high frequency (HF) transformer, and it is also attached to the ac link through an output filter. Therefore, two ac power signals are mixed in the output bridge: a HF signal, which maintains the dc link capacitor voltage, and a low frequency power signal, which transfers energy to the grid. This paper details the different working modes of the converter and presents a 3000 W prototype that validates the design. [ABSTRACT FROM AUTHOR]

Due to the advantages of high torque density and compact mechanical structure, brushless dual-mechanical-port dual-electrical-port (BLDD) permanent magnet (PM) machine has become a promising alternative in series–parallel hybrid electrical vehicles (HEVs). However, two sets of windings in the same core may also result in flux cross coupling, which deteriorate control performance. Through special design of the magnetic circuit, the two sets of windings in the stator side are decoupled. In this paper, the mathematical model of the BLDD-PM machine is analyzed first. Then, based on the energy management system and the model of the machine, the decoupled vector control algorithm for the outer and inner rotor is developed. Next, common operation states under city road condition for hybrid vehicles have been summarized. According to the operation state of HEV, the power flow analysis in the BLDD-PM machine system has been done. To validate the analysis results, experimental test under different operation condition has been conducted. Test results show good control performance of the BLDD-PM prototype and verify the correctness of analysis. [ABSTRACT FROM AUTHOR]

In this paper, a new structure for a nonisolated boost dc–dc converter is proposed. The proposed converter generates higher voltage gain than some conventional nonisolated boost dc–dc converters. In this paper, the voltage and current equations of the elements and voltage gain in continuous conduction mode and discontinuous conduction mode are extracted. Then, the critical inductance converter is extracted and the current stresses in the switches are calculated. To achieve high voltage gain, a generalized structure based on the proposed structure generates for dc–dc converters. Meanwhile, the root mean square current relations of devices are obtained for an extended structure. Finally, the results of PSCAD/EMTDC software and laboratory prototype are used to reconfirm theoretical concept. [ABSTRACT FROM AUTHOR]

This paper proposed a novel method for two-segment three-phase motor to eliminate the harmonics nearby pulsewidth modulation (PWM) frequency. Due to PWM technique and switching losses considerations, ear-piercing high-frequency electromagnetic noise in drive system is common. By using magnetically coupled inductors (MCIs) and interleaved technique, the proposed novel method is able to remove the high-frequency harmonics located nearby the PWM frequency and other odd multiples in two-segment three-phase motor. With this method, the unpleasant acoustic noise could be removed when the PWM frequency is selected near 10 kHz. The size of MCIs mainly depends on the PWM frequency harmonic currents rather than the fundamental frequency currents. Thus, its size is very small compared with LC filter. Moreover, this method remains the control dynamics of two-segment three-phase motor without additional inductance for fundamental-frequency currents. The shift phase of two inverters PWM carriers is π, which is simple to implement. Finally, the effectiveness of the proposed method is verified by experimental results. [ABSTRACT FROM AUTHOR]

Modular multilevel converters (MMCs) represent an emerging topology in medium-voltage (MV) and high-voltage applications. But for MV variable-speed motor drives, the MMC faces the challenge of large capacitor voltage ripple at low speeds. Delightfully, a hybrid MMC (HMMC) has proved to be potential in MV motor drives, since this topology has a lower capacitor voltage ripple and does not introduce any common voltage to the motor. This paper proposed a method to decrease the average capacitor voltage of the HMMC, which can effectively drive the motor at very low speeds without significantly increasing the submodule (SM) capacitance. Moreover, the selection of average capacitor voltage and the dimension of the SM capacitance are presented. Simulation and experimental results verify the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

This paper proposes a general control scheme for the dual-input three-level inverter, which comes from a neutral point clamped three-level inverter. It can be used for photovoltaic (PV) systems or battery storage systems with two dc sources. The dual-input three-level inverter can be connected with two PV arrays, which are able to realize maximum power point tracking independently. First, the dynamic model of the dual-input three-level inverter is established, which describes the relationship between the dual-input voltages and the duty cycle. After discussing the control theory of the dual-input voltages, a typical control scheme is proposed. The design of a control loop is introduced in details. Afterward, modulation and restriction of the proposed method are discussed. Finally, experiment on a 125 kW dual-input three-level PV inverter is implemented to verify the validity and feasibility of the proposed method. [ABSTRACT FROM AUTHOR]

This paper presents a two-segment motor system powered by two inverters with phase-shift pulsewidth modulation (PWM) to fulfill the purpose of low-torque ripple and vibration noise. Different from conventional multi-inverter structure, the inverters for this type of machine are electrically isolated between each other. First, the concept of multisegment machine is presented and the basic operation principle is analyzed with finite-element analysis (FEA) method. Then vibration caused by the switching device in machine is investigated and the control model of a two-segment motor is developed. Further, the principle of carrier phase-shift PWM is illustrated with the vibration analysis. Carrier phase shift can generate interleaved torque and force on the rotor for the two groups of windings in the machine and cancel each other for certain harmonics. Then simulation of control strategy for this type of machine has been done in MATLAB. Finally, based on the concept and principles mentioned before, a two-segment motor with its drive system is fabricated. Both the test of torque ripple and the vibration of the motor have been significantly improved. Compared with a normal three-phase motor driven by a paralleled inverter with interleaving, the proposed approach is with comparable vibration reduction but without using extra coupled inductors. [ABSTRACT FROM AUTHOR]

With the increasing renewable energy injected into the electrical distribution grid, the reliability of the power converter is gaining importance for the power system. In order to address the wear-out caused failure mechanisms of power semiconductors and thereby increasing the reliability, this paper aims at balancing the thermal stress caused during operation between different power converters in a wind park. An active thermal control strategy based on the discontinuous pulsewidth modulation is proposed for reducing the thermal stress of the semiconductors under a fluctuating power profile, while maintaining good power quality. The proposed method is introduced for multiple converters, which are connected to the same grid feeder and its impact on the lifetime of the semiconductors is investigated analytically. Finally, the effectiveness of the proposed method is experimentally validated for a two-level voltage source converter. [ABSTRACT FROM AUTHOR]

This paper presents a robust deadbeat predictive power control (DPPC) for pulsewidth modulation (PWM) rectifiers with the consideration of parameter mismatches under unbalanced grid conditions. First, conventional DPPC is modified to extend its application to both ideal and unbalanced grid conditions. Second, a tracking error of the modified DPPC with inaccurate grid-side impedance is analyzed. Third, a discrete-time power disturbance observer (DPDO) is designed to achieve accurate power control with mismatched parameters. The designed DPDO can predict complex power at the next sampling instant and estimate system disturbance simultaneously. Therefore, the DPDO can contribute to eliminate the steady-state tracking error resulting from disturbances caused by inaccurate parameters and compensate one-step delay in digital implementation. Although satisfactory steady-state performance can be obtained with modified DPPC and DPDO, transient performance still deteriorates significantly with an inaccurate value of the grid-side inductance. Thus, an online adaptive method to estimate mismatched inductance is finally developed based on the proposed DPDO. Both DPPC and DPDO are implemented in the stationary reference frame without coordinate transformation. Theoretical analysis confirms that the proposed DPDO can track disturbance without phase lag or magnitude error. Experimental tests and comparative studies with a prior DPPC on a two-level PWM rectifier validate the effectiveness of the proposed scheme. [ABSTRACT FROM AUTHOR]

The duty cycle in digital pulse width modulation (DPWM) whose time resolution is as high as hundreds of picosecond will be increased since the propagation delays of internal logics and interconnects are superimposed on the on-time. The duty-cycle-increment phenomenon affects the regulation performance of converters, especially when the delays are the same magnitude level as switching period. In this paper, a compensation method based on tool command language commands is used to offset the propagation delays. Furthermore, the DPWM applies a counter, phase locked loop, and carry chain to constitute segmented delay-line, while it maintains a wide duty cycle range and a high time resolution. This DPWM is implemented by a low-cost field-programmable gate array Cyclone IV. It achieves a good linearity where R2 is 0.9949 for an 11-bit, 9.375 MHz switching frequency DPWM. The duty cycle range is from 1.52% to 97.81%. Meanwhile, the time resolution and average duty difference are 53 ps and 3.08%, respectively. [ABSTRACT FROM AUTHOR]

This paper proposes a novel discontinuous pulse-width modulation (DPWM) method to reduce the current harmonics and improve the system efficiency for a single-phase three-level neutral-point clamped inverter. In single-phase inverters, the unipolar pulse-width modulation (UP-PWM) method is commonly used. However, this method has the disadvantage of power losses due to numerous switching operations. Conventional DPWM methods reduce the power losses and improve efficiency but increase the current total harmonic distortion (THD). To overcome these weaknesses, this paper proposes a hybrid DPWM switching method combining two PWM methods: the UP-PWM method and the conventional DPWM method called one-pole clamped PWM method. Since the proposed DPWM method offers all the advantages of both PWM methods, the optimal performance—with regard to the power losses and current THD—is obtained. The combination of two PWM methods is investigated by analyzing the power losses and current THD. Based on the analysis, the process determining the optimal operating condition is introduced. The effectiveness of the proposed DPWM method is demonstrated through simulations and experiments. [ABSTRACT FROM AUTHOR]

In this paper, a new pulse width modulation (PWM) scheme and commutation method is presented for one phase loss operation of three-phase isolated buck matrix-type rectifier. With the proposed PWM scheme, the maximum allowable voltage gain for one phase loss operation can be achieved, which permits the continuous operation of the converter to deliver two-third of the rated power and regulate the output voltage with maximum output voltage drop less than 5% of nominal output voltage. In addition, with the proposed commutation method, a safe transition from one phase loss operation to normal operation and vice versa can occur with minimum commutation steps (two-step) under zero-voltage switching condition. The performance of the proposed PWM scheme and commutation schemes with one phase loss operation is evaluated and verified by simulations and experiments on a 5 kW prototype. [ABSTRACT FROM AUTHOR]

Single-loop current control is an attractive scheme for the LCL-type grid-connected inverter due to its simplicity and low cost. However, conventional single-loop control schemes, which command either the inverter current or the grid current, are subject to the specific resonance frequency regions. The weighted average current control, which splits the filter capacitor into two parts (in form of an LCCL filter) and commands the current flowing between these two parts, is independent of the resonance frequency, but on the other hand, it is limited by the poor sensitivity to the grid impedance variation and weak stability in the grid current. These limitations are comprehensively explained in this paper and then addressed by identifying that the single-loop weighted average current control is equivalent to the dual-loop grid current control with an inherent capacitor current active damping. By tuning the capacitor split proportion as a second degree of freedom, an optimal damping performance that is robust to the grid impedance variation can be naturally achieved using only the inherent damping. Thus, no extra damping is required, and the single-loop structure with only one current sensing turns to be adequate. Moreover, for convenience of practical implementation, an improved LCCL filter configuration is proposed to allow the use of two equal nominal capacitances for the split capacitors. Finally, experiments are performed to verify the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

In order to incorporate the advantage of the $V^{2}$ control scheme and the benefits of digital implementation, this paper proposes a digital $V^{2}$ control with hybrid capacitor current ramp compensation, which includes the estimated output capacitor current ramp and the external ramp. Since capacitor current responds to the load change immediately, the proposed method has faster transient response than either digital inductor current compensation or external ramp compensation. The proposed estimator does not require high sampling rate and avoids the current ramp distortion due to the parasitic resistance and inductance. The small-signal model is derived by describing function to understand the dynamic characteristics of the proposed control scheme. The model provides design criteria of the current feedback gain and the external ramp slope. The effectiveness of the proposed control architecture and the current ramp estimator is verified by simulation and experimental results. Compared with the benchmark, the proposed control has 70% reduction on settling time and 20% reduction on undershoot deviation. [ABSTRACT FROM AUTHOR]

For the purpose of reducing cost and volume, as well as to increase reliability in hostile environments, techniques of reconstructing three-phase current through a single current sensor have been reported for a three-phase alternating current motor vector control system. Based on the phase current reconstruction method, this paper proposes a novel open-circuit fault diagnosis method for the low-power voltage source inverter in the three-phase permanent-magnet synchronous motor drive. Other than sampling the single dc-link current sensor, the zero voltage vector sampling method (ZVVSM) is adopted to implement the fault diagnosis. By placing the single current sensor at a special position, ZVVSM is able to sample current during the two zero voltage vectors and reconstruct the three-phase currents. The reconstructed three-phase currents are used to generate the diagnostic variables that can detect and locate the faulty power switches. The PWM modulation strategy remains unchanged in this method and the reconstructed phase currents are with less waveform distortion and less harmonic contents, which are suitable for the fault diagnosis. The effectiveness of the proposed method is verified by experiments. [ABSTRACT FROM AUTHOR]

Application of pulse width modulation (PWM) is known to produce sideband effects. The accuracy of the models of dc–dc converters can be improved if essential information of the sideband effects of PWM can be incorporated. In this paper, the aliasing effect of the sideband components on the closed-loop control is analyzed, and an effective representation of the transfer function of the pulse-width modulator is derived. Applying this transfer function to the dc–dc converter, an extended-frequency-range small-signal model is obtained, which can be conveniently used for deriving the loop gain of a PWM-controlled dc–dc converter. Furthermore, for wideband control applications, the large switching ripple in the modulation signal necessitates adjustment of the representation of the gain of the pulse-width modulator, which is dependent on the controller. Despite being highly accurate for stability assessment, the extended-frequency-range model is relatively complex after incorporating the effects of the sideband components and the large switching ripple. An approximate approach is introduced to simplify the loop gain expression and to provide physical insights into the effects of the sideband components and large modulation ripple amplitude. Experimental verification of the extended-frequency-range model is provided for a buck converter and a boost converter. [ABSTRACT FROM AUTHOR]

This paper proposes a vector-controlled squirrel cage induction motor drive with synchronized sinusoidal pulse width modulation (PWM) for traction applications. In traction applications, switching loss in insulated-gate bipolar transistors is very important, and hence, a switching frequency of few hundred hertz is used in these devices. A triangular carrier comparison-based synchronized sinusoidal PWM for medium-voltage inverters with low switching frequency (less than 500 Hz) is proposed in this paper. To have very good dynamic behavior of the synchronization scheme, the triangular carrier is generated from the instantaneous voltage references in a phase-locked manner. A synchronous carrier-based overmodulation scheme that ensures linearity between the reference voltage and the fundamental motor terminal voltage is also proposed. An inverse gain-based linearization method is used to match the reference and inverter output voltage fundamental. This overmodulation strategy fails at the zone of high values of modulation index and a reference modification approach is used in that zone. The proposed PWM and overmodulation schemes integrate methods of field weakening and harmonic current estimation available in the literature and propose a consolidated scheme, which ensures good dynamic response with wide speed variation for rotor flux-oriented induction motor drive. The scheme is experimentally verified and the results are presented. [ABSTRACT FROM AUTHOR]

This paper provides theoretical and experimental discussions on an optimal carrier frequency for a phase-shifted pulsewidth modulation modular multilevel cascade converter for grid connections. The theoretical discussion concludes that a ratio of the optimal carrier frequency with respect to the supply (ac) frequency is 5/2. A three-phase downscaled front-to-front system is designed, constructed, and tested to confirm validity of the theoretical discussion. It consists of a pair of three-phase modular multilevel cascade converters rated at 400 Vdc and 10 kW, where the carrier frequency is set to 450 Hz and the ac frequency to 180 Hz, that is, their ratio is equal to 5/2. Moreover, simulated waveforms are compared to experimental ones under the same operating conditions. Both experimental and simulated waveforms agree well with each other not only in steady states but also in transient states. [ABSTRACT FROM AUTHOR]

In this paper, a high-performance grid simulator based on a parallel structure fractional repetitive control scheme is employed to emulate various operation scenarios of power grids for testing power products. In this paper, a simple fractional repetitive control scheme is proposed for grid simulators to achieve high-accuracy tracking performance. Using parallel branches, the proposed repetitive controller can flexibly select the interested harmonics for compensation, and independently, tune the convergency rate at selective harmonic frequencies. Compared with the conventional repetitive control, the proposed control scheme achieves faster transient response. Moreover, the number of delay units required in the proposed repetitive controller is reduced to at least half of that in a conventional repetitive controller. Design process and stability criteria are presented in details. A set of experimental results is provided to verify the effectiveness of the proposed approach. [ABSTRACT FROM PUBLISHER]

This paper presents an alternative approach to address the control and modulation problem of single-phase three-level converters applied in the high-speed railway electrical traction drive system. Following the principle of deadbeat predictive direct torque control of ac motors, this paper discusses an improved direct power control (DPC) method based on a deadbeat active and reactive power prediction technique. Comparing with the conventional PI-based DPC scheme, the proposed deadbeat predictive DPC scheme can provide these advantageous features: lower current harmonics and THD index, lower active and reactive power ripples, and fewer adjusted parameters. Moreover, compared with PI-based DPC with the PI parameters optimization, this approach can also easily obtain fast dynamic response but without the main voltage orientation. A single-phase three-level space vector pulse width modulation (SVPWM) with inherent neutral-point voltage balancing capability is adopted, which can be combined with DPC scheme as an overall control and modulation system. A series of simulation and experimental tests have been conducted to demonstrate an excellent performance of the deadbeat predictive DPC. In addition, the neutral-point-voltage balancing ability of the adopted SVPWM method has been verified. [ABSTRACT FROM PUBLISHER]

In order to solve the neutral-point voltage unbalancing problem for three-level inverters, this paper proposes a method to balance the neutral-point voltage for three-level inverters with variable modulation wave offset sinusoidal pulse-width modulation (SPWM) control. Based on the mathematical expressions of neutral-point voltage unbalancing, the factors are studied, which affect the fluctuation of neutral-point voltage. Theoretically the mathematical expressions of the neutral-point voltage with the proposed method are derived, and the mathematical relationship between the fluctuation of neutral-point voltage and the adjusting offset of modulation wave is studied. This proposed method realizes controlling the neutral-point voltage balance by dynamically calculating the offset superimposed to the modulation wave based on SPWM (DCOSPWM). This DCOSPWM method is very simple, which has good steady-state performance and is easy for digital implementation. The simulation results verify the correctness of the theoretical analysis in this paper, and the feasibility and effectiveness of this method is verified by the experiments in the experimental platform of neutral point clamped three-level inverters based on digital signal processor (DSP)-complex programmable logic device (CPLD). [ABSTRACT FROM AUTHOR]

According to the number of segments, the space vector modulation (SVM) can divide into conventional SVM sequence (CSVMS) and special SVM sequence (SSVMS). It is well known that SVM can be equivalently realized by carrier-based pulse width modulation (CBPWM) with a zero component injection in both two-level and three-level inverters. For eight segment CSVMS in three-level inverters, many papers have ever got the injected zero component equation. But similar approach does not work for SSVMS, which has more than eight segments, e.g., 10, 12, or 14. What more, the accurate injected zero component has never been achieved so far. To solve above problems, therefore, a generated decomposition method of modulation wave has been proposed in this paper. By strict theoretical derivation, the same correlation can be extended to SSVMS and the corresponding zero component expression can be acquired. Based on this method, this paper puts a lot attention on the essential feature explanation, mathematical proof, and gives a detailed process to get the zero component equation, using it can realize SSVMS by CBPWM. The simulation and experimental results illustrate that the generated decomposition method of modulation wave is correct, and the unified theory of CBPWM and SVM is verified. [ABSTRACT FROM AUTHOR]

This paper presents an integrated solution for a photovoltaic (PV)-fed water-pump drive system, which uses an open-end winding induction motor (OEWIM). The dual-inverter-fed OEWIM drive achieves the functionality of a three-level inverter and requires low value dc-bus voltage. This helps in an optimal arrangement of PV modules, which could avoid large strings and helps in improving the PV performance with wide bandwidth of operating voltage. It also reduces the voltage rating of the dc-link capacitors and switching devices used in the system. The proposed control strategy achieves an integration of both maximum power point tracking and V/f control for the efficient utilization of the PV panels and the motor. The proposed control scheme requires the sensing of PV voltage and current only. Thus, the system requires less number of sensors. All the analytical, simulation, and experimental results of this work under different environmental conditions are presented in this paper. [ABSTRACT FROM AUTHOR]

Pulse width modulation schemes are aimed at adjusting the fundamental component while reducing the harmonic content of an inverter output voltage or current. This paper addresses the topic of optimal inverter operation in reference to a given objective function. The objective function could embody either a single performance criterion, such as voltage or current total harmonic distortion (THD), or a weighted sum of multiple criteria. The proposed method ensures primacy of the chosen solution while imposing no restriction over its modulation index. In particular, operating the inverter by the chosen solution would result in performances superior to any other modulation scheme commutating in an equal number of switching angles per fundamental cycle. The proposed method allows for the consideration of practical inverter constraints and prevents the possibility of impractical switching sequence. A detailed investigation of the method is given, accompanied by two practical cases minimizing, respectively, phase-voltage THD and line-current THD of a three-level inverter. Selected simulation and experimental results are presented to validate the theoretical part. [ABSTRACT FROM AUTHOR]

In this paper, an immune algorithm (IA)-based dead-time elimination PWM control strategy is proposed. For existing dead-time elimination applications, one of the major problems is the dead-time control around the zero-current-crossing points. To deal with this problem, this paper proposes a different PWM control method which first restricts the control sequence to a specified level around the zero-crossing zone. Also, the proposed method can improve the current waveform quality by using the IA approach and three-level control strategy. Compared with conventional dead-time elimination methods, this technique has the features of simple hardware requirement and adaptive control. Moreover, this control strategy effectively eliminates the effect of dead-time, while at the same time significantly reducing the total harmonic distortion of output current and improving the amplitude of output RMS value in different modulation indexes and loads conditions. To verify the analysis, an experimental platform based on DSP and field-programmable gate array is built. The simulation and experimental results are given to demonstrate the effectiveness and feasibility of this new method. [ABSTRACT FROM AUTHOR]

This paper discusses the voltage error caused by the dead time in voltage-source PWM converters. The theoretical analysis in this paper derives the nonlinear voltage error paying attention to the parasitic output capacitance in each switching device. The analytical result reveals that the turn-off current or the switching current ripple strongly affects the voltage error. In addition, it is clarified that the conventional compensation methods based on linear and three-level approximation are suitable under small and large current ripple conditions, respectively. A simple calculation method of current ripples in three-phase PWM converters is also developed to estimate the turn-off currents. Turn-off transition compensation method which is a new compensation method based on the analysis is developed and compared with three different conventional methods in experiments using a 200-V, 5-kW three-phase grid-connection converter. The proposed method exhibits a good compensation performance having a lower voltage THD than the conventional methods in all over the operating range. [ABSTRACT FROM AUTHOR]

A solid-state transformer is a three-phase ac/ac converter with a high-frequency transformer. Due to advanced features like high power density, on demand var support and frequency regulation, solid-state transformer is an enabling technology for the modern power distribution system. It can also find application in high-power-density motor drives. The single-stage solid-state transformer considered in this paper is capable of bidirectional power flow and open loop power factor correction. This topology uses a minimum amount of copper and has relatively few semiconductor switches. One major problem in this converter is the commutation of leakage energy which results in power loss, reduction in switching frequency, loss of output voltage, and additional common-mode voltage switching. This paper presents a source-based commutation strategy along with a novel modulation technique resulting in elimination of additional snubber circuits, minimization of the frequency of leakage inductance commutation, recovery of the leakage energy, and soft switching of the output converter. The topology and its proposed control have been analyzed. Simulation and experimental results confirm the operation. [ABSTRACT FROM AUTHOR]

This paper presents an in-depth critical discussion and derivation of a detailed small-signal analysis of the phase-shifted full-bridge (PSFB) converter. Circuit parasitics, resonant inductance, and transformer turns ratio have all been taken into account in the evaluation of this topology's open-loop control-to-output, line-to-output, and load-to-output transfer functions. Accordingly, the significant impact of losses and resonant inductance on the converter's transfer functions is highlighted. The enhanced dynamic model proposed in this paper enables the correct design of the converter compensator, including the effect of parasitics on the dynamic behavior of the PSFB converter. Detailed experimental results for a real-life 36 V-to-14 V/10 A PSFB industrial application show excellent agreement with the predictions from the model proposed herein. [ABSTRACT FROM AUTHOR]