Search

Efficiency, power quality, and reliability of SiC MOSFET-based voltage-source converters are significantly affected by the dead-time settings. The conventional fixed dead-time setting can induce large output voltage loss and additional energy loss due to the output capacitance of the SiC MOSFETs and the SiC Schottky barrier diodes or the freewheeling of the diodes, which will be more serious under high switching frequencies. This paper analyzes and models the detailed switching process of the SiC MOSFET half-bridge circuit when various dead-time settings are adopted. Based on the models, an optimal asymmetric variable dead-time (OAVDT) setting is proposed, which can avoid the discharging loss of the output capacitance and redundant freewheeling loss of the diode. The OAVDT setting is realized by adjusting the optimal dead-time in real time after the active device is turned off, which does not require any additional hardware circuits. The OAVDT setting can also reduce the output voltage loss to a certain level compared to the fixed dead-time setting. A three-phase two-level SiC MOSFET inverter has been built in the lab to verify the proposed OAVDT setting. Experimental results show a decrease of power loss by 22.5% with reduced output voltage loss compared to the fixed dead-time setting of 0.28 μs when the output power is 8 kW and the switching frequency is 40 kHz. The proposed OAVDT setting shows clear advantages over that of fixed dead-time setting, especially at light load and high switching frequencies. [ABSTRACT FROM AUTHOR]

Recent studies have proved that sustainable saturation operation of Ferrite Power Inductors (FPIs) allows reducing the inductor size and increasing the power density in Switch-Mode Power Supply (SMPS) applications. This paper discusses a new behavioral model for reliable prediction of ac power loss in FPIs, including the effects of saturation. The new model has been identified by means of the Genetic Programming (GP) algorithm combined with a Multi-Objective Optimization (MOO) technique, starting from large sets of power loss experimental measurements. The proposed ac power loss model uses as input variables the voltage and switching frequency imposed to the inductor by the SMPS operation, while the dc inductor current is used as a parameter expressing the impact of saturation. Such quantities can be easily determined for whatever converter topology and in real-world switching operation, thus confirming the readiness and the easiness-to-use of the proposed behavioral model. The results of experimental tests presented in this paper prove the reliability of the power loss predictions, also by correctly accounting for the impact of inductors saturation. [ABSTRACT FROM AUTHOR]

This paper analyzes the benefits of the active damping applied to transformerless three-phase grid-connected photovoltaic (PV) inverters using modified LCL (MLCL) filter for leakage current reduction. In comparison with passive damping techniques, the active damping can reduce the MLCL filter resonance peaks, improving the dynamic performance of the control system without addition of power losses. Besides these classical advantages, this paper demonstrates that the active damping also contributes for PV leakage current reduction, preserving the high-frequency attenuation of the MLCL filter. Additionally, an active damping for the inverter common-mode circuit is also proposed, reducing the low-frequency leakage current caused by the common-mode signal used to extend the inverter modulation index. Experimental results are given to demonstrate the leakage current reduction and the grid current control for a 10 kW PV inverter. [ABSTRACT FROM PUBLISHER]

This paper studies the need to include equalizing circuits in energy storage systems (ESSs), particularly in supercapacitor arrays. It evaluates the advantages and disadvantages of introducing these circuits in the system, and it presents a probabilistic study in order to show how much more energy can be stored by using an equalizing system. In addition, it evaluates several equalizing systems and presents a fast charging circuit that allows ESSs to charge at the same power as in the discharge process. The objective of the paper is to provide a guide for properly selecting an equalizing system when one is needed, for example, in electric vehicle or microgrid applications. [ABSTRACT FROM PUBLISHER]

High-frequency copper losses, or copper losses produced during switching in switching-mode power supplies, are very much related to variations of the magnetic field distribution within the core window. When operating at high frequency, the current flowing through the windings of a magnetic component experiences redistribution across the section of the conductor due to skin and proximity effects. Current redistribution depends not only on actual frequency, but also on conductor size and layer distribution. While previous works aim to optimize windings size by considering just the current flowing through that winding, this paper shows that, in most of the cases, current redistribution is strongly affected by the currents at the other transformer windings, which should also be taken into account. This paper derives a mathematical expression to calculate the evolution, in the time domain, of the magnetic field during the switching, which will be later used to obtain the current density distribution and copper losses in the component. An easy-to-calculate expression will be derived that allows magnetic windings to be analyzed and/or optimized, because losses are expressed as a function of the winding geometry and position. An application example is also included. All the equations derived are verified by comparing them with the results obtained from a differential equations solver, and with previous works when applicable. Experimental results are also provided. [ABSTRACT FROM AUTHOR]

The measurement of fast voltage and current transients of Silicon Carbide (SiC) devices requires high bandwidth (BW) probes. Commercially available voltage and current probes can be expensive, and, in addition, the delay introduced by them must be compensated to achieve a proper time alignment (de-skew). Determining this de-skewing value is not a trivial task. In this paper, a simple and affordable measurement method is presented for the simultaneous measurement of the voltage and current transients of SiC devices. The voltage is measured by means of a high BW RC attenuator, while the current is estimated from the voltage drop in the stray inductance of the switching loop. Since both voltages are measured with two equal and matched high BW passive voltage probes, there is no need to apply any de-skew. This is one of the most important advantages of the method. The presented method is experimentally evaluated and used for the estimation of energy switching losses in the tested SiC-mosfet. [ABSTRACT FROM AUTHOR]

To reduce current stress and improve efficiency of dual active bridge (DAB) dc–dc converters, various control schemes have been proposed in recent decades. Most control schemes for directly minimizing power losses from power loss modeling analysis and optimization aspect of the adopted converter are too difficult and complicated to implement in real-time digital microcontrollers. Thus, this paper focuses on a simple solution to reduce current stress and improve the efficiency of the adopted DAB converter. However, traditional current-stress-optimized (CSO) schemes have some drawbacks, such as inductance dependency and an additional load-current sensor. In this paper, a simple CSO scheme with a unified phase-shift (UPS) control, which can be equivalent to the existing conventional phase-shift controls, is proposed for DAB dc–dc converters to realize current stress optimization. The simple CSO scheme can overcome those drawbacks of traditional CSO schemes, gain the minimum current stress, and improve efficiency. Then, a comparison of single-phase-shift (SPS) control, simple CSO scheme with dual-phase-shift (CSO-DPS) control, simple CSO scheme with extended-phase-shift (CSO-EPS) control, and simple CSO scheme with UPS (CSO-UPS) control is analyzed in detail. Finally, experimental results verify the excellent performance of the proposed CSO-UPS control scheme and the correctness of theoretical analysis. [ABSTRACT FROM AUTHOR]

In this paper, the near-state pulsewidth modulation (NSPWM), adapted to be implemented in dual-voltage-source inverter (VSI) fed open-end motor, is proposed with the aim of mitigating low-order harmonics (which lead to current total harmonic distortion (THD) minimization). The following two proposed methods are studied in detail: 1) fixing phase angle displacement (PAD) between two VSIs to 120° while adjusting the modulation index (MI); and 2) fixing MI to the predetermined value (wherein low-order harmonics are highly mitigated) while adjusting PAD. Furthermore, the proposed approaches enhance efficiency by limiting the number of commutations within the switching interval. The paper also presents the mathematical approaches to accurately determine low-order harmonic components and switching losses for dual-VSI structure. The experimental setup, including dual-VSI and open-end induction motor, is assembled in the laboratory to evaluate performance of the proposed method. Finally, the simulation results, carried out in the MATLAB/Simulink environment, are found to be in close agreement with experimental data. [ABSTRACT FROM AUTHOR]

Modular multilevel converters (MMCs) are being developed for the grid connection of offshore wind or tidal farms. In order to reduce the construction and maintenance costs, it is desirable to reduce the weight and volume of the system. In current MMC submodule designs, the reservoir capacitor usually accounts for over 50% of the total volume and 80% of weight. This paper presents a new design concept and control principle for a submodule using the stacked switched capacitor (SSC) architecture that can significantly reduce the capacitor size in an MMC. Practical considerations for a high-voltage high-power SSC-based MMC submodule are presented in this paper, through the design of a 21-level, 40-kV (pole-pole dc), 19.1-MW, grid-connected system, and the concept is demonstrated experimenttally on a scaled-down 400-V, 12.3-Apeak laboratory prototype submodule. It is shown that with the proposed SSC architecture, the total volume of capacitors in each submodule can be reduced by more than 40% without significantly increasing the power loss. [ABSTRACT FROM AUTHOR]

This paper presents an analytical and experimental comparison of a two-phase buck converter and a two-phase, series capacitor buck converter. The limitations of a conventional buck converter in high-current (10 A or more), and high-frequency (HF, 3–30 MHz) point-of-load voltage regulators with large voltage conversion ratios (10-to-1) are highlighted. The series capacitor buck converter exhibits desirable characteristics at HF, including lower switching loss, less inductor current ripple, automatic phase current balancing, duty ratio extension, and soft charging of the energy transfer capacitor. Analysis of the topologies indicates that switching loss and inductor core loss can dominate at HF. Results from side-by-side 12 V input, 1.2 V output hardware prototypes demonstrate that the series capacitor buck converter has up to 12 percentage points higher efficiency at 3 MHz and reduces power loss by up to 33% at full load (10 A). Some guidelines for inductor selection are provided, and a switch stress comparison reveals that the maximum converter switch stress is reduced by 30%. [ABSTRACT FROM AUTHOR]

This paper proposed a novel method for two-segment three-phase motor to eliminate the harmonics nearby pulsewidth modulation (PWM) frequency. Due to PWM technique and switching losses considerations, ear-piercing high-frequency electromagnetic noise in drive system is common. By using magnetically coupled inductors (MCIs) and interleaved technique, the proposed novel method is able to remove the high-frequency harmonics located nearby the PWM frequency and other odd multiples in two-segment three-phase motor. With this method, the unpleasant acoustic noise could be removed when the PWM frequency is selected near 10 kHz. The size of MCIs mainly depends on the PWM frequency harmonic currents rather than the fundamental frequency currents. Thus, its size is very small compared with LC filter. Moreover, this method remains the control dynamics of two-segment three-phase motor without additional inductance for fundamental-frequency currents. The shift phase of two inverters PWM carriers is π, which is simple to implement. Finally, the effectiveness of the proposed method is verified by experimental results. [ABSTRACT FROM AUTHOR]

10 kV integrated gate-commutated thyristor (IGCT) has been recently developed and has the potential to push wind turbine systems to higher power and voltage rating. Converters employing IGCTs need snubber and over-voltage protection circuit to limit the rate of current's rising and peak over voltage across IGCT during turn-on and -off state, respectively. The conventional resistor-capacitor-diode (RCD) snubber which is used in such power converter dissipates a significant amount of power. In order to reduce the amount of energy lost by the conventional RCD snubber, this paper proposes flyback-type snubber. Flyback-type snubber not only meets all of the IGCTs characteristics during on- and off-state but also significantly saves the power loss. The proposed flyback-type snubber can save up to 73% of the loss in conventional di/dt snubber circuit according to the PLECS magnetic simulation of three-level neutral point clamped grid side converter. The experiments are performed using IGCT stack. Flyback transformer yields the effectiveness of the proposed snubber in wind turbine systems. [ABSTRACT FROM PUBLISHER]

This paper investigates the use of multilevel conversion in dc–dc applications that require a large voltage conversion ratio. A quantitative method that can serve as a guide to compare and design multilevel topologies for large conversion ratio applications is presented. The proposed method keeps the conduction loss and switching loss constant across the different converters and employs the passive component volume as the single performance metric. As examples, flying capacitor multilevel converters and hybrid switched-capacitor (SC) converters are compared to conventional two-level buck converters, and are shown analytically to have significantly reduced passive component size. Three converter prototypes are implemented, based on the presented methodology to experimentally validate the method as well as demonstrate the advantages of multilevel and hybrid SC converters. [ABSTRACT FROM PUBLISHER]

This paper aims to develop a novel adaptive gate switching controller (AGSC) for discontinuous conduction mode (DCM) dc–dc converters, in an attempt to reduce the power losses caused by nonideal gate switching operations. The proposed AGSC employs a dead-time controller (DTC) and a zero-current detector (ZCD) to turn ON and OFF the synchronous switch, respectively. Both the DTC and the ZCD perform self-calibration according to the converter switching node voltage, allowing the AGSC achieves near-optimal gate switching control regardless of the operating frequency, process variation, power device variation, as well as source voltage and load current variation. The proposed AGSC can have useful applications in many DCM dc–dc converters, e.g., buck, boost, and buck–boost converters. For a proof of concept, in this paper, a boost converter was implemented with the proposed AGSC in a 0.18-μm 3.3-V CMOS process with an area of 1.5 mm^2. The experimental results demonstrate precise control of the gate switching operations, and the boost converter at 1.2-V/2.5-V nominal input/output achieves a peak efficiency of 86% at 30-mA load current. [ABSTRACT FROM AUTHOR]

The power electronics cooling system should be able to dissipate very high heat flux densities (watts per surface area). For that, many solutions can be used: liquid forced convection, heat pipes, capillary loops, and so on. In the forced convection cooling system case, one of the hotspots is the mechanical pump. We propose in this paper to study the possibility of replacing the conventional mechanical pumps by electroosmotic (EO) pump. The pump based on porous ceramic seems well suited for this application. In this paper, after a few reminders on electroosmosis pumping theory, the new modification of our second prototype will be presented. Then, the test bench and the experiment results of the second prototype with a power electronics device will be presented and discussed. It will be shown that the pump generates 20 ml/min and it is used to evacuate 100 W/cm2 of heat flux generated by the power electronics device. [ABSTRACT FROM AUTHOR]

This paper analyzes supercapacitor energy loss and investigates its impact on power management in environmentally powered wireless sensor nodes that use supercapacitor-based energy storage systems. While supercapacitor self-discharge is usually taken into account for system design and power management in wireless sensor nodes, supercapacitor charge redistribution and the associated energy loss have not been considered. In an environmentally powered wireless sensor node, supercapacitor charge redistribution may have more significant impact on power management than self-discharge. This paper analyzes supercapacitor energy loss during charge redistribution based on the variable leakage resistance (VLR) model. It is concluded that supercapacitor energy loss is dependent on charge redistribution time and supercapacitor initial state, which is defined as the initial voltages across the capacitors in the VLR model. The impact of supercapacitor energy loss on power management is studied by considering the task scheduling problem. A set of simulation cases that covers various supercapacitor initial state and energy harvesting capability is designed to investigate the impact of supercapacitor energy loss on task scheduling policy. It is demonstrated that greedy or lazy scheduling policy is preferred depending on supercapacitor initial state and energy harvesting capability in terms of two performance evaluation metrics. [ABSTRACT FROM AUTHOR]

In this paper, a fast electro-thermal model of traction inverters for electrified vehicles is proposed. First, a thermal model considering the thermal coupling is presented and experimentally verified. The impact of the thermal spreading effect, heat convection, and temperature-dependent material thermal properties on the accuracy of the linear assumption is investigated by ANSYS-Fluent simulation. In order to reduce the influence of the temperature-dependent thermal conductivity on the accuracy of the thermal model, the average temperature is applied to determine the thermal conductivity of the power module package. Second, an accurate temperature-dependent switching power loss model is represented as the lookup table through experimental measurements. In order to simplify the lookup table, the switching power loss is considered proportional to the dc-link voltage and, therefore, the inputs of the lookup table are current and temperature. Finally, a scheme to speed up the online junction temperature estimation is proposed by considering both the thermal network properties and the required accuracy. With the proposed calculation rate determination method, the total computational time for the junction temperature estimation is reduced significantly. [ABSTRACT FROM AUTHOR]

It is well known that multilevel converters can offer significant benefits in terms of harmonic performance and reduced switching losses compared to their two-level counterparts. However, for lower voltage applications the neutral-point-clamped inverter suffers from relatively large semiconductor conduction losses because the output current always flows through two switching devices. In contrast, the T-type multilevel inverter has less conduction losses because only a single outer loop switching device is required to connect the converter output to the upper and lower dc buses, albeit at the expense of increased switching losses since these outer switches must now block the full dc link voltage. Silicon carbide (SiC) mosfet devices potentially offer substantial advantage in this context with their lower switching losses, but the benefit of replacing all switching devices in a T-type inverter with SiC mosfets is not so clear-cut. This paper now explores this issue by presenting a detailed comparison of the use of Si and SiC devices for a three-level T-type inverter operating in grid-tie applications. The study uses datasheet values, switching loss measurements, and calibrated heat sink thermal measurements to precisely compare semiconductor losses for these two alternatives for a T-type inverter operating at or near unity power factor. The results show that replacing only the dc bus connection switches with SiC devices significantly reduces the semiconductor losses, allowing either the converter power level or the switching frequency to be significantly increased for the same device losses. Hence, the use of SiC mosfets for T-type inverters can be seen to be an attractive and potentially cost-effective alternative, since only two switching devices per phase leg need to be upgraded. [ABSTRACT FROM AUTHOR]

In this paper, a nonisolated two-channel light-emitting diode (LED) driver with automatic current balance and zero-voltage switching (ZVS) is presented. In this LED driver, a dc-blocking capacitor is connected with one side of the coupled inductor. Therefore, based on the ampere–second balance, a current source is generated with the average value of the positive current identical to the absolute average value of the negative current. Accordingly, the LED currents can be balanced naturally without extra active components or current sharing transformer. Consequently, the circuit components can keep at a low count. In addition, the proposed LED driver can achieve ZVS turn-on. Thus, the switching loss can be decreased. Above all, the proposed two-channel LED driver can be extended to a multichannel LED driver. In this paper, detailed theoretical analyses and experimental results are provided to verify the feasibility and effectiveness of the proposed LED driver. [ABSTRACT FROM AUTHOR]

Thermal management is a key design aspect of power converters since it determines their reliability as well as their final performance and power density. Cooling technologies have been a research area in electronics since the 1940s and, in the last 15 years, the number of articles related to this field has grown significantly. At present, thermal management is essential in new disciplines and it is a critical enabling technology in the development of power electronic systems. This paper aims at presenting a review of the state-of-the-art technology and provides future design guidelines for high efficiency power electronic converters. The main design trends are focused on the need to develop cooling systems able to manage high local density heat fluxes due to two converging trends: higher power dissipation and smaller module size. Considering the latest advances in thermal management, as well as the huge improvement in power electronics in the last decades, a review and classification of the main thermal management techniques is presented. Besides, they are compared considering important parameters such as peak power dissipation, efficiency, cost/complexity, power density or technical maturity, and a design example for an ultrahigh efficiency converter is presented. [ABSTRACT FROM PUBLISHER]

This paper is a continuation of part I, which presented interturn fault (ITF) models for interior permanent magnet synchronous motors (IPMSMs). ITFs are defined by two ITF parameters: the healthy turn ratio and the fault contact resistance. First, this paper presents a proof that the two fault parameters defining a given ITF condition cannot be individually estimated from motor information and drive information (applied voltage, phase current, rotor speed, etc.) because they have multiple solutions. However, it is also shown that the additional Ohmic loss, which is the most important factor in heat generation and deterioration due to ITFs, is not dependent on these solutions. Thus, after arbitrarily setting one fault parameter, the other can be estimated for a given ITF condition; this model can be used to represent the effect of an ITF, particularly its Ohmic power loss. In this paper, an online fault parameter estimation method for IPMSMs is proposed after presenting one of the two fault parameters. The proposed method utilizes a searching algorithm that finds the fault parameter that has the minimum negative-sequence voltage error between the applied voltage and the ITF models (presented in part I). An experiment was performed to verify the proposed fault parameter estimation method. [ABSTRACT FROM AUTHOR]

This paper presents an online procedure for the automatic search of the maximum-torque-per-ampere operating region for a synchronous reluctance motor. The algorithm is based on a signal-injection method with a random-based perturbation pattern applied to a common direct-torque-controlled drive. Among motor parameters, only the stator resistance is required to perform the automatic procedure. Simulations and experimental results are presented in the paper, demonstrating the benefits of the proposed algorithm. The solution is easily extended to any ac drive. [ABSTRACT FROM PUBLISHER]

An inner current loop is frequently used in many switching power supplies to achieve higher stability and a good current sharing. Nevertheless, some problems derived from its practical implementation can be encountered. One problem is related to the need of filtering of the sensed current and was discovered by the authors in the implementation of a 500 W converter, when peak current control was applied by sensing the switch current. This paper will demonstrate mathematically that an RC filter not only filters out the noise but also can cause a degradation of the phase margin, especially, if the needed duty cycle is close to zero. The main reason for it is the severe distortion of the current waveform that results in an excessive phase loss. This phase loss is much larger than the expected from the filter and its delay. The problem becomes worse if we reduce the duty cycle and increase the load current. Therefore, the response to the ON time slope of the current waveform is negligible, and we have only the response to a steep rising edge. We will also demonstrate that phase margin loss disappears if current is sensed at the inductor instead of the switch. In both cases, the RC filter results in a different frequency response than the one predicted with the classical peak current mode theory. These differences are analyzed in depth in this paper. [ABSTRACT FROM AUTHOR]

This paper presents an original implementation of a technique in ac-to-ac power converters to power the gate drivers of power transistors. AC to ac converters are well known for the complexity of their implementation due to the large number of power transistors required, many of which have different potential references. This requires a consequent number of insulated gate drivers and corresponding power supplies. Besides, MOS-MOS switching transitions (characterized by switching transitions among transistors without the introduction of freewheeling diode conduction time), typical of these converters, are complex to manage and often lead to voltage or current overshoots. The gate driver powering technique presented in this paper simplifies the global implementation of the converter as well as the management of MOS-MOS switching transitions. The proposed technique harvests energy from the power side, when this energy is available, in order to redistribute this energy to the transistor drivers. This original self-powering technique significantly simplifies the implementation of the transistor since it can be integrated within the power switch to be controlled. The immediate benefit is a reduced number of elements to be implemented, thus providing a costeffective solution. As an additional benefit, the proposed technique simplifies the management of high-stress switching transitions. Indeed, the gate driver power supplies are designed to be sensitive to positive dv/dt, a feature that allows self-powering during the dead time of switching transitions. This leads to a reduction in both dead time duration and voltage overshoots, as validated by a practical implementation. [ABSTRACT FROM AUTHOR]

Due to the superior material properties, SiC mosfet is a promising candidate switching device for high power density and high efficiency power conversion system. The robustness of switching device under extreme temperature condition becomes a crucial factor to ensure power conversion system safely and continuously operating. In this paper, the temperature dependence of dynamic performance of 1.2-kV 4H-SiC power mosfets is systematically characterized over such wide temperature range of 90–493 K and compared with 1.2-kV Si IGBT by a layout optimized double pulse tester (DPT). The degradation of dynamic on-resistance related interface traps is analyzed specially and the energy loss caused by degradation is quantified at cryogenic temperatures. Besides, to validate the performance of SiC mosfet under safely and continuously operating conditions for cryogenic temperature application, a hard switched non-isolated dc–dc buck converter is designed and tested to estimate temperature dependence of conversion efficiency under temperature range of 90–290 K. Moreover, the further characterizations are conducted with gate resistance range of 2–20 Ω, load current range of 3–30 A, and converter output current of 5–22.5 A under different switching frequency (up to 150 kHz) to validate high power and high frequency application potential of SiC mosfet. [ABSTRACT FROM AUTHOR]

This paper proposes a voltage balancing method for stacked multicell converters (SMCs) based on phase-disposition pulse-width modulation (PD-PWM). In order to reduce the switching transitions of the power devices, only optimal transitions between consecutive voltage levels are used. Selection of the optimal transition sequence is performed by evaluating a cost function. Significant reductions in the switching transitions and power losses of the power devices are achieved as compared to the optimal-state voltage balancing method where nonoptimal transitions are allowed. Simulation and experimental results from a seven-level $3\times 2$ SMC verifies that the proposed PD-PWM voltage balancing method is robust under linear/nonlinear loads and transients. [ABSTRACT FROM AUTHOR]

The four-switch three-phase (FSTP) inverter has been proposed as an innovative inverter design to reduce the cost, complexity, size, and switching losses of the dc–ac conversion system. Traditional FSTP inverter usually operates at half the dc input voltage; hence, the output line voltage cannot exceed this value. This paper proposes a novel design for the FSTP inverter based on the topology of the single-ended primary-inductance converter (SEPIC). The proposed topology provides pure sinusoidal output voltages with no need for output filter. Compared to traditional FSTP inverter, the proposed FSTP SEPIC inverter improves the voltage utilization factor of the input dc supply, where the proposed topology provides higher output line voltage which can be extended up to the full value of the dc input voltage. The integral sliding-mode control is used with the proposed topology to optimize its dynamics and to ensure robustness of the system during different operating conditions. Derivation of the equations describing the parameters design, components ratings, and the operation of the proposed SEPIC inverter is presented in this paper. Simulation model and experimental setup are used to validate the proposed concept. Simulations and experimental results show the effectiveness of the proposed inverter. [ABSTRACT FROM AUTHOR]

In this paper, various types of discontinuous space vector pulse-width modulation techniques for a three-leg voltage source inverter supplying balanced two-phase loads are proposed. The main objectives of the paper are to analyze switching loss characteristics associated with semiconductor devices and to reduce output current ripple by dealing with various types of zero space vector time in each switching sequence. Capabilities of reductions in switching losses and current ripple for both balanced and unbalanced output phase voltages at high modulation index and load power factor angle of 30° lagging are focused. The validity of the proposed techniques is verified by simulation and experimental results in terms of voltage spectrum, current waveforms, reductions in switching losses, and output current ripple at high modulation index when compared to a continuous space vector pulse-width modulation technique. [ABSTRACT FROM AUTHOR]

A unidirectional single-phase ac–dc–ac converter is proposed and analyzed in this paper. It is composed of paralleled rectifiers and inverters sharing two legs with two dc-link capacitor voltages. Models and a control strategy of the systems including circulating currents are developed. Compared to the conventional four-leg and three-leg (4L and 3L) single-phase ac–dc–ac converters, the proposed topology allows the decreasing of the current and power ratings of the power switches, the harmonic distortion, and semiconductors power losses. And compared to the unidirectional three-leg ac–dc–ac converter, it allows us to decrease the current and power ratings of the power switches and the harmonic distortion. In addition, a modified interleaved pulse width modulation (PWM) strategy using four-carrier PWM is presented, ensuring five-level voltage at the input and output sides of the converter. Simulation and experimental results are also presented to demonstrate the viability of the proposed circuit. [ABSTRACT FROM AUTHOR]

Soft switching pulse-width modulation (PWM) dc–dc full-bridge converter with controlled rectifier on the secondary side of the high-frequency power transformer is presented in this paper. An active secondary switch, including new nondissipative passive energy recovery turn-off snubber on the secondary side and modified PWM control algorithm, provide conditions for zero-voltage and zero-current turn-on and zero-current turn-off of IGBT transistors on the primary side of the high-frequency dc–dc converter. The simple passive energy recovery snubber ensures also zero-voltage turn-off of the transistor on the secondary side of the power transformer. The principle of operation is explained and analyzed and consequently verified on a 2 kW, 50 kHz laboratory model of the converter. [ABSTRACT FROM PUBLISHER]

In this paper, we investigate the performance of the three-phase ac–ac matrix converter (MC) utilizing the novel superjunction (SJ) reverse-blocking (RB)-insulated gate bipolar transistor (IGBT) as switch elements for the first time. The SJ RB-IGBT offers bidirectional blocking capability >1200 V by introducing a shorted-collector trench and n2-layer. The SJ RB-IGBT exhibits bipolar conducting mode in the on-state and the unipolar mode during turn-off. Therefore, both a low on-state voltage (Von) and a low turnoff energy loss ( Eoff) can be obtained. The SJ RB-IGBT delivers the Eoff 80% lower than state-of-the-art RB-IGBTs without penalty in the Von. These merits make the SJ RB-IGBT an attractive candidate for the MC. To address the short circuit arising in commutation of the MC, the split gate is adopted for a low Miller capacitance. The power loss, efficiency, and loss distribution of the three-phase MC with the SJ RB-IGBT and other RB-IGBTs are compared by simulation and calculation. Compared with the MC using conventional nonpunch-through RB-IGBT, the MC with SJ RB-IGBT achieves 85%, 87%, and 56% reductions in the turnoff, reverse recovery, and conduction losses, respectively, yielding 56% reduction in the total loss. The low-power loss and superior dynamic performance of the SJ RB-IGBT enables the MC to operate at higher frequency and higher power density. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a new capacitor degradation evaluation method aimed at failure prediction and suitable for digitally controlled switching mode power supply (SMPS) for servers. Electrolytic capacitors have one of the highest component failure rates in SMPS; therefore, we attempt to detect an equivalent series resistance degradation of the electrolytic capacitor directly from the data fetched to a digital controller of the SMPS. With a SPICE simulation and a rapid control prototyping evaluation, we confirm the degradation can be detected by the data at a transient response under a normal operation without additional circuits. Even only 10% of a load step change, which commonly occurs in SMPS for servers, causes detectable transient response degradation. [ABSTRACT FROM PUBLISHER]

A concept, named as power semiconductor filter, has been demonstrated to be an alternative to perform input harmonic filtering in switched-mode power converters. It utilizes a series pass device (SPD) to profile the wave shape of the supply current, while the voltage across the SPD is regulated at a threshold voltage between the linear and saturation regions of the SPD to minimize its power dissipation. Bulky passive components for input harmonic filtering can then be eliminated or shrunk with such active supply current control. For the sake of circuit elegancy, regulation of the SPD voltage is realized by a bang-bang (peak-voltage) controller to vary the input characteristics of the power conversion stage through adjusting some control parameters, such as duty cycle and switching frequency. Experiments reveal that the entire system might exhibit bifurcation phenomena under some supply and load conditions. This paper will derive a sampled-data model to characterize such system behaviors and to identify the onset of bifurcation and chaos. A compensation ramp will be proposed to introduce into the bang-bang controller to stabilize the system operation. Moreover, the slow-scale dynamics will be studied with small-signal models. The investigations will be exemplified on a 48 W, 40–140 V/24 V buck dc–dc converter prototype. [ABSTRACT FROM PUBLISHER]

With the emerging market for multichip module based high-power LED systems, the demand for advanced thermal management techniques has been steadily growing. This paper presents a model developed by the authors for thermal coupling matrix that can calculate temperature distribution at a given heat power of each chip. The model significantly simplifies the task of measuring thermal coupling effect on multichip light-emitting diodes with symmetrical structure, while simultaneously preserving temperature accuracy. The modeling technique was validated experimentally on three-, four-, and six-chip rectangular modules, and a ten-chip circular module, by infrared thermography and transient thermal measuring system, respectively. The modeling technique was found to be more efficient especially for large systems. The model offers a rapid way to predict thermal coupling behaviors of multichip LED systems. [ABSTRACT FROM PUBLISHER]

An isolated converter such as SEPIC has high voltage stress on the main switch due to transformer leakage inductance. To solve this issue, active or passive clamp action is necessary. The common passive solution based on an RCD snubber is simple but impractical when the value of the leakage inductance is significant. On the other hand, passive regenerative solutions generally compromise the isolation, making the search for a suitable snubber a challenge. In this paper, an effective passive regenerative snubber cell for isolated SEPIC converters operating in DCM or CCM is presented. It is intended to improve the converter efficiency by transferring the energy stored in the transformer leakage inductance to the output. The analysis is presented in detail for DCM and extended to CCM together with a practical design procedure. In order to compare with the RCD, the analysis and design of a conventional cell are presented as well. To validate the proposal and quantify its feasibility, experimental results are performed for both dissipative and regenerative snubbers on a 100 W, 100 V, input and 50 V output voltage converter operating first in DCM and later in CCM. [ABSTRACT FROM PUBLISHER]

For maximizing the power transfer in an inductive power transfer system, the operating frequency of the system is normally designed to be the same as the resonant frequency of the secondary power pick-up. But the load deviation reflected from secondary side to primary side will result in the frequency mismatch issue. Therefore, the contactless load detection technique is significant to ensure the power transfer efficiency and capacity. The emerging technique taking advantages of the amplitude decay rate in a transient process is promising. The robustness and practicability can get enhanced and the complicated steady circuit model is avoided. However, the accuracy for the small resistance application is still a challenge even with sophisticated compensation algorithms. This paper classified the system detectable region through the root locus method. The transient process in different subregions is excavated mathematically. It is revealed that the variation of the system from the second order to fourth order is the key issue for the detection error in the small load resistance application. The analysis brings out a novel automatic contactless load detection method to extend the detection range. Both simulation and experimental results verified the effectiveness of the proposed theory and detection method. [ABSTRACT FROM AUTHOR]

An energy-efficient maximum power point tracking (MPPT) circuit with a fast-tracking time for use with 800-μW PV energy harvesters is presented in this paper. The proposed MPPT circuit uses a successive approximation register MPPT algorithm, which has a power down mode and a fast tracking time, to achieve low power consumption and energy savings. The prototype MPPT circuit, which consists of analog-based circuits, has been implemented and fabricated in a 0.35-μm BCDMOS process. The MPPT core occupies an area of 3 mm^2 and consumes 4.6 μW of power. The tracking time is reduced by 69.4% and the stored energy is increased by 31.4% as compared to the conventional hill climbing-based MPPT algorithm under indoor conditions. [ABSTRACT FROM AUTHOR]

This paper proposes a new interleaved buck converter (IBC) having low switching losses and improved step-down conversion ratio, which is suitable for the applications where the input voltage is high and the operating duty is below 50%. It is similar to the conventional IBC, but two active switches are connected in series and a coupling capacitor is employed in the power path, such as Cuk, Sepic, and Zeta converters. The proposed IBC shows that since the voltage stress across all the active switches is half of the input voltage before turn-on or after turn-off when the operating duty is below 50%, the capacitive discharging and switching losses can be reduced considerably. This allows the proposed IBC to have higher efficiency and operate with higher switching frequency. In addition, the proposed IBC has a higher step-down conversion ratio and a smaller output current ripple compared with a conventional IBC. The features, operation principles, and relevant analysis results of the proposed IBC are presented in this paper. The validity of this study is confirmed by the experimental results of prototype converters with 150-200 V input, 24 V/10 A output. [ABSTRACT FROM AUTHOR]

The on-state resistance of power MOSFET devices tasked to perform repetitive avalanche operations is subject to modifications caused by the growth of voids and cracks in the source metallization. Endurance tests are the traditional way to monitor these changes in order to assess device reliability. However, they are very time intensive, requiring even months of uninterrupted operations. An interesting alternative is assessment of reliability through a suitable model, but no standard techniques have been developed up until now to accomplish this task. A possible approach, dynamic analysis of the temperature distribution over the source metal, is presented in this paper. Coupling the results of the thermodynamic analysis with a reliability model, and based on the Coffin-Manson law, device degradation over time can be estimated and the level of reliability can be evaluated. The consistence of the obtained reliability prediction is confirmed by comparison with endurance test results. The described approach can be usefully applied to assess the reliability of MOSFETs in a large set of applications in the automotive field. [ABSTRACT FROM AUTHOR]

With the use of wall-plug efficiency, estimation techniques for the optical power and heat-dissipation coefficient of LEDs are introduced in this paper to enrich the photo-electro-thermal theory, which has provided a framework for analyzing LED systems. The estimation methods consist of simple procedures for optical and electrical power measurements, which are easy for LED device manufacturers and system designers to follow. The extended theory has been tested with several types of LED devices, with reasonably good agreements between theoretical and practical results. [ABSTRACT FROM AUTHOR]

An analytical approach for the management of regenerative energies in multiaxis servo-motor-drives, which can operate in parallel packaging/assembly/manufacturing lines, is presented in this paper. This energy management is achieved through a proper time-coordination between the speed commands of multiaxis drives. Moreover, the proposed approach significantly limits the peak value of the ac input current in these systems. It is mathematically proved that a time-delay can significantly increase the amount of utilized regenerative energy, and consequently decreases the amount of dissipated energy. In this paper, a set of closed-form formulas is developed for different acceleration-deceleration time ratios, where motor losses are neglected. The findings of this investigation were experimentally verified using a two-axis permanent-magnet motor-drive system, and the results are presented in this paper. The experimental results are in remarkable agreement with the developed closed-form formulas. [ABSTRACT FROM AUTHOR]

Two different dynamic effects influencing the insulated gate bipolar transistor (IGBT) losses in soft-switching converters are demonstrated. The first one, the Dynamic tail-charge effect shows that the tail charge is dependent not only on the absolute value of the current at turn-off, but also on the dynamics of the current. This effect may have a significant impact on the optimization of zero-current-switching converters. The Dynamic conduction losses originate from the conductivity modulation lag of the IGBT. It is shown by experiments that the on-state losses depend on the operating frequency. Different methods to accurately determine the on-state losses are evaluated. It was found that the best method is an indirect measurement, where the stray inductance is identified by the use of an oscillating circuit. The experiments are performed under a sinusoidal current excitation at a fixed amplitude (150 A) for different frequencies (up to 104 kHz). The switching devices used are IGBT modules rated 300–400 A/1200 V in a bridge-leg configuration. From the experiments performed, it is found that IGBTs of a modern punch-though (PT) designs have the lowest losses in the series-loaded resonant converters studied in this paper. [ABSTRACT FROM PUBLISHER]

In this paper, losses in a 4-kVA three-phase voltage-sourced inverter designed to drive an induction machine, are investigated. A comparison of inverter losses with sinusoidal pulsewidth modulation (PWM), space vector PWM and discontinuous PWM (DPWM) is presented, concluding that DPWM is the method of choice. These PWM schemes are implemented using a field-programmable gate array and modeled in Pspice. PWM excitation models are combined with an inverter model that incorporates the Hefner model for the insulated gate bipolar transistors. After verification of the complete inverter model with calorimetric measurements, the model is used to predict inverter losses under various conditions of modulation index, switching frequency, and gate resistance for each of the PWM scheme. A breakdown of losses into conduction and switching losses is presented. Moreover, the effects of different DPWM variants on inverter losses are also being considered. Overall, the use of DPWM is found to give minimum losses as a consequence of the reduced number of switching transitions. [ABSTRACT FROM PUBLISHER]

This paper presents a new digital pulsewidth modulator (DPWM) architecture for field programmable gate array (FPGA)-based systems. The design of the proposed DPWM architecture is based on fully utilizing the digital clock manager (DCM) resources available on new FPGA boards. Furthermore, this architecture will also window-mask the DCM operation to only a portion of the switching period in order to decrease power dissipation. This proposed digital modulator technique allows for higher DPWM resolution with lower power consumption, the primary barrier to high switching frequency operation. The presented technique relies on power-optimized resources already existing on new FPGAs, and benefits from the inherit phase-shifting properties of the DCM blocks, which help in simplifying the duty cycle generation. The architecture can be applied to achieve different numbers of bits for the DPWM resolution designed for different dc-dc applications. The suggested architecture is first simulated, implemented, and experimentally verified on a Virtex-4 FPGA board. [ABSTRACT FROM AUTHOR]

This paper proposes an active current source gate drive (ACSD) method based on voltage controlled current source(VCCS) feedback control strategy for high-power IGBTs. Unlike the common voltage source gate drive, the proposed ACSD method provides constant drive current to charge and discharge an IGBT. With a large gate drive current, high switching speed and low switching losses can be achieved in a power converter. However, a high-current/voltage overshoot occurs. To solve this problem, a feedback current proportional to the \rmdi/ \rmdt or \rmdv/ \rmdt signal is generated to the IGBT gate. Thus, direct control of the net gate drive current is produced. Then, the current/voltage overshoot is controlled with little sacrifice in switching time, and the switching losses are lower than that with the conventional gate drive method operating simply by gate resistance switchover. The operation principle and circuit implementation of the proposed ACSD method are presented. The experimental results from a 1200 V/800 A IGBT module verify the performance of the proposed method. [ABSTRACT FROM AUTHOR]

This paper proposes a hierarchical active balancing architecture for the series-connected lithium-ion batteries. The key point of the architecture is that by grouping the battery string into different packs and introducing the top layer, the coupled influence among the cells in different packs is eliminated, which reduces the required balancing time and the energy loss. The repeated charging and discharging problem is avoided, which is beneficial for increasing the state-of-health. Moreover, the proposed architecture can lower the current rating of the balancing circuits, which helps decrease the required cost and improve the system efficiency. On the basis of the architecture, a balancing control using the state-of-charge of each cell is proposed to achieve the balance for all the cells. Furthermore, to deliver the energy from one pack to any other pack bidirectionally, a multidirectional multiport converter along with the current control method is proposed to serve as the top layer. This converter is different from the conventional three-port converter as it can achieve the arbitrary current flow direction control for any number of ports. The experimental results based on 24 series-connected 200-Ah lithium-ion batteries verified the benefits of the proposed architecture and the balancing circuits. After balancing, 4.1% of the total energy of the battery string is saved. Compared to the conventional adjacent cell-to-cell architecture, the proposed architecture can decrease the balancing time and the energy loss during the balancing process by 27.6% and 44.0%, respectively. In addition, the current rating and the cost of the balancing circuits in the proposed architecture is only 37.5% and 11.5% of that in other references. [ABSTRACT FROM AUTHOR]

Power converters operating in boundary conduction mode (BCM) can benefit from an efficiency increase compared to continuous conduction mode (CCM) based on the soft-switching transitions at turn-on and/or turn-off. However, for a given average inductor current, the RMS current in BCM converters becomes larger than in CCM converters, leading to an increase in conduction losses. Interleaving smaller BCM power converters overcome this drawback by reducing the total ripple current amplitude at the expense of an increase in complexity and in magnetic parts count. Nevertheless, as the magnetic devices are among the largest components in power converters, it is convenient to find the design conditions under which BCM or CCM could yield the smaller net volume. This paper proposes a method to estimate the volume ratio for magnetic parts, between single-phase CCM and multiple interleaved BCM power converters as a function of the number of phases, inductor loss, and switching frequency. The results obtained can be applied to boost, forward, and flyback dc-to-dc topologies. [ABSTRACT FROM AUTHOR]

Because of the forward recovery, the performance of the diodes degrades seriously at multimegahertz, causing extremely high power loss. So, the synchronous rectification (SR) is strongly desired in the multimegahertz resonant converters. This paper proposes a self-driven level-shifted resonant gate driver (RGD) for the SR FET in a 10-MHz isolated class-Φ2 resonant converter. The proposed RGD provides precise switching timing for the SR so that the body diode conduction loss can be minimized. A control stage is introduced to the proposed RGD to block the circulating current and the low-impedance path in the driver to realize ON–OFF control of the converter with high efficiency. The proposed RGD also generates a tunable dc bias to increase the peak gate voltage and extend the conduction time with the optimal $R_{{\rm DS}({\rm on})}$ so that the average $R_{{\rm DS}({\rm on})}$ and the associated conduction loss can be reduced significantly. A 10-MHz prototype with 18-V input and 5-V/2-A output was built. At full load of 2 A, the proposed RGD improves the efficiency from 80.2% using the conventional RGD to 82% (an improvement of 1.8%). Compared to the efficiency of 77.3% using the diode rectification, the efficiency improvement is 4.7% at full load. [ABSTRACT FROM AUTHOR]

Modern multifunction systems on chip often require a high-efficiency buck converter over a wide load current range as the main power source, for which complex multimode operation with mode detection/change is a frequent compromise between efficiency and transient response. This paper proposes a novel power-loss-aware switch-on-demand modulation (PLASOM) technique based on accurate power loss modeling to switch critical components/parameters of power loss on demand: the ON/OFF status and the size of the power transistor, the dead time, and the ON/OFF status of power-hungry subcircuits. The proposed PLASOM-based converter can work as either an adaptive on-time mechanism with constant frequency or a cycle-extended adaptive ON/OFF-time mechanism with variable frequency without mode detection/change, so that the conversion efficiency and transient response can be improved. A proposed buck converter with the PLASOM technique was implemented using the TSMC 90-nm 1/3.3-V CMOS process. Experimental results show that a conversion efficiency higher than 90% was achieved over the 1–500 mA load current range, whereas the voltage variation/recovery time during the 0.1–500 mA load transient were less than 50 mV/25 μs. Performance evaluations indicate that the proposed PLASOM technique is favorable for wide load current range buck converters in terms of conversion efficiency, transient response, and voltage ripples. [ABSTRACT FROM AUTHOR]

Deadtimes are required to avoid simultaneous conduction of high-side and low-side power transistors in half-bridge power converters. During these secure times, free-wheeling current flow generates extra power losses. Very short deadtimes are desired but they cannot be safely set in conventional isolated power converters because of a digital input propagation delay mismatch. A specific deadtime management is introduced in this paper to ensure proper operation of a high-voltage synchronous power converter. A controller integrated in each isolated gate driver secures synchronous switching by detecting the opposite switch turn-off before turn-on. With such a selfswitching technique, very short but safe nonoverlap times can be set. A gate driver has been implemented in a 0.35 μm 20-V CMOS process. The monolithically integrated controller consumes only 140 μA and 0.22 mm2 of silicon area. The proposed local deadtime management has been validated in two synchronous buck converters without external free-wheeling diodes: a 500-W 250-V to 55-V converter based on SiC JFETs and a 30-W 45-V to 10-V converter based on eGaN FETs. In either case, the proposed controller allows a higher efficiency from 10% of the rated load with resulting deadtimes as short as 15 ns. [ABSTRACT FROM AUTHOR]