Search

V2Ic is a ripple-based control with an excellent performance for load transients and reference voltage tracking because it exhibits a feedforward of the load current and the error of the output voltage. However, if V2Ic is modulated with constant frequency, constant on-time or constant off-time, its dynamic response is hindered by delays in the response. This paper proposes a technique that synchronizes the clock of the converter to initialize the duty cycle when a worst-case load transient occurs using the current through the output capacitor to detect load transients. It is exemplified on a V2Ic control but it is applicable to most of controllers as it only acts on the modulator. [ABSTRACT FROM AUTHOR]

Active rectifiers/inverters are becoming used more and more often in regenerative systems and distributed power systems. Typically, the interface between the grid and rectifier is either an inductor or an LCL-filter. The use of an LCL-filter mitigates the switching ripple injected in the grid by a three-phase active rectifier. However, stability problems can arise in the current control loop. In order to overcome them, a damping resistor can be inserted, at the price of a reduction of efficiency. The use of active damping by means of control may seem attractive but it is often limited by the use of more sensors compared to the standard control and also by a complex tuning procedure of the controllers. This paper introduces a new active damping method that does not require the use of more sensors. It consists of adding a filter on the reference voltage for the modulator. The tuning process of this filter is easily done, for a wide range of sampling frequencies, with the use of genetic algorithms. This method is used only for the optimum choice of the parameters in the filter and an on-line implementation is not needed. Thus the resulting active damping solution does not need new sensors or complex calculations. Moreover, in the paper particular attention is devoted to the susceptibility of the system in a high polluting environment. [ABSTRACT FROM AUTHOR]

This article is aiming to unify the modeling methods for various ripple-based control schemes. It is divided into two parts, and the first part presents a sampled-data modeling method for the peak/valley current mode (PCM/VCM) control and the peak/valley voltage mode (PVM/VVM) control. It is pointed out that due to the high bandwidth of the dc–dc converter under PCM/VCM or PVM/VVM control, the sideband effect cannot be ignored in the modeling process. Meanwhile, with the small-signal assumption, the feedback perturbation signal has a discontinuity of the first kind at each sampling instant, so the perturbation value at this instant should be obtained according to the Dirichlet conditions, which is equal to half of the sum of the limit values on the left and right sides of the signal. Then, by using Shannon's sampling theorem, the transfer functions of the modulator and the loop gain are derived, and they are used to analyze the influence of the sideband components on the converter stability. Finally, the experimental results from a PCM controlled buck converter validate the proposed modeling technique. [ABSTRACT FROM AUTHOR]

This part is the second part of this article and mainly presents the sampled-data modeling method for the dc–dc converters with the constant on-time (COT) and constant off-time (COFT) controls. Compared with the constant frequency control in the first part, the duty cycle perturbation signal in the COT/COFT control is found to have two sets of narrow pulse signals in each switching period. Then, by establishing the relationship between the two sets of signals and using Shannon's sampling theorem, the transfer functions of the modulator and the loop gain are derived. Based on the theoretical results, the phenomenon that a current-mode constant on/off time controlled buck converter is stable at any duty cycle, and the instability of a voltage-mode constant on/off-time controlled buck converter with the smaller time constant of the output capacitor could be predicted. Moreover, the sampled-data modeling method is further extended to the digital control by taking a digitally current-mode controlled buck converter as an example. Simulation results are provided to confirm the validity of the proposed modeling method. [ABSTRACT FROM AUTHOR]

This letter presents a novel implementation of pulse width modulation that improves the quality of the line-to-line output voltages in interleaved multiphase voltage-source inverters (VSIs). In multiphase VSIs with n interleaved parallel-connected legs, the best single-phase output voltage is achieved when the carriers are evenly phase shifted. However, switching among nonadjacent levels can be observed at regular intervals in the line-to-line voltages, causing bad harmonic performance. With the proposed method, switching in the line-to-line voltages happens exclusively between adjacent levels. The modulator utilizes two sets of n evenly phase-shifted carriers that are dynamically allocated. Because of its generality, the proposed implementation is valid for any number of phases and any number of legs in parallel. A MATLAB/Simulink model has been set up for simulation purposes. Selected experimental results obtained from a three-phase VSI made up with two and three legs in parallel per phase are reported, confirming the enhancement attained with the proposed implementation. [ABSTRACT FROM AUTHOR]

An architecture is presented for digital multiphase modulators (MPM) that leads to an efficient, high performance hardware realization. The combined modulator, switching phases and output filter are viewed as a multilevel digital-to-analog converter with high power output, or a power D/A, and concepts used in D/A converters are leveraged to achieve high performance and hardware efficiency. The modulator is split into three functional blocks including a decoder that determines how many phases are on at any time, a selector that determines which phases are on at any time, and a single high-resolution module that is time-shared among all phases. The resulting architecture scales favorably with a large number of phases and facilitates fast update rates of the input command well above the single phase-switching frequency, fs. Experimental results are presented for a custom integrated circuit realization in a 0.35-µCMOS process, designed for 16-phase output with an input command update rate of 16 times fs. Two complete 16 phase MPM designs are verified on the IC with different high-resolution modules, including a delay-line based design achieving 9-b resolution at fs = 4 MHz and a counter-based design achieving 8-b resolution at fs = 586 kHz. [ABSTRACT FROM AUTHOR]