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According to the number of segments, the space vector modulation (SVM) can divide into conventional SVM sequence (CSVMS) and special SVM sequence (SSVMS). It is well known that SVM can be equivalently realized by carrier-based pulse width modulation (CBPWM) with a zero component injection in both two-level and three-level inverters. For eight segment CSVMS in three-level inverters, many papers have ever got the injected zero component equation. But similar approach does not work for SSVMS, which has more than eight segments, e.g., 10, 12, or 14. What more, the accurate injected zero component has never been achieved so far. To solve above problems, therefore, a generated decomposition method of modulation wave has been proposed in this paper. By strict theoretical derivation, the same correlation can be extended to SSVMS and the corresponding zero component expression can be acquired. Based on this method, this paper puts a lot attention on the essential feature explanation, mathematical proof, and gives a detailed process to get the zero component equation, using it can realize SSVMS by CBPWM. The simulation and experimental results illustrate that the generated decomposition method of modulation wave is correct, and the unified theory of CBPWM and SVM is verified. [ABSTRACT FROM AUTHOR]

This paper presents an integrated solution for a photovoltaic (PV)-fed water-pump drive system, which uses an open-end winding induction motor (OEWIM). The dual-inverter-fed OEWIM drive achieves the functionality of a three-level inverter and requires low value dc-bus voltage. This helps in an optimal arrangement of PV modules, which could avoid large strings and helps in improving the PV performance with wide bandwidth of operating voltage. It also reduces the voltage rating of the dc-link capacitors and switching devices used in the system. The proposed control strategy achieves an integration of both maximum power point tracking and V/f control for the efficient utilization of the PV panels and the motor. The proposed control scheme requires the sensing of PV voltage and current only. Thus, the system requires less number of sensors. All the analytical, simulation, and experimental results of this work under different environmental conditions are presented in this paper. [ABSTRACT FROM AUTHOR]

Pulse width modulation schemes are aimed at adjusting the fundamental component while reducing the harmonic content of an inverter output voltage or current. This paper addresses the topic of optimal inverter operation in reference to a given objective function. The objective function could embody either a single performance criterion, such as voltage or current total harmonic distortion (THD), or a weighted sum of multiple criteria. The proposed method ensures primacy of the chosen solution while imposing no restriction over its modulation index. In particular, operating the inverter by the chosen solution would result in performances superior to any other modulation scheme commutating in an equal number of switching angles per fundamental cycle. The proposed method allows for the consideration of practical inverter constraints and prevents the possibility of impractical switching sequence. A detailed investigation of the method is given, accompanied by two practical cases minimizing, respectively, phase-voltage THD and line-current THD of a three-level inverter. Selected simulation and experimental results are presented to validate the theoretical part. [ABSTRACT FROM AUTHOR]

In this paper, an immune algorithm (IA)-based dead-time elimination PWM control strategy is proposed. For existing dead-time elimination applications, one of the major problems is the dead-time control around the zero-current-crossing points. To deal with this problem, this paper proposes a different PWM control method which first restricts the control sequence to a specified level around the zero-crossing zone. Also, the proposed method can improve the current waveform quality by using the IA approach and three-level control strategy. Compared with conventional dead-time elimination methods, this technique has the features of simple hardware requirement and adaptive control. Moreover, this control strategy effectively eliminates the effect of dead-time, while at the same time significantly reducing the total harmonic distortion of output current and improving the amplitude of output RMS value in different modulation indexes and loads conditions. To verify the analysis, an experimental platform based on DSP and field-programmable gate array is built. The simulation and experimental results are given to demonstrate the effectiveness and feasibility of this new method. [ABSTRACT FROM AUTHOR]

This paper discusses the voltage error caused by the dead time in voltage-source PWM converters. The theoretical analysis in this paper derives the nonlinear voltage error paying attention to the parasitic output capacitance in each switching device. The analytical result reveals that the turn-off current or the switching current ripple strongly affects the voltage error. In addition, it is clarified that the conventional compensation methods based on linear and three-level approximation are suitable under small and large current ripple conditions, respectively. A simple calculation method of current ripples in three-phase PWM converters is also developed to estimate the turn-off currents. Turn-off transition compensation method which is a new compensation method based on the analysis is developed and compared with three different conventional methods in experiments using a 200-V, 5-kW three-phase grid-connection converter. The proposed method exhibits a good compensation performance having a lower voltage THD than the conventional methods in all over the operating range. [ABSTRACT FROM AUTHOR]

A solid-state transformer is a three-phase ac/ac converter with a high-frequency transformer. Due to advanced features like high power density, on demand var support and frequency regulation, solid-state transformer is an enabling technology for the modern power distribution system. It can also find application in high-power-density motor drives. The single-stage solid-state transformer considered in this paper is capable of bidirectional power flow and open loop power factor correction. This topology uses a minimum amount of copper and has relatively few semiconductor switches. One major problem in this converter is the commutation of leakage energy which results in power loss, reduction in switching frequency, loss of output voltage, and additional common-mode voltage switching. This paper presents a source-based commutation strategy along with a novel modulation technique resulting in elimination of additional snubber circuits, minimization of the frequency of leakage inductance commutation, recovery of the leakage energy, and soft switching of the output converter. The topology and its proposed control have been analyzed. Simulation and experimental results confirm the operation. [ABSTRACT FROM AUTHOR]

This paper presents an in-depth critical discussion and derivation of a detailed small-signal analysis of the phase-shifted full-bridge (PSFB) converter. Circuit parasitics, resonant inductance, and transformer turns ratio have all been taken into account in the evaluation of this topology's open-loop control-to-output, line-to-output, and load-to-output transfer functions. Accordingly, the significant impact of losses and resonant inductance on the converter's transfer functions is highlighted. The enhanced dynamic model proposed in this paper enables the correct design of the converter compensator, including the effect of parasitics on the dynamic behavior of the PSFB converter. Detailed experimental results for a real-life 36 V-to-14 V/10 A PSFB industrial application show excellent agreement with the predictions from the model proposed herein. [ABSTRACT FROM AUTHOR]

A modular multilevel converter (MMC) is an attractive solution for power conversion without transformers. The MMC consists of cascade connections of floating dc capacitors. In this paper, an adaptive observer design has been proposed to estimate the capacitor voltages from the measurement of arm currents. This work introduces the capacitance value of the cell capacitors as a parameter uncertainty for making the system performance robust with unknown constant parameters. It may be used for predictive control, condition monitoring for capacitors, and diagnosis check for capacitor health. In addition, a pulsewidth modulation (PWM) technique for MMC has been explored. The PWM technique is performed using a carrier-based level-shifted PWM strategy. It does not necessitate the calculation of duty cycles, and can be easily implemented in a DSP. By using the PWM technique, harmonics in the phase voltage is shifted to twice the switching frequency. Theoretical analysis is included in this paper for showing stability and convergence of the proposed observer. Analytical expressions are verified by simulation and experimental results. [ABSTRACT FROM AUTHOR]

This paper presents a new multilevel selective harmonic elimination pulse-width modulation (MSHE-PWM) technique for transformerless static synchronous compensator (STATCOM) system employing cascaded H-bridge inverter (CHI) configuration. The proposed MSHE-PWM method optimizes both the dc-voltage levels and the switching angles, enabling more harmonics to be eliminated without affecting the structure of the inverter circuit. The method provides constant switching angles and linear pattern of dc-voltage levels over the modulation index range. This in turns eliminates the tedious steps required for manipulating the offline calculated switching angles and therefore, easing the implementation of the MSHE-PWM for dynamic systems. Although the method relies on the availability of the variable dc-voltage levels which can be obtained by various topologies, however, the rapid growth and development in the field of power semiconductor devices led to produce high-efficiency dc-dc converters with a relatively high-voltage capacity and for simplicity, a buck dc-dc converter is considered in this paper. Current and voltage closed loop controllers are implemented for both the STATCOM and the buck converter to meet the reactive power demand at different loading conditions. The technique is further compared with an equivalent conventional carrier-based pulse-width modulation to illustrate its enhanced characteristics. The effectiveness and the theoretical analysis of the proposed approach are verified through both simulation and experimental studies. [ABSTRACT FROM AUTHOR]

The design of modulation schemes at low pulse ratios is a known topic. However, most of previous work has focused on optimized pulse patterns, e.g., selective harmonic elimination. For industrial applications, standard carrier modulators are still highly attractive in many cases. Unfortunately, few papers presented insightful studies on carrier modulators at extremely low pulse ratios. This paper covers this gap. At extremely low pulse ratios, several special phenomena of carrier modulators are introduced for the first time. For example, a significant performance variation effect can be observed when carrier modulators are used. Moreover, the thermal unbalance of the hotspot devices in the converter may lead to significant power capability degradation of the converter unit. In this paper, the mechanisms behind this are explored and explained in detail for the first time. A quantitative comparison between different carrier-based modulation schemes is presented. Based on that, several design instruction for modulators at low pulse ratios are summarized at the end. [ABSTRACT FROM AUTHOR]

A high stability flat-top pulsed magnetic field has both high field strength and high field stability simultaneously, which can be used for the high precision scientific experiments. In this paper, we present such a high stability flat-top pulsed magnetic field facility developed in the Wuhan National High Magnetic Field Center. A passive bypass circuit is developed to regulate current up to tens of thousands amperes, as well as a 25 T/200 ms flat-top pulsed magnetic field with a ripple of 250 ppm (0.025%). The main circuit scheme of the facility as well as the preliminary experimental results will be presented in this paper. [ABSTRACT FROM AUTHOR]

Insertion of dead time, transfer links between micro control unit (MCU) and voltage source inverter (VSI), VSI's nonideal characteristics all lead to deviation that cannot be ignored between the actual output voltage and the command voltage, which seriously affects the performance of the ac induction motor (ACIM) control system. Among many dead-time effect compensation methods, VSI usually operates under an open-loop condition, thus making complete compensation hard to achieve. This paper studies methods to obtain the two key elements of compensation voltage amplitude and current polarity and a novel phase voltage compensation method is proposed. In this method, a simple hardware circuit is applied to obtain the actual output of the VSI as feedback with which precise compensation amplitude can be calculated. And judgment of current polarity is accurately realized by reconstructing phase current from filtered current components under M-T coordinate with a Kalman filter. The compensation in a zero-crossing region is also closely discussed in this paper. To verify the validity of the method, simulations and experiments are carried out. The experiments emphasize on the efficacy of feedback, steady-state, and transient performance of current reconstruction; and the performance of a conventional method to that of the proposed method are also compared. Results show that the proposed method proves to be effective. [ABSTRACT FROM AUTHOR]

Switch fault diagnosis is an important design aspect for pulse width modulation (PWM) dc-dc power converters. It can prevent power converters from further damage, and also make preparations for remedial actions. In this paper, a fast switch fault diagnostic method is proposed for PWM dc-dc converters operating in continuous conduction mode. The proposed method utilizes the magnetic component (inductor or transformer) voltage for fault diagnosis. Based on the real-time voltage measurement and switch gate-driver signals, characteristics of switch open-circuit faults and short-circuit faults are rapidly extracted, and thus, switch faults can be quickly detected. The magnetic component voltage can be measured by an auxiliary winding in the magnetic core, and gate-driver signals can be easily got from the control circuit. Moreover, the fault detection can be implemented by a low-cost logical hardware circuit, and this circuit can be integrated into the control circuit. The fault diagnosis principle, design considerations, and implementation are discussed in this paper. Experiments are conducted to verify the theoretical analysis. [ABSTRACT FROM AUTHOR]

The switching frequency is an important control parameter of pulse-width-modulation (PWM) rectifier to reduce switching losses and electromagnetic interference noise. This paper proposed a variable switching frequency PWM (VSFPWM) strategy for dc-link voltage ripple control in two-level rectifier. DC-link voltage ripple is determined by the dc-link current directly, and can be predicted synchronously with PWM signals. A real-time prediction model of dc-link voltage ripple is derived for a common voltage-oriented control PWM rectifier. Then, VSFPWM control is introduced, which changes the switching frequency cycle to cycle with a restriction of dc-link voltage ripple peak value. Furthermore, the dynamic behavior is also observed when the proposed VSFPWM control scheme is adopted. Detail simulation and experimental comparisons are carried out between VSFPWM and normal constant switching frequency PWM, which demonstrate the advantages of the proposed method. [ABSTRACT FROM AUTHOR]

For dc–dc converters with pulsating output current, such as boost and buck–boost converters, the use of leading-edge or trailing-edge pulse width modulation (PWM) can result in distinctly different behavior. This phenomenon is not readily captured by the usual averaged model but can be predicted with a discrete-time model. However, the discrete-time model, which tracks the dynamics of state variables over a switching period, is usually more complex and less convenient to apply for the design of the feedback control. Based on the low-pass characteristics of dc–dc converters, an approximate discrete-time model is proposed in this paper, and upon transforming to the s-domain, the model results in transfer functions that can be conveniently used for deriving practical closed-loop parameters. With the proposed model, the loop gain, the input and output impedances are derived and analyzed. The effects of applying different types of PWM on the stability of a single dc–dc converter and a system of cascaded dc–dc converters are discussed. Finally, prototypes of a buck converter, a boost converter, and a cascaded system of buck and boost converters are constructed to verify the effectiveness of the approximate discrete-time model. [ABSTRACT FROM AUTHOR]

This paper proposes a new single-phase single-stage switched-boost inverter with four switches. Like the quasi-Z-source inverter and quasi-switched boost inverter (qSBI), the proposed inverter has the main features as continuous input current, buck/boost voltage with single-stage conversion, and shoot-through immunity. Compared to the qSBI, the proposed inverter uses one more capacitor and one less switch. This paper presents the operating principles, pulse-width modulation control strategy, parameter design guidelines, and simulation results for the proposed inverter. To verify the performance of the proposed inverter, an 800-W prototype was built with an 110 V/50 Hz output voltage in stand-alone and grid-connected modes. The simulation and experimental results matched those of the theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper presents the active capacitor voltage-balancing (ACVB) methods based on the dynamic model for a five-level nested neutral-point piloted (NNPP) converter using hybrid carrier modulation. The traditional hybrid carrier modulation provides natural voltage balancing of floating capacitors and dc-link capacitors. First, the natural voltage-balancing ability under steady-state and ideal conditions is theoretically proved. However, there are accumulated errors and deviations of capacitor voltages in practical applications, especially under dynamic conditions. In order to address the accumulated errors and deviations of capacitor voltages, the dynamic models of floating-capacitor voltages and neutral-point voltage are established. Moreover, the ACVB method based on the dynamic model of the neutral-point voltage is proposed by injecting the zero-sequence voltage. And the ACVB method based on the dynamic model of floating-capacitor voltages is proposed by introducing the adjustment variables. The proposed ACVB methods have the advantages of simple formula, definite physical meaning, and high accuracy. Furthermore, the output voltage quality and current quality are evaluated in term of total harmonic distortion and the effect of model parameter mismatch on the proposed ACVB methods is presented. Finally, the comparative simulation and experimental results verify the correctness of the proposed ACVB methods based on the dynamic model under different conditions. [ABSTRACT FROM AUTHOR]

Conventional centralized control strategies may reduce the flexibility and expandability of a modular multilevel converter (MMC) system. To tackle this issue, this paper proposes a distributed control architecture that is capable of assigning certain control tasks to distributed local controllers and improves the modularity of an MMC system. A central controller dealing with the output current regulation based on sensed arm currents is adopted. The control of MMC internal dynamics and the pulsewidth modulation (PWM) generation are distributed into local controllers. Unlike the conventional MMC control that needs all submodule capacitor voltages for capacitor voltage averaging, the proposed capacitor voltage control only relies on local submodule voltage measurement. Consequently, communication-intensive capacitor voltage transmission in each control cycle is not required and the communication burden of the control system can be significantly reduced. The control loops and possible control conflicts among submodules are presented and considered for system stability analysis. The effectiveness of the proposed distributed control architecture and capacitor voltage control for an MMC are confirmed by the start-up, steady state, and transient experimental results. [ABSTRACT FROM PUBLISHER]

This paper presents a general space vector modulation (SVM) method for the modular multilevel converter (MMC). Compared with earlier modulation methods, the proposed SVM method not only utilizes the maximum level number (i.e., $2n+ 1$, where $n$ is the number of submodules in the upper or lower arm of each phase) of output phase voltages, but also leads to an optimized control performance in terms of capacitor voltage balancing, circulating current suppression, and common-mode voltage reduction. The maximum level number is achieved by introducing a new equivalent circuit of the MMC, and the optimized control is obtained by selecting the optimal redundant switching states. Since the computational burden of the SVM scheme is independent of the voltage level number, the proposed method is well suited to the MMC with any number of submodules. Simulation and experimental results are presented to validate the proposed method. [ABSTRACT FROM PUBLISHER]

In the traditional three-resistor-based current sampling scheme, the sampled currents will become inaccurate when the duration of zero-voltage vectors of an inverter is too short, which leads to a limited modulation index (MI). To overcome this problem, an improved three-resistor sampling method is proposed by establishing a predictive current model of an inverter load, which is that of an induction motor on the synchronous rotating frame for the demonstration purpose in this paper. The principle of this method is detailed in the paper. Then a simulation model of a vector-controlled induction motor drive that utilizes the proposed current sampling scheme is built in the Simulink environment. Finally, the experiment on the new sampling scheme is performed in both steady-state and dynamic conditions. The results verify that the existing current sampling problems can be solved effectively and the motor can perform well with higher MI under the new scheme. As a result, the loading capacity of the system can be enhanced notably. [ABSTRACT FROM PUBLISHER]

Huge voltage spikes on auxiliary switches is a common issue for most of the existing zero-current switching (ZCS) pulsewidth-modulated (PWM) converters. The reason for the spike lies in the parasitic resonance between the resonant inductance and the stray output capacitance Coss of the auxiliary switch, which does not have the negative impact in zero-voltage switching (ZVS) converters. This paper proposes a low-stress ZCS technique to eliminate the negative consequence of the Coss in ZCS PWM converters. All the power devices, including the auxiliary switch, show low voltage stresses and ZCS. The auxiliary cell of the low-stress ZCS technique introduced a clamping diode to realize the low-voltage stress for the power devices. The low-stress ZCS buck converter is taken as an example to explain both the low-stress and ZCS characteristics. A 2-kW hardware prototype is developed. The simulation and experiment results both validate the effectiveness of the proposed low-stress ZCS technique. [ABSTRACT FROM AUTHOR]

The noninverting buck–boost converter has attracted significant attention in the photovoltaic (PV) module integrated application, as it offers high efficiency while maintaining a low cost and a simple topology. When this converter is employed, special care must be taken at the transition between buck and boost operating modes, as a dead-zone in the voltage transfer function can cause abrupt perturbations in the controlled voltage, decreasing the regulation quality and ultimately lowering the power conversion efficiency. In this paper, a new dead-zone compensation technique is proposed with the scope of smoothing the transition between operating modes, eliminating the voltage ripple and improving the regulation performance, while maintaining high efficiency. The converter under analysis is studied together with its gate driving circuit, which is based on a bootstrap capacitor power supply for the high-side switches. The proposed dead-zone compensation technique is deduced by using the principle of maintaining the ideal voltage gain function across the converter operating range. The technique is analyzed, implemented and tested on a purposely built PV module integrated noninverting buck–boost converter. The experiments reveal a sensible improvement of the voltage regulation during mode transition, confirming the effectiveness of the proposed technique and its fitness for the PV application. [ABSTRACT FROM AUTHOR]

Due to the development of integrated electronic appliances, independently controlled multiple-output dc–dc converter prototypes have started to emerge in various forms, offering advantages of more compact size and cheaper cost. However, the existing converter topologies are capable of regulating outputs only with the help of auxiliary converter circuits and additional switches. The converter also fails to control all of the outputs independently when the converter has a greater number of output stages than that of the peripheral switching/linear regulators. Therefore, in this paper, a novel dc–dc converter prototype is proposed that can be utilized to construct independently controlled multiple-output converter topology with a single PWM signal driving the primary inverter switches. Feasibility, design challenges, and practical considerations are discussed in this paper with a design example of an independently controlled four-output, 356-W resonant converter system. [ABSTRACT FROM AUTHOR]

The recent advancements in power switching device material and manufacturing technology have enabled the design of highly efficient and compact high-speed motor direct drives. The use of high-switching frequency pulse width modulation in these drives provides speed and torque control capabilities and it can also serve as an effective phase current shaping method for torque ripple minimization. This paper builds upon the previous paper introducing a torque ripple minimization technique for gallium nitride high-electron mobility transistor-based high-speed single-phase brushless dc motor drive. It presents an in-depth performance analysis in comparison with the conventional high-speed control techniques. Four different high-speed control techniques are implemented and tested to quantify the maximum speed, efficiency, torque ripple, and vibration. The vibration of the motor drive is measured using a microelectromechanical systems accelerometer with a ferroelectric random access memory for high-speed data acquisition with the maximum bandwidth of 1 kHz. [ABSTRACT FROM PUBLISHER]

This paper presents a novel six-pulse low-frequency (LF) fluctuating high-voltage dc-bus-based power system architecture for fuel cell vehicles (FCVs) application. A novel hybrid modulation scheme consisting of six-pulse modulation at LF scale and modified secondary modulation and 33% pulse width modulation at high-frequency (HF) scale is proposed. Three-phase ac waveforms for the propulsion system of FCVs are generated from LF fluctuating high-voltage dc bus. The proposed modulation technique significantly reduces the switching losses of the bidirectional dual-stage inverter: 1) soft-switching of both sides of the front-end current-fed full-bridge converter is realized; and 2) at any moment, only one leg of back-end three-phase inverter is switched at HF, while the other two legs are kept in on or off states. This tremendously reduces the bidirectional inverter's switching losses and improves the system efficiency. The LF fluctuating high-voltage dc bus allows the elimination of large electrolytic dc-link capacitor, which contributes to a more reliable and compact design. This paper presents the operation, analysis, and design of a bidirectional inverter implementing the proposed hybrid modulation technique. Simulation results obtained from power electronics simulation software PSIM and experimental results from the lab prototype clearly validate the effectiveness of the proposed modulation technique. [ABSTRACT FROM PUBLISHER]

Insertion of dead time in space vector pulse width modulation (SVPWM) causes phase voltage and current distortion or even zero-current clamping phenomenon, degrading the control performance of ac induction motor. In addition, analysis of distortion becomes more complicated due to the existence of parasitic capacitance in power switching device of voltage source inverter (VSI). This paper tries to make clear that how the parasitic capacitance influences VSI's output independently. First, an equivalent circuit of VSI containing parasitic capacitance is constructed. On that basis, mathematical expression of phase voltage distortion is derived from Kirchhoff's voltage law, Kirchhoff's current law, and charge and discharge characteristics of capacitance. Moreover, through the division of multiple zero-crossing regions in one phase current period, the difficulty of obtaining specific phase voltage error expressions is overcome. Second, to figure out the effect of parasitic capacitance, it is theoretically discussed in detail that how parasitic capacitances of different values affect phase voltage, current distortion, and zero-current clamping phenomenon. At last, simulations and experiments are carried out in which VSI with different parasitic capacitances is constructed by paralleling additional capacitors and with phase voltage feedback methods, the theoretical analysis can be verified. [ABSTRACT FROM PUBLISHER]

This paper introduces series work of common-mode (CM) voltage reduction for the paralleled inverters. The paralleled inverters’ phase-legs are connected through coupling inductors and the combined three-phase currents are provided to the load. Interleaving is an approach to reduce the CM voltage for the paralleled inverters but it cannot eliminate CM voltage. A novel pulse-width-modulation (PWM) method for paralleled inverters which can theoretically achieve zero CM voltage is developed. Considering the basic voltage vectors in each inverter, novel paralleled voltage vectors which have zero CM voltage are proposed to combine the reference voltage vector. The action time's distribution and voltage vectors’ sending sequence for each inverter are also introduced. The proposed PWM method can make sure the voltage of the two inverters are balanced in each switching cycle and limits the circulating current through small coupling inductors. Similar to interleaving space vector PWM, the proposed zero CM PWM also has the ability to reduce the output current ripple and electromagnetic interference (EMI). Simulation and experimental results are provided to show the advantage of paralleled inverters in CM voltage reduction and validate the proposed method has good performance to reduce CM current and CM EMI noise. [ABSTRACT FROM PUBLISHER]

This paper proposes a comprehensive analytical LCL filter design method for three-phase two-level power factor correction rectifiers (PFCs). The high-frequency converter current ripple generates the high-frequency current harmonics that need to be attenuated with respect to the grid standards. Studying the high-frequency current of each element proposes a noniterative solution for designing an LCL filter. In this paper, the converter current ripple is thoroughly analyzed to generalize the current ripple behavior and find the maximum current ripple for sinusoidal pulse width modulation (PWM) and third-harmonic injection PWM. Consequently, the current ripple is used to accurately determine the required filter capacitance based on the maximum charge of the filter capacitor. To choose the grid-side inductance, two methods are investigated. First method uses the structure of the damping to express the grid-side filter inductance as a function of the converter current ripple. Reducing the power loss in the filter and optimizing the grid-side filter inductance is the main focus of the second method which is achieved by employing line impedance stabilization network (LISN). Accordingly, two LCL filters are designed for a 5 kW silicon-carbide-based three-phase PFC. Various experimental scenarios are performed to verify the filters attenuation and performance. [ABSTRACT FROM PUBLISHER]

A dual-buck inverter (DBI) possesses no shoot-through worries and can boost efficiency by using power mosfet s. The main drawback of a DBI is the use of more inductors than in a traditional full-bridge inverter. This greater number of inductors decreases the power density and increases system cost. In this paper, a modified cascaded full-bridge DBI is proposed. It retains all the advantages of the conventional cascaded full-bridge DBI, possesses no shoot-through issues, and can be operated with no pulse-width-modulation dead-times. It can be implemented with power mosfet without reverse recovery issues of a body diode to boost efficiency. The cascaded modules in the proposed inverter share current limiting inductors. Therefore, the number of inductors and inductor footprints, the complexity of the circuit layout, required inductance, and magnetic volume can all be decreased. To show the advantages of the proposed inverter, detailed theoretical analysis and experimental results are provided. [ABSTRACT FROM PUBLISHER]

A widely adopted multilevel converter topology is the cascaded H-bridge (CHB), as it can provide voltage and power scalability. However, since the CHB converter can be composed by cells with different remaining lifetime, it could be useful to delay a fault of higher aged cells in order to prolong the entire converter's lifetime. In this paper, a thermally compensated discontinuous pulse width modulation (DPWM) strategy is proposed in order to reduce the thermal stress for power semiconductors in power modules of higher aged cells. Considering the thermal cycles as the most influencing cause of wear out of power modules, the proposed method compensates the thermal cycles under a varying power profile by manipulating the clamping angle of the DPWM. Moreover, the proposed method obtains a comparable total harmonic distortion performance to the phase-shifted carrier modulation. [ABSTRACT FROM PUBLISHER]

This paper presents a current sensorless technique for current-driven full-bridge dc/dc converters. The proposed technique is able to precisely estimate the transformer current and in turn input/output current of the converter. Since the high-frequency current is estimated, different current-based modulations schemes (e.g., self-sustained oscillating control (SSOC), modulators for synchronous rectifications, etc.) can be implemented using the proposed current sensorless technique. In the proposed technique, the current is estimated using the precise model of dc/dc converters instead of the averaged model. Thus, the accurate current waveform is derived within a switching cycle. The mathematical analysis of the system observability and the practical concerns related to the implementation of the proposed technique are also described in detail. Experimental results on a current-driven dc/dc converter are presented to show the feasibility of the proposed technique and verify its performance. [ABSTRACT FROM AUTHOR]

In this paper, a high efficiency dc–dc buck converter with two-step digital pulse width modulation (DPWM) and low power self-tracking zero current detector (ST-ZCD) is proposed for Internet of Things (IoT) and ultralow power applications. The hybrid DPWM core with high linearity and low power consumption is proposed to implement the high efficiency DPWM dc–dc converter. It is composed of a two-step delay control using the counter and delay line. An adaptive window analog to digital converter is proposed to reduce the output voltage ripple within 20 mV. A dead time generator is implemented with the proposed ST-ZCD to minimize the reverse current. The ST-ZCD can improve efficiency by reducing the control loss that accounts for a large proportion of the dc–dc converter. Also, all digital type-III compensator is implemented for the low power and small die area. This chip is fabricated with a 55 nm CMOS process, which uses the standard supply voltage of 1.5–3 V to generate the output voltage of 1.2 V. The total active area is 500 μm × 300 μm. The measured peak efficiency of the DPWM dc–dc buck converter is 91.5% with a quiescent current consuming only 130 μA. [ABSTRACT FROM AUTHOR]

This paper presents a simple method to analyze the behavior of feedback loops that contain a naturally-sampled single-edge pulse-width modulator. A small-signal model is derived by means of simple geometric arguments. It is shown how this small-signal model can be used to analyze the stability of the continuous-time pulse-width modulated feedback loop by using standard $z$-domain techniques. The strategy relies on familiar concepts like transfer functions and small-signal gains and does not require any in-depth knowledge of nonlinear systems. A simple design process, where the continuous-time compensator is designed directly in the $z$-domain, is developed and detailed design equations are derived for a PI current regulator. It is shown how the proposed strategy can accurately predict instability that cannot be explained by means of the well-known average model of the pulse-width modulator. The theoretical analysis is confirmed by means of detailed time-domain simulations. The mechanisms that lead to instability are discussed and an equation for the critical loop gain is derived. [ABSTRACT FROM PUBLISHER]

This paper analyzes synchronization strategy for cascaded H-bridge multilevel inverter (CHBMLI) topologies with a carrier-based sinusoidal phase-shifted pulse width modulation (PSPWM) technique. In the PSPWM technique, a separate carrier is used for each H-bridge (HB). The carriers are generally phase shifted from each other by π /x rad (x = No. of HBs) for unipolar PWM. With the carrier frequency being an integer (odd/even) multiple of the fundamental frequency, it is observed that the positions of zero crossings of the carriers with respect to the zero crossings of voltage references play an important role for maintaining quarter-wave symmetry among multilevel inverter pole voltage waveforms. This paper analytically shows the conditions for half-wave symmetry and quarter-wave symmetry and experimentally verifies those conditions for the PSPWM technique with a five-level CHBMLI laboratory prototype. [ABSTRACT FROM PUBLISHER]

Power electronic transformers (PETs) offer the advantage of size and weight reduction compared to line-frequency transformers by operating at much higher frequencies than line frequency. In this paper, a push–pull-based ac/dc PET has been proposed and analyzed. The PET offers bidirectional power flow between single-phase ac and dc, using the dual-active bridge principle. Such a system may find applications in interfacing plug-in hybrid and electric vehicles to the grid. The proposed PET offers advantages of open-loop unity power factor operation, soft switching of secondary-side converter power switches for all operating points, high power density owing to use of a high-frequency transformer, and high utilization factor (UF), compared to previous work. Analysis has been done for power transfer, UF, and soft switching. Simulation and experimental results have been provided to demonstrate the operation of the PET. [ABSTRACT FROM PUBLISHER]

The performance of modular multilevel converters (MMCs) in medium-voltage applications, where the number of required submodules is not high, can be improved utilizing low switching frequency modulations such as (2N+1) selective harmonic elimination-pulse width modulation (SHE-PWM), which provides tight control of lower order harmonics and low switching losses. This paper proposes a calculation method, which is based on a novel formulation, to solve the SHE-PWM problem. In particular, MMCs with (2N+1) phase output voltage levels are considered, obtaining a (2N+1) SHE-PWM waveform. This method utilizes a unique system of equations that is valid for any possible waveform. Therefore, it is able to calculate simultaneously, without predefined waveforms, both the switching patterns and the associated firing angles that solve the (2N+1) SHE-PWM problem. Consequently, the search process is simplified and optimized. Furthermore, this paper also proposes a circulating current control technique, which can be applied along with (2N+1) SHE-PWM without disturbing the phase output voltage. Simulation results and experimental tests obtained with a single-phase laboratory prototype prove the validity of the novel (2N+1) SHE-PWM implementation method and the proposed circulating current control technique. [ABSTRACT FROM PUBLISHER]

This paper analyzes the use of the voltage distortions in pulse width modulation voltage-source inverters caused by the inverter switching for islanding detection purposes. The nonideal characteristics of the inverters, mainly due to the dead time needed to have safe commutations, produce fundamental frequency-dependent harmonics (−5th, 7th, …) in the output voltage. These harmonic order are, in principle, an unwanted effect, as they reduce the power quality. However, they can potentially be used for islanding detection purposes. The physical principles of the method would be the same as for high-frequency signal injection methods that have already been proposed, but without the need of injecting a high-frequency signal, behaving, therefore, as a passive islanding detection technique. [ABSTRACT FROM AUTHOR]

This paper targets the reduction of common-mode voltage in an indirect matrix converter (IMC) through an intelligent space-vector-based modulation technique. This mode of control results in lower dV/dt at the motor terminals, thereby, reducing voltage stress to windings; and reduced output voltage distortion resulting in lower machine losses. The conventional indirect space vector pulse-width modulation method of controlling matrix converters involves independent control of either the rectifying stage or the inverting stage of the converter. However, in this paper, by suitable selection of space vectors, the rectifying stage of the matrix converter generates different levels of virtual dc-link voltage. Therefore, the responsibility of formulating output voltages with a particular magnitude and frequency, which can be translated to different machine speeds, has been transferred solely to the rectifying stage of the IMC. Estimation of the degree of distortion in the three-phase output voltage is another facet discussed in this paper, which aids the sizing and designing of output passive filters. The analysis of output voltage distortion and the proposed modulation strategies have been substantiated by simulations in MATLAB/Simulink and experimentally verified on a scaled down laboratory prototype. [ABSTRACT FROM AUTHOR]

This paper presents two hybrid six-phase machine drive systems. The topologies are considered to be hybrid because two three-phase groups of the machine are fed by different types of converters. The purpose of these topologies is to be alternative configurations, being midway between the conventional six-leg two-level (2L) inverter, composed of 12 switches, and more complex structures, such as the six-leg three-level neutral point clamped (3L-NPC) inverter, composed of 24 switches and 12 clamping diodes, or the conventional 12-leg dual inverter, composed of 24 switches. One of the hybrid topologies is composed of 18 switches and the other is composed of 18 switches and 6 clamping diodes. A comparative study of harmonic distortion, semiconductor losses, and machine torque ripple is performed. Compared with the conventional 2L inverter, the proposed systems provide better performance in terms of harmonic distortion, overall semiconductor losses, and machine torque ripple and are less complex than dual and NPC inverters. Pulse width modulation (PWM) strategy is discussed and simulated. A modification in PWM strategy of the hybrid configurations is performed in order to obtain similar torque ripple to the cases when dual and 3L-NPC converters are used, even with lower number of semiconductor devices. Experimental results are also presented in order to validate the PWM strategy. [ABSTRACT FROM AUTHOR]

This paper presents a retention/ pulse frequency modulation (PFM)/ pulse width modulation (PWM) mode dc–dc buck converter with adaptive zero current detector (AZCD) and spread spectrum clock generation (SSCG) for IoT/Wearable systems. The proposed dc–dc buck converter is capable of handling loads from 10 μA to 20 mA with high efficiency by applying triple mode (retention mode, PFM mode, and PWM mode), gate split technique, and AZCD. Retention mode is proposed to extend wide load range at ultralight load. Gate split technique adjusts the conduction loss and switching loss. AZCD reduces the operation duty of the high-speed comparator and avoid reverse current below light load. In IoT applications, each node communicates with other nodes through a Bluetooth low energy transceiver, which consumes very low current and is highly sensitive to supply noise. Therefore, the proposed dc–dc buck converter adopts the SSCG technique to reduce electromagnetic interference by up to 18 dB. This chip is implemented using 0.13 μm CMOS technology with an active area of \text820\times \text800\;\mu \textm^2. The maximum power efficiency of the proposed dc–dc buck converter is 92.4% at a switching frequency of 2.5 MHz when the load current range is 10 to 20 mA. The input voltage range and the regulated output voltage are 2.2–3.3 and 1.7 V, respectively. In addition, the proposed dc–dc buck converter achieves over 74.2% efficiency in retention mode when the load current range is from 10 to 500 μA. [ABSTRACT FROM PUBLISHER]

This paper proposes a current-fed isolated bidirectional dc–dc converter (CF-IBDC) that has the advantages of wide input voltage range, low input current ripple, low conduction losses, and soft switching over the full operating range. Compared with conventional CF-IBDCs, the voltage spikes of the low-voltage (LV) side switches in the proposed converter can be eliminated without additional clamp circuits. The converter adopts the pulse width modulation plus hybrid phase-shift control scheme such that the bus voltage can match the output voltage by means of the transformer. Thus, the current stresses and conduction losses of the converter become lower. In addition, the practical zero voltage switching (ZVS) of the secondary-side switches can be realized by adjusting the phase-shift angle within the secondary side when in light load or no load condition. The operating principles and characteristics including the power transfer, root-mean-square (RMS) current, and soft switching are investigated in detail. Then the design guidelines of inductors are also given. Finally an experimental prototype with 30–60 V input and 400 V/2.5 An output is built to verify the correctness of theoretical analyses. [ABSTRACT FROM PUBLISHER]

A new zero-sequence circulating current (ZSCC) reduction method for multimodule voltage source inverters (MVSIs) consisting of P three-phase inverters that are connected in parallel is proposed in this paper. Four-switch inverter modules are used instead of the conventional six-switch modules to reduce the cost. In this paper, the effectiveness of the proposed ZSCC reduction method is studied using selective harmonic elimination pulse width modulation. The proposed ZSCC reduction method can remove about P times the number of harmonics using the same switching frequency as compared to more conventional methods, as explained later in this paper. The concepts discussed in the paper are confirmed with results obtained from an MVSI experimental prototype. [ABSTRACT FROM AUTHOR]

Several novel digital assistant power integrated technologies (DAPITs) for power management unit (PMU) to reduce the designing complexity, as well as to keep good performance in scaling CMOS process, are proposed in this paper. The DAPITs include segment power driving with pulse skip modulation/pulse width modulation and loop regulating with digital regulation circuit for dc-dcs in PMU, calibrating digital-to-analog converter (DAC) with resistance compensation network for dynamic voltage scaling (DVS), and separating phase clock for multi-dc-dcs in PMU. With these DAPITs, the efficiencies and output accuracies of dc-dcs are increased, the DVS signal sent by DAC is linear, and current ripples in PMU are reduced. In this paper, a PMU embedded into system-on-a-chip (SoC) is designed based on a 0.13-μm CMOS process. The designed PMU includes four dc-dc buck converters and two LDOs. This paper introduces the top structure of the PMU and the main proposed DAPITs. Simulation and test results show that the output voltages of the dc-dc converters in the PMU can be changed by external resistors and regulated from 0.7 to 1.8 V stepped with 25 mV by SoC load through interface. And the maximum efficiency of the dc-dcs with DVS in the PMU is more than 90%, while, with an external resistor, it can reach to 95%. [ABSTRACT FROM AUTHOR]

The imbalance in the currents of strings of LEDs will cause fast degradation or even failure in some LEDs. Such current imbalance should be avoided. To balance the common average current, a small duty cycle may necessitate a large LED turn-on current amplitude, which may cause temporal overheat and low luminous efficacy of the LEDs. This paper presents a current balancing method based on pulse-width modulation of a common bus voltage to each LED string to achieve the intended average current. An optimal feedback control scheme is proposed to maximize the duty cycles and minimize the bus voltage. As a result, at least one of the LED strings is operating at unity duty cycle. The analysis, implementation, and verification are detailed in this paper. [ABSTRACT FROM AUTHOR]

A comprehensive method of electromagnetic emission interference (EMI) reduction in dc/ac inverters through periodic dithering of the pulse-width modulated (PWM) switching frequency is presented in this paper. The periodic dithering is the process of changing the switching frequency of the PWM signal that drives the switches of the power electronics inverter. The effects of the various parameters involved in the PWM dithering process have been analyzed in this paper. The important parameters involved in the dithering process are the frequency range used for dithering, the periodic time of the dithering signal, and the phase of the dithering signal. The effect of each of these parameters has been studied to determine their values that minimize the EMI. Additionally, analytical expressions for theoretical prediction of the EMI levels at different frequencies have been derived for performance analysis during the design stage. The theoretical predictions for the dithering signals have been found to accurately correlate with both the simulation and experimental results. [ABSTRACT FROM AUTHOR]

An improved circulating current control method by applying a digital plug-in repetitive controller is discussed for harmonic elimination of a carrier-phase-shift pulse-width-modulation (CPS-PWM)-based modular multilevel converter (MMC) in this paper. The performance of the controller is analyzed in detail based on an improved circulating current control model with the consideration of the submodule voltage disturbance. It is shown that the proposed control method has the merits of simplicity, versatility, and better performance of circulating harmonic current elimination than the traditional proportional integral controller. The stability analysis of the proposed method are also discussed in the paper as well as the design principles. Finally, the experimental results including the steady-state performance and the transient response are given, which validates the feasibility and excellent performance of the proposed control scheme. [ABSTRACT FROM AUTHOR]

A new soft-switching pulsewidth modulated (PWM) full-bridge converter is proposed in this paper. The outstanding feature of the new converter is that it allows its main power switches to operate with zero current switching (ZCS) and with fewer conduction losses than conventional full-bridge converters. This is achieved by using two very simple active auxiliary circuits—one active, the other passive. The paper presents the new converter and then discusses its operation, steady-state characteristics, and design. Experimental results obtained from a 3 kW converter prototype are presented to validate the converter's performance and the concepts presented in the paper. [ABSTRACT FROM AUTHOR]

Compensating the grid background harmonics in a grid-interfacing converter system, such as a drive system's active-front-end rectifier or a grid-connected inverter in a distributed generation system, is an effective method of reducing line side current harmonics. However, this harmonic compensation is particularly challenging in medium-voltage high-power applications (>1 MVA). This is mainly due to the low-switching frequency operation of high-power converters (300–800 Hz) to maintain low power loss. Therefore, the traditional tasks of active power filters with relatively high-switching frequency cannot be easily realized here. This paper proposes a new pulse width modulation technique, named selective harmonic compensation (SHC), which actively compensates the power system background harmonics, but still operates at very low-switching frequencies. Details of the proposed SHC are presented. An SHC application example on a high-power current-source rectifier is provided in this paper. The simulations and experiments show that the proposed SHC scheme can effectively compensate the system background harmonics and improve the line current harmonic performance. [ABSTRACT FROM AUTHOR]

The digital implementations of Sinusoidal Pulse Width Modulation (SPWM) generators have dominated over their counterparts based on analog circuits. In this paper, an FPGA-based SPWM generator is presented, which is capable to operate at switching frequencies up to 1 MHz (requiring FPGA operation at 100-160 MHz), thus it is capable to support the high switching frequency requirements of modern single-phase dc/ac power converters. The proposed design occupies a small fraction of a medium-sized FPGA and, thus, can be incorporated in larger designs. Additionally, it has a flexible architecture that can be tuned to a variety of single-phase dc/ac inverter applications. The post-layout simulation and experimental results confirm that compared to the past-proposed SPWM generation designs, the SPWM generator presented in this paper exhibits much faster switching frequency, lower power consumption, and higher accuracy of generating the desired SPWM waveform. [ABSTRACT FROM AUTHOR]

The five-level active neutral-point-clamped (5L-ANPC) converter has been widely studied for its excellent performance in high-power medium-voltage applications. This paper analyzes the space vector pulse width modulation (SVPWM) strategy of the 5L-ANPC converter in the virtual coordinate, and presents an optimized control strategy which can balance the neutral point (NP) voltage and avoid the dead-time effects for the first time. In this strategy, on one hand, the 125 space vectors are combined by 96 triangles in the seven-segment vector synthesis method, then the triangles are divided into seven categories which have different characteristics of balancing the NP voltage, and every category has its own principles to choose the vector sequence and compute the vector durations. On the other hand, the dead-time effects of the 5L-ANPC converter are studied in detail and the transitions between different switching states are constrained in the optimized control strategy to avoid the dead-time effects that cannot be compensated by traditional pulse-based dead-time compensation methods. Finally, the optimized SVPWM strategy is experimentally verified in this paper. [ABSTRACT FROM AUTHOR]