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Bipolar repetitive high-voltage pulse generators are commonly used in modern pulsed power applications. Conventionally, bipolar high-voltage pulses can be generated by adding a high-voltage H-bridge at the output stage of a unipolar high-voltage pulse generator which increases complexity and cost of the bipolar high-voltage pulse generator. In this paper, a boost-inverter-based bipolar high-voltage pulse generator with high-voltage gain is proposed. The proposed generator can provide high-voltage bipolar output pulses with the desired specifications from a low input dc voltage. The proposed generator is based on employing two bidirectional boost dc–dc converters, where the load is connected differentially between the boost converters’ output terminals. In the proposed approach, four controlled switches are required. Only two out of these four switches are rated at the high-voltage output level which affects positively the system cost. A detailed illustration of the proposed approach along with the design of its passive components is presented in this study. Simulation and experimental results are used to validate the proposed approach. [ABSTRACT FROM AUTHOR]

The four-switch three-phase (FSTP) inverter has been proposed as an innovative inverter design to reduce the cost, complexity, size, and switching losses of the dc–ac conversion system. Traditional FSTP inverter usually operates at half the dc input voltage; hence, the output line voltage cannot exceed this value. This paper proposes a novel design for the FSTP inverter based on the topology of the single-ended primary-inductance converter (SEPIC). The proposed topology provides pure sinusoidal output voltages with no need for output filter. Compared to traditional FSTP inverter, the proposed FSTP SEPIC inverter improves the voltage utilization factor of the input dc supply, where the proposed topology provides higher output line voltage which can be extended up to the full value of the dc input voltage. The integral sliding-mode control is used with the proposed topology to optimize its dynamics and to ensure robustness of the system during different operating conditions. Derivation of the equations describing the parameters design, components ratings, and the operation of the proposed SEPIC inverter is presented in this paper. Simulation model and experimental setup are used to validate the proposed concept. Simulations and experimental results show the effectiveness of the proposed inverter. [ABSTRACT FROM AUTHOR]

An interline dynamic voltage restorer (IDVR) is invariably employed in distribution systems to mitigate voltage sag/swell problems. An IDVR merely consists of several dynamic voltage restorers (DVRs) sharing a common dc link connecting independent feeders to secure electric power to critical loads. While one of the DVRs compensates for the local voltage sag in its feeder, the other DVRs replenish the common dc-link voltage. For normal voltage levels, the DVRs should be bypassed. Instead of bypassing the DVRs in normal conditions, this paper proposes operating the DVRs, if needed, to improve the displacement factor (DF) of one of the involved feeders. DF improvement can be achieved via active and reactive power exchange (PQ sharing) between different feeders. To successfully apply this concept, several constraints are addressed throughout the paper. Simulation and experimental results elucidate and substantiate the proposed concept. [ABSTRACT FROM AUTHOR]