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A single-stage three-phase ac–ac converter benefiting from a high-frequency alternating link voltage is proposed in this paper. In this converter, a very small film capacitor can transfer the energy from the input to the output, owing to the high-frequency alternating voltage of the link. This eliminates the need for large electrolytic capacitors that are typically used in dc-link ac–ac converters. Moreover, a compact high-frequency transformer at the link can replace the bulky low-frequency transformers, in case isolation is required. These features increase the power density as well as reliability of the proposed converter in comparison with the conventional dc-link converters. The number of required switches in the proposed converter is 12, which is less than the number of switches needed in matrix converters, leading to lower switching and conduction losses. Despite being single-stage, the proposed ac–ac converter is capable of both stepping up and stepping down the voltage and also frequency transformation. This eliminates the need for using cascaded power converters. In this paper, the operation principles of the proposed ac–ac converter are investigated, and variable switching frequency and fixed switching frequency control methods for operating this converter are introduced. The performance of the converter is verified through simulation and experiment. [ABSTRACT FROM AUTHOR]

In this paper, a new structure for a nonisolated boost dc–dc converter is proposed. The proposed converter generates higher voltage gain than some conventional nonisolated boost dc–dc converters. In this paper, the voltage and current equations of the elements and voltage gain in continuous conduction mode and discontinuous conduction mode are extracted. Then, the critical inductance converter is extracted and the current stresses in the switches are calculated. To achieve high voltage gain, a generalized structure based on the proposed structure generates for dc–dc converters. Meanwhile, the root mean square current relations of devices are obtained for an extended structure. Finally, the results of PSCAD/EMTDC software and laboratory prototype are used to reconfirm theoretical concept. [ABSTRACT FROM AUTHOR]

This paper proposes a novel method for instantaneous balancing of neutral-point (NP) voltages with stacked multilevel inverters (MLIs) for variable-speed drives. The stacked MLI uses series-connected dc sources and NPs (connecting points of dc sources) to obtain the desired levels. The balancing of NP voltages are obtained by using a low-voltage-capacitor-fed cascaded H-bridge (CHB) per phase of a symmetrical six-phase induction machine (IM), which ensures zero current drawn from NPs (at any given instant). Since no current is drawn from NPs, the single dc-link operation with stacked capacitors is also possible. The scheme is suitable for applications, where low-voltage dc sources and batteries are stacked to form a dc link. A variable-speed operation is done using a seven-level inverter scheme for a symmetrical six-phase IM, which is formed by three dc-link stacked capacitors cascaded with two low-voltage-capacitor-fed CHBs per phase. Furthermore, the method is extended for an open-end IM to obtain a seven-level common-mode eliminated space vector structure using a single dc link. The generalization of this method for any stacked $n$ -level inverter without NP voltage deviation is also presented in this paper. The experimental results and analysis are included to validate the proposed method. [ABSTRACT FROM AUTHOR]

Nonregenerative pulsewidth-modulated (PWM) rectifiers are increasingly being considered for applications, where the power flow is unidirectional, such as power supplies for telecommunications, X-ray, the machine-side converter for wind energy conversion systems, etc. They use fewer active switches, which increase their power density and reduce cost. This paper proposes a novel reduced switch topology for a multilevel (five-level or higher) nonregenerative PWM rectifier. It uses only four controlled switches and eight diodes per phase for a five-level rectifier. Half of the diodes are naturally commutated (zero current switching) at the line frequency, which reduces switching losses. This topology has several other advantages compared to similar topologies reported in the literature, such as minimum voltage stress across the devices, elimination of transient voltage-balancing snubbers, no extra hardware for balancing the flying capacitors, the dc-link mid-point voltage, etc. In this paper, switching cycle average modeling and the carrier-based modulation strategy for this rectifier are also presented to maintain a balanced dc link and to regulate flying capacitor voltages, while achieving unity displacement factor at the rectifier input terminals. The overall performance of the rectifier is verified by experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes a novel two-level single-stage direct ac–ac converter for realizing a 7.2-kV medium-voltage (MV) solid-state transformer (SST) based on 15-kV SiC mosfets. A new current-fed series resonant converter (CFSRC) topology is proposed to address major challenges in MV ac–ac converters such as achieving zero-voltage switching (ZVS) for the MV mosfets across wide voltage and load ranges and minimizing system capacitance. The topology is analyzed with both time-domain analysis and first harmonic approximation to provide useful equations for circuit design. Constant deadtime strategy is adopted, allowing partial ZVS to occur at low-voltage (LV) levels. ZVS behavior over wide voltage range is investigated, and calculation of the associated loss from partial ZVS is presented. System parameters are optimized based on the tradeoff between conduction loss and switching loss. The 15-kV mosfet has been tested continuously at a park voltage of 10 kV and 37 kHz, indicating stable device operation and an extremely high voltage × frequency figure of merit. Moreover, inherent cycle-by-cycle current limiting in the proposed CFSRC under output short-circuit circumstance is realized by paralleling diodes to the LV resonant capacitors. Without employing any additional current sensors, the input and circulating currents are limited to a safe range automatically when the short-circuit occurs. This paper presents detailed short-circuit protection operating principles and peak resonant current equation to aid the design of the resonant tank. A full-scale and compact SST that converts 7.2 kV ac to 240 V ac is developed to verify the theoretical analysis. This is the highest reported voltage rating for two-level-based power converters without device series connection. ZVS is verified and achieved over wide voltage and load ranges with a peak efficiency of 97.8%. A short-circuit experiment is conducted at 3-kV peak voltage to verify the analysis. Experimental results closely match the theoretical analysis. [ABSTRACT FROM AUTHOR]

Power management integrated circuits (PMICs) with on-chip compensation are widely used to power multiple loads in mobile devices with increased power density. However, there are two issues for on-chip compensated PMICs. First, on-chip compensation reconfigurability is required to obtain the appropriate response in various passive components. Second, a converter for a processor requires adaptive voltage positioning (AVP) to reduce the output capacitor size. In this paper, a novel reconfigurable on-chip compensated current-mode buck converter with AVP is proposed to solve the aforementioned issues without requiring high-speed and high-resolution analog-to-digital converter (ADC). A reconfigurable accurate load line control scheme and on-chip compensation are proposed to achieve an accurate load line and AVP in various load lines and passive components. The control scheme, small-signal model, and circuit implementation are illustrated in this paper. The proposed buck converter was implemented into an integrated circuit to verify the analysis. [ABSTRACT FROM AUTHOR]

Rising power demands in more electrical aircraft (MEA) put power converters for commercial airplanes under increasing pressure to fulfill current harmonic distortion regulations as specified, for example, in DO-160G. Today, the implementation of filters is seen as an effective tool for dealing with harmonics; however, their increased weight and volume are not welcomed in the aerospace industry. This paper proposes a circuit, named forced commutation controlled series capacitor (FCSC-rectifier), which is able to maintain low individual harmonic current levels without the need for filter components. The FCSC-rectifier includes a variable capacitive line reactance that interacts in a controlled manner with the inductive line impedance. The result is that the converter input current is nearly purely sinusoidal with a power factor of almost unity. The FCSC-rectifier is to be used for stand-alone variable-voltage, variable-frequency generation systems and can, therefore, power the full authority digital electronic control system (FADEC) in an MEA. This paper shows that the FCSC-rectifier can maintain a high power factor and acceptable current harmonic levels without the use of filters, despite large voltage and frequency variations. A full description of the circuit modes of operation is presented in this paper together with simulation results showing circuit performance characteristics over a range of voltages and frequencies. Results are experimentally verified using a 1-kW test circuit. [ABSTRACT FROM AUTHOR]

In this paper, a new soft-switching bridgeless single-phase power factor correction (PFC) converter is presented and analyzed. Employing an auxiliary switch, the input current dead angle that is the main drawback of the existing buck-type PFCs is omitted, and thus, the power factor (PF) is improved, which is the main contribution of the paper. Proposed PFC converter operates under discontinuous conduction mode (DCM) and draws sinusoidal input current from power supply inherently. All switches and diodes are turnedonandoffunder soft switching, which leads to low switching losses and elimination of diode reverse recovery problems. Also, minimum numbers of semiconductor devices are in the power flow path that reduce the conduction losses. A 120-W laboratory prototype is implemented and experimental results verify the validity of theoretical analysis and show efficiency of 92.1%. In addition, total harmonic distortion (THD) of 3.3% is achieved and the input current harmonics complies with IEC61000-3-2 Class D requirements. [ABSTRACT FROM AUTHOR]

Power converters and electric motor drives when tightly regulated behave as constant power loads. These loads are different from resistive loads and have destabilizing negative impedance characteristics, which impact a system's stability. A boost converter is intrinsically nonlinear and is a nonminimum phase system at the output voltage with respect to the control input. The linear approximation of this boost converter loaded with a constant power load has a zero and poles in the right half of the $s$ -plane, making the system unstable and very difficult to control. Control techniques that employ some form of system inversion cannot be implemented for a nonminimum phase system. This paper describes a technique to modify the nonminimum phase boost converter to a minimum phase for a constant power load, further implementing the input–output linearization technique to stabilize the system. This paper also provides a methodological analysis of the problem followed by the proposed solution. Furthermore, it verifies the analysis of the proposed solution through simulation and experimental results. [ABSTRACT FROM AUTHOR]

A high step-up dc–dc converter is proposed in this paper. The presented converter benefits from some advantages such as high voltage gain and continuous input current, which makes it suitable for the renewable energy applications. The presented converter is based on the SEPIC converter. However, the converter voltage gain is improved by employing a coupled inductor and two voltage multipliers. A passive clamp circuit is also added to the proposed converter that increases the voltage gain and reduces the voltage stress on the main switch. Thus, a switch with low $R_{{\text{DS(on)}}}$ will be needed that decreases the conduction loss. Besides, the voltage stress on the output diode in the proposed converter is reduced, which alleviates reverse recovery problem. The steady-state analysis of the proposed converter is discussed in this paper. The analysis is verified with experimental results under the output power of 245 W. [ABSTRACT FROM AUTHOR]

In this paper, a high step-up quasi-Z Source (QZS) dc–dc converter is proposed. This converter uses a hybrid switched-capacitors switched-inductor method in order to achieve high voltage gains. The proposed converter have resolved the voltage gain limitation of the basic QZS dc–dc converter while keeping its main advantages, such as continuous input current and low voltage stress on capacitors. Compared to the basic converter, the duty cycle is not limited, and the voltage stress on the diodes and switch is not increased. In addition to these features, the proposed converter has a flexible structure, and extra stages could be added to it in order to achieve even higher voltage gains without increasing the voltage stress on devices or limiting the duty cycle. The operation principle of the converter and related relationships and waveforms are presented in the paper. Also, a comprehensive comparison between the proposed and other QZS based dc–dc converters is provided which confirms the superiority of the proposed converter. Simulations are done in power systems computer aided design (PSCAD) in order to investigate the maximum power point tracking (MPPT) capability of the converter. In addition, the valid performance and practicality of the converter are studied through the results obtained from the laboratory built prototype. [ABSTRACT FROM AUTHOR]

This paper proposes a split-capacitor four-wire current source inverter, which is the dual of the split-capacitor four-wire voltage source inverter. Since the midpoint of the dc link is tied to the neutral point of ac filter capacitors, the common-mode voltage (CMV) is reduced significantly. Consequently, the leakage current issue is effectively addressed. The proposed circuit is cost-effective as no extra switch is added. This paper, first, establishes the equivalent common-mode circuit of the proposed inverter. The impact of the neutral line inductance on CMV is also analyzed. Then, a specific modulation is introduced to balance the dc-link voltages/currents. To achieve good input/output performance, a nonlinear control method is developed based on time-domain models. Finally, all the proposed methods and related theoretical analysis are verified by simulations and experimental results. [ABSTRACT FROM AUTHOR]

This paper introduces a new bidirectional single-phase inverter topology. The proposed topology has three ports: a dc port, an ac port, and a ripple port. The ac and dc ports are bidirectional to support rectifier or inverter operation. A small inductor, which is of alternating current, exchanges power between different ports of the single-phase system. The proposed topology is capable of accomplishing voltage step-up or step-down, suppressing the ripple power, and performing inversion or rectification operation in one stage of power conversion. The proposed configuration offers an active decoupling function, which not only eliminates the double-frequency ripple power at the dc port but also achieves minimum capacitance requirements to minimize the size of the decoupling capacitor. This facilitates the use of a very small thin-film capacitor, which offers a much longer life-cycle and higher reliability compared with a bulky electrolytic capacitor. A control approach is also developed to regulate the dc-port and ac-port currents and manage the ripple power through proper distribution of power between each port. Moreover, a very small capacitor can be placed in parallel with the inductor to reinforce the proposed configuration with soft-switching operation, which enhances the overall efficiency and minimizes the voltage stress over the semiconductor devices. This converter is capable of accommodating an arbitrary number of dc or single-phase ac sources and/or loads configuring a multiple-input multiple-output inverter without introducing any additional passive elements or sacrificing the performance of the inverter. The primary focus of this paper is dc-to-ac conversion mode of operation, in spite of the fact that it can easily be configured to serve as a rectifier. Experimental and simulation results are presented to validate the operation of the proposed topology and its control strategy. [ABSTRACT FROM AUTHOR]

Most of the two-stage converters for electric bike battery charging comprise of a boost converter for power factor correction (PFC) followed by a dc–dc converter with universal input voltage. These two-stage conversions suffer from poor efficiency and increased component count. In this paper, a single-stage switched inductor Cuk converter based PFC converter is proposed, which offers high step-down gain, low current stress, high efficiency, and reduced component count. The operational analysis and design equations for various components of the proposed converter are carried out in continuous current mode. This paper presents mathematical modeling, analysis, simulation, and experimentation on the proposed converter rated for 500 W, 48 V/10.4 A. The performance investigation of the proposed converter with respect to power quality indices like voltage total harmonic distortion (THD), current THD, and total power factor is carried out with various types of loads such as resistive load and battery load in both constant voltage (CV) and constant current (CC) mode. Furthermore, the dynamic performance of the proposed converter with battery charging is investigated in CV mode and CC mode with respect to the wide range of supply variations. [ABSTRACT FROM AUTHOR]

Voltage-controlled voltage-source converters (VSCs) are widely applied in islanded microgrids, dynamic voltage restorers, and uninterruptible power supplies, etc. Typically, an LC filter with a large filter capacitance is employed to improve the quality of output voltage and system robustness against external disturbances. Nevertheless, a large capacitance may lead to a low LC-resonant-frequency and cause unstable voltage control of VSCs when a single-loop proportional-resonant (PR) or resonant controller is used. This paper proposes a novel design of single-loop voltage control, where a negative proportional gain is adopted in the PR voltage controller, and it is revealed that the voltage control can be stable even with a low LC -resonant-frequency, e.g., lower than one-third of the system sampling frequency. To tackle the poor dynamic issue introduced by the negative proportional gain, this paper further proposes a closed-loop zeros configuration-based control method, which can flexibly tune the system dynamic response without affecting its stability. Finally, simulation and experimental results are provided to verify the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

This paper proposes a new power decoupling control method for a direct ac-to-ac converter. The ac-to-ac converter consists of two half-bridge converters, two input filter capacitors, and a series-resonant circuit, which enables it to convert the single-phase line-frequency ac input to the high-frequency ac output directly. The proposed power decoupling control method stores input power pulsation at double the line frequency in the input filter capacitors. Thus, the proposed control method realizes a unity power factor in the line-frequency ac input and a constant amplitude current in the high-frequency ac output without any additional switching device or energy storage element. This paper theoretically discusses the principle and operating performance of the proposed control method and confirms the effectiveness of the proposed control method in experiments using an isolated ac-to-dc converter based on the direct ac-to-ac converter. As a result, the proposed power decoupling control method effectively improved the displacement power factor of the line-frequency ac input current to more than 0.99 and reduced the voltage ripple in the dc load to 4%. [ABSTRACT FROM AUTHOR]

In high-power applications, parallel-operated T-type three-level pulse width modulation (PWM) rectifiers (T3LPRs) are widely employed to improve the power capacity and system reliability. For parallel-operated T3LPRs, there are two important issues need to be properly addressed: 1) the neutral-point potential (NPP) balancing, and 2) the zero sequence circulating current (ZSCC) between the common ac and dc bus. In this paper, the fluctuation of NPP in a T3LPR and the generative mechanism of ZSCC in parallel-operated T3LPRs are first investigated. The zero sequence voltage (ZSV) difference between the parallel-operated T3LPRs is identified as the main excitation source of the ZSCC problem. Meanwhile, the disconnection of the neutral point and the control effect difference of NPP balancing in each T3LPR also affect the ZSCCs within the parallel-operated T3LPRs. To adjust the ZSV of T3LPRs, the dwell time of the positive small voltage vector in each switching period of the converter, which is usually adjusted to balance the NPP, is also required to be controlled to suppress ZSCC. Therefore, in this paper, to avoid the possible conflict, an improved modulation mechanism is designed to guarantee simultaneous ZSCC suppression and NPP balancing. The neutral points of each T3LPR are connected. Then, by adjusting the dwell time of the positive small voltage vector, the charging time of two dc capacitors is adjusted to balance the NPP, and the ZSV differences between different T3LPRs are adjusted to suppress ZSCCs. To avoid the control effect difference of independent NPP balancing in different T3LPRs, all T3LPRs share the same value marking the difference between two dc capacitor voltages. Thus, a communication with a greatly reduced baud rate requirement is needed for NPP balancing to transfer the difference between the two dc capacitor voltages. Moreover, no extra circuit is needed for ZSCC suppression. These approaches make the proposed improved space vector PWM strategy much more practical and easy to employ. The proposed method is verified with experiments on two 3-kW T3LPR prototypes. [ABSTRACT FROM AUTHOR]

This paper proposes generation of a 15-level (14 concentric) dodecagonal voltage space vector structure (DVSVS) for a star connected induction motor drive. The proposed multilevel DVSVS is obtained by cascading two inverters, namely a primary and secondary inverter. The primary inverter is a five-level (5L) structure formed by stacking two three-level flying capacitors with individual reduced dc sources and the secondary inverter is also a 5L structure formed by cascading two capacitor-fed cascaded H-bridges (CHB). The active power is supplied by the primary inverter, while the secondary inverter acts as switched capacitor harmonics filter, and capacitors in the secondary inverter are balanced naturally irrespective of load power factor for entire modulation index. The high-voltage dc supply fed primary inverter is operated in quasi-square wave mode, while the high frequency switching is applied to low voltage CHBs, thus, reducing the overall switching loss. The proposed scheme gives the advantages of both DVSVS and multilevel structure, thus, making it one of the solutions for battery or stacked dc-fed applications. The paper also presents the experimental results as well as comparison study with the existing topologies to support the advantages of proposed scheme. [ABSTRACT FROM AUTHOR]

Constant on-time V^2 control for point-of-load buck converters has instability issues in the cases that the output capacitors' RC time constants are small. This paper intensively studies the proposed solution using capacitor current ramp compensation, which is a superior solution featuring fast response and universality. A frequency-domain small-signal model based on describing function method is proposed in this paper. The time-domain large-signal response to the load step change is analyzed. The analysis illustrates the unique transient response behaviors of the capacitor current ramp compensated V^2 control. The design optimization methodology based on frequency-domain and time-domain analysis is presented. The proposed model and the design guidelines are verified by the experimental results. [ABSTRACT FROM AUTHOR]

This paper presents a generalized power-decoupling control scheme using a multiport isolated bidirectional converter for a multilevel inverter, which has multiple dc links inside. In the proposed method, a single power-decoupling capacitor is needed for all the dc links in the multilevel inverter cell. First, a prototype of the power-decoupling concept of individual H-bridge cells in the multilevel inverter is proposed, using a separate power-decoupling circuit. Then, a more advanced one-step power-decoupling method is proposed. The lifetime and reliability of the multilevel inverter is improved as film capacitors replace the large capacitance electrolyte capacitors. A multi-input ports/single output voltage-fed dual half-bridge converter (MDHB) is used for the power-decoupling circuit. A steady-state analysis for the peak and root mean square of the MDHB current is carried out for the loss breakdown. The currents are functions of the switching frequency, phase shift, leakage inductance, turn ratio, and output voltage, which make the multiport transformer design complex. A design methodology is proposed, which takes into account the design of the copper and core losses as functions of the switching frequency and number of turns. Furthermore, a special winding method for the input port is illustrated to obtain identical leakage inductances for the uniform current distribution in the multiport transformer. The proposed MDHB employs a current-sensorless power-decoupling control that contributes to the spontaneous ripple rejection of all the dc links without individual link current information, as well as to the cost and size reduction. Hence, the ripple-rejection controller is independent of the control configuration of the multilevel inverter, and also available for universal applications of various inverter topologies. Since the primary-input ports of MDHB share a single magnetic core for interfacing the ripple power to the unified secondary ripple capacitor, the controller design becomes difficult in considering the dynamic interaction among the ports, along with the average-voltage control loop design. In this paper, the dynamic analysis and controller design procedure of the circuit is also presented. The power decoupling is achieved even when the ripple frequency is other than the double frequency of the inverter output, since the single-pole transfer function of the small-signal model of the MDHB allows sufficient phase margin, along with high bandwidth. The proposed power-decoupling method for the multilevel inverter is validated with the help of simulation and 1.2-kW hardware prototype experimental results. [ABSTRACT FROM AUTHOR]

Class $E^2$ DC–DC converter composed of Class $E$ power amplifier (PA) and rectifier is a promising candidate for MHz wireless power transfer. It is soft-switching based and able to achieve high efficiency at MHz frequency. However, the converter implemented through traditional static design is sensitive to the variations of operation condition. Its performance gets deteriorated when DC load and coil coupling deviate from their respective optimum values. This paper demonstrates that the degradation of system efficiency is mostly due to the mismatch of PA load, and the efficiency drop can be efficiently improved by adding an L-type impedance matching network (IMN) after PA. A fixed IMN is sufficient to maintain a high efficiency, while a tunable IMN is required to ensure stable output power when operation condition dramatically changes. Key techniques, particularly system-level optimization, are discussed in this paper that ensure high efficiency over a wide range of variation in operation condition and also with reduced capacitor/inductor tuning ranges in the IMN. The 6.78-MHz Class $E^2$ DC–DC converters with and without the fixed/tunable IMN are fabricated and measured for validation purposes. The experimental results show that both high efficiency ( $>$66%) and stable output power (around 9 W) are maintained for the tunable converter when there are variations in the DC load and coil coupling. [ABSTRACT FROM AUTHOR]

This paper proposes a new single-phase single-stage switched-boost inverter with four switches. Like the quasi-Z-source inverter and quasi-switched boost inverter (qSBI), the proposed inverter has the main features as continuous input current, buck/boost voltage with single-stage conversion, and shoot-through immunity. Compared to the qSBI, the proposed inverter uses one more capacitor and one less switch. This paper presents the operating principles, pulse-width modulation control strategy, parameter design guidelines, and simulation results for the proposed inverter. To verify the performance of the proposed inverter, an 800-W prototype was built with an 110 V/50 Hz output voltage in stand-alone and grid-connected modes. The simulation and experimental results matched those of the theoretical analysis. [ABSTRACT FROM AUTHOR]

In this article, an adaptive frequency control scheme of a sensorless-receiver inductive wireless power transfer system for battery charging applications is proposed. The mixed-compensation topology is utilized instead of the conventional topologies to deliver power more efficiently. Perturb and observe is proposed to track the optimal operating frequency to achieve maximum transfer efficiency or maximum output power delivery. Moreover, the paper proposes a highly accurate analytical model considering the nonlinear effect of the ac/dc rectifier-stage. Two subsystems are considered: a rectifier based resistive-load, and a rectifier based battery-load. The rectifier based battery-load is represented as a variable ac voltage source. The proposed model is linearized using the first harmonic approximation technique and generalized using the Thévenin's equivalent representation, thus the proposed model can be applied to any compensation topology. Afterward, a systematic approach is developed based on the proposed model to estimate the connected load information including battery voltage based on sender-side measurements only. This results in a smaller size and increased portability of the receiver. A prototype is designed in small-scale with low-power specifications to comply with implantable biomedical applications to demonstrate and validate the proposed model, estimation approach, and frequency tracking experimentally. [ABSTRACT FROM AUTHOR]

In this article, a high-power-density off-line light-emitting diode (LED) driver is proposed. The proposed ac–dc driver is the novel integrated buck and boost converter (IBBC). Besides the high-power-density, the converter shows a high power factor (PF), and a low total harmonic distortion (THD). The IBBC is a two-stage driver that features just one controlled switch, which leads to high PF and low THD operation ensuring high efficiency, and size and cost reduction. Moreover, the switch current is minimized as it conducts the higher of the buck or boost converter, but not the addition of both as in other integrated converters. Moreover, for a further increase of the power-density, a magnetic integration is made by integrating the two inductors of both the buck and boost converters in one core. Thus, the proposed converter has been named as fully integrated buck and boost converter (FIBBC). In this paper, the IBBC is analyzed, and a design methodology is proposed. Also, this article presents a magnetic analysis of the novel FIBBC. In addition, a comparison between two prototypes is presented, one for the IBBC and another for the FIBBC, both of them supplying an LED luminaire of 46 V/ 0.575 A. The FIBBC shows a high PF equal to 0.994, very small THD of 10%, output current ripple of 6%, and efficiency of 92.62%, which represents a landmark on the efficiency of integrated converters. [ABSTRACT FROM AUTHOR]

The soft-switching solid-state transformer (S4T) employs only 12 main active devices and an auxiliary resonant circuit to implement a bidirectional solid-state transformer, with an attractive feature of achieving a full range of zero-voltage-switching conditions for all the main devices. This paper covers detailed design of the power stage, auxiliary resonant circuit, and control of the S4T. The high-frequency transformer is an essential element for the S4T, and it has a unique feature of dc-biased flux. Design of such a high-frequency transformer is also discussed in detail in this paper. Soft startup, shutdown, and fast dynamic response under load transients are also attractive behaviors because of the low inertia of the S4T. Experimental results from a 208-V/10-kV·A S4T unit are presented. [ABSTRACT FROM PUBLISHER]

This paper introduces a non-isolated high step-up dc–dc converter with dual coupled inductors suitable for distributed generation applications. By implementing an input parallel connection, the proposed dc–dc structure inherits shared input current with low ripple, which also requires small capacitive filter at its input. Moreover, this topology can reach high voltage gain by using dual coupled inductors in series connection at the output stage. The proposed converter uses active clamp circuits with a shared clamp capacitor for the main switches. In addition to the active clamp circuit, the leakage energy is recycled to the output by using an integrated regenerative snubber. Indeed, these circuits allow soft-switching conditions, i.e., zero voltage switching and zero current switching for active and passive switching devices, respectively. The mentioned features along with a common ground connection of the input and output make the proposed topology a proper candidate for transformer-less grid-connected photovoltaic systems. The operating performance, analysis and mathematical derivations of the proposed dc–dc converter have been demonstrated in the paper. Moreover, the main features of the proposed converter have been verified through experimental results of a 1-kW laboratory prototype. [ABSTRACT FROM PUBLISHER]

This paper presents a procedure for evaluating self-capacitances and parasitic capacitors between physically adjacent turns in multiconductor systems—with a special focus on single-layer air-core inductors. To this end, the paper proposes the use of standard cells, which correspond to a minimal and basic turn, layer, or macrolevel arrangement of a winding in reference to its patterns of stored electrostatic energy. A standard cell embraces mathematical rules derived by means of a curve fitting approach through a set of finite element analysis (FEA) simulations. Besides, it is applied in a matching routine wherein self- and stray capacitances are evaluated according to the relative position of each turn, layer, or macrolevel arrangement along the length of the winding. Finally, the analytical technique is validated by comparing frequency-domain results obtained from an implemented SPICE model and laboratory measurements. [ABSTRACT FROM PUBLISHER]

This paper analyzes the limitations of a reduced-order model for modular multilevel converters (MMCs) by elucidating the relation between its accuracy, operating frequency, and converter parameters. A reduced-order simplifies the analysis of the MMC and thereby may provide additional information about the converter behavior. However, the accuracy of such model depends on several factors. In this paper, the effect of approximating the converter as a continuous system by neglecting quantization issues associated with having a finite number of modules is studied in detail. The analysis is done based on Fourier-series approximations with which it is possible to elucidate the relationship between the resonant frequencies of the MMC and the error of the reduced-order model. With the Fourier approximation, it is also possible to characterize resonant frequencies of the converter, both numerically and analytically, in terms of the converter parameters. The results can serve as a tool to identify situations when the reduced-order model produces good and also less accurate approximations especially when a low number of modules is available. [ABSTRACT FROM PUBLISHER]

In this paper, a new structure of nonisolated boost dc–dc converters based on voltage-lift technique is proposed. In comparison with conventional nonisolated boost dc–dc converters, the proposed converter generates higher voltage gain. In this paper, the relations between voltage and current of all elements in continuous conduction mode and discontinuous conduction mode are calculated as well as voltage gain in each mode. Then, the critical inductance and stress of switch current are extracted. Finally, the validity of given theories is examined by using the experimental results. [ABSTRACT FROM PUBLISHER]

Cascaded H-bridge (CHB) converter technology is actually the most popular solution for grid-connected converters in both medium- and high-voltage applications. This paper introduces a new control of a single-phase CHB active rectifier. The control uses a direct grid current control based on adaptive resonant controllers. The resonant controllers are adapting to slow fluctuation of ac grid frequency. The challenging problem of CHB converters is dc-link capacitor voltage balancing especially under unbalanced load conditions. This paper presents a reliable voltage-balancing technique utilizing energy estimation of particular dc-link capacitor banks and simple prediction of the changes of their energies. A nonlinear behavior of the converter caused by power semiconductors voltage drops and dead-time effects is minimized by auxiliary adaptive resonant controllers. The resulting control has very good performance, including the operation under unbalanced load conditions, and achieves low total harmonic distortion of converter grid current. The theoretical results were verified by experiments made on the developed CHB active rectifier prototype with three power cells in cascade. [ABSTRACT FROM AUTHOR]

This paper provides an experimental and theoretical discussion on dynamic braking for a medium-voltage induction motor fed by a modular multilevel double-star chopper-cell (DSCC) inverter. It is intended to apply the motor drive to large-capacity fans and compressors with a large moment of inertia. Each chopper cell consists of a bidirectional chopper and a braking chopper connecting a single small-rated braking resistor in series with a single IGBT. This configuration results in a “distributed” dynamic brake that provides a distinctive welcomed side effect of protecting all the bidirectional-chopper cells against sudden overvoltage. An experimental system rated at 400 V and 15 kW is designed, constructed, and tested to verify operating performance of the distributed dynamic brake. Experimental waveforms, along with simulated waveforms, confirm firmly that the distributed dynamic brake is feasible and effective in an induction motor fed by a medium-voltage high-power DSCC inverter for fans and compressors. Finally, this paper gives a design example of a distributed dynamic-braking resistor for the 11-kV, 12-MW induction motor driving a large-capacity fan equipped with a large moment of inertia. [ABSTRACT FROM AUTHOR]

This paper proposes a single-phase power factor correction (PFC) rectifier to achieve high power factor, wide output voltage range, and ripple power decoupling without using electrolytic capacitors. It consists of two parts: PFC circuit and output voltage regulation circuit. The load side is involved in both parts, which is different from the regular two-stage conversion structure. The proposed rectifier can be directly applied to low voltage cases due to the wide output voltage range. And the decoupling capacitor voltage can be smaller than the peak grid voltage, which reduces the voltage stress. Besides, the low-frequency ripple power buffer is implemented without a dedicated power-buffering controller. This paper first introduces the circuit structure, operation principles, and control method. Then, the system design consideration is given. Finally, the effectiveness of the proposed topology is verified by the simulations and experimental results. [ABSTRACT FROM AUTHOR]

An analytical steady-state model of the modular multilevel converter (MMC) can be used for component sizing and assessment of the impact of different parameters on the MMC performance. Thus, this paper proposes an enhanced steady-state model for the MMC, which enables one to calculate the amplitudes of the harmonic components of MMC arm currents, submodule capacitor voltages, and arm voltages. In addition, the proposed model allows for the calculation of the amplitude and phase angle of the modulating signal, and it also presents a criterion for resonance of the arm currents. This is achieved by means of a polynomial function of the modulation index, and through checking the stability criteria established by the proposed model. The capability of formulating the modulating signal enables a more accurate calculation of the steady-state amplitudes of the variables, as compared to the previously published models. This paper also presents an accurate method of submodule capacitor sizing, based on the proposed steady-state model. The proposed method gives the exact value of the submodule capacitance (i.e., the capacitance that results in dc voltage fluctuations within a desired range) for a prespecified submodule capacitor voltage variation and a given circulating current amplitude. The stability criterion given by the proposed steady-state model, used for sizing the arm inductance, and the submodule capacitor voltage variation given by the proposed capacitor sizing method, used for sizing the submodule capacitor, allows for the determining of the operating limits of the MMC in terms of its parameters. Extensive simulation results are presented to demonstrate the efficacy of the proposed steady-state model and the capacitor sizing method. Further, the results obtained from the proposed capacitor sizing method are compared with experimental results from the literature. [ABSTRACT FROM AUTHOR]

In this paper, a single-phase shared leg converter is proposed along with two generalizations. The basic configuration has three two-level insulated gate bipolar transistor (IGBT) legs and is cascaded on the main power system by means of two injection transformers, such that one of these legs is shared between the transformers. The generalizations are expanded cases in which the converter has N\text{leg} legs. The first generalization is the cascaded shared leg (CSL), where the converter is cascaded by N\text{leg}-1 transformers, and one of the N\text{leg} legs is shared between all transformers. The second is the modular CSL, where Nmod modules, each one similar to the basic configuration, are cascaded by 2Nmod transformers. The conventional configurations considered for general comparisons are the cascaded h-bridge (CHB) and the cascaded half-bridge (CHfB). In this paper, we show that proposed configurations provide multilevel ac voltages with greater levels-per-switch ratio compared to the CHB. We also show that proposed CSL generalization has practically the same levels-per-switch than conventional CHfB and saves one transformer. Simulations and experimental results are shown to demonstrate proposed configurations performance and feasibility. [ABSTRACT FROM AUTHOR]

A switched-capacitor-based dual-switch dc–dc converter with a high-boost voltage gain is proposed in this paper. The proposed converter can obtain a high-voltage gain with a small duty cycle, which decreases the voltage stress and the conduction loss on the power switches. This paper presents the key waveforms, the operating principles at the continuous conduction mode and the discontinuous conduction mode, and the parameter design. Moreover, a comparison between the proposed converter and other nonisolated converters has been completed. To verify the operating principle, a 200 W prototype is constructed with an input voltage of 25–50 V and an output voltage of 200 V. The simulation and experimental results are shown. [ABSTRACT FROM PUBLISHER]

This paper presents a novel six-pulse low-frequency (LF) fluctuating high-voltage dc-bus-based power system architecture for fuel cell vehicles (FCVs) application. A novel hybrid modulation scheme consisting of six-pulse modulation at LF scale and modified secondary modulation and 33% pulse width modulation at high-frequency (HF) scale is proposed. Three-phase ac waveforms for the propulsion system of FCVs are generated from LF fluctuating high-voltage dc bus. The proposed modulation technique significantly reduces the switching losses of the bidirectional dual-stage inverter: 1) soft-switching of both sides of the front-end current-fed full-bridge converter is realized; and 2) at any moment, only one leg of back-end three-phase inverter is switched at HF, while the other two legs are kept in on or off states. This tremendously reduces the bidirectional inverter's switching losses and improves the system efficiency. The LF fluctuating high-voltage dc bus allows the elimination of large electrolytic dc-link capacitor, which contributes to a more reliable and compact design. This paper presents the operation, analysis, and design of a bidirectional inverter implementing the proposed hybrid modulation technique. Simulation results obtained from power electronics simulation software PSIM and experimental results from the lab prototype clearly validate the effectiveness of the proposed modulation technique. [ABSTRACT FROM PUBLISHER]

This paper proposes a new battery cell voltage equalization approach using multiple-receiver wireless power transfer (WPT) working at megahertz (MHz). Compared with existing multiwinding transformer, the MHz multiple-receiver WPT system is advantageous in terms of saved weight and space, ease of implementation, and improved safety. In this paper, the unique operating principle of the WPT-based equalization is first explained, through which equalization currents are naturally determined by the battery cell voltage distribution. The currents are also analytically derived. This facilitates the discussion on power amplifier (PA) design. Performance analysis is then provided to investigate the influences of system parameters on the efficiency and equalization ability of the proposed WPT-based equalization system, and thus guide following design and implementation. Considering the uncertainty in PA load due to the random cell voltage distribution, a current-model Class $E$ PA is designed that enables approximately constant PA output current. Experimental results show that the proposed multiple-receiver WPT-based battery cell equalization system can achieve high overall system efficiency (above 71%) when equalizing six lithium-ion battery cells under loosely coupling ( $k$ = 0.065). A good match between the experimental and calculation results also validates the correctness of the theoretical discussion. [ABSTRACT FROM PUBLISHER]

This paper discusses the impact of small dc capacitance in a motor drive using a floating capacitor H-bridge topology. The proposed topology is intended for applications where variable frequency control is not required. Special attention is paid on investigating the second-order dc capacitor voltage ripples, whose influence on the induction motor as well as on the motor drive itself is of importance. This issue is addressed in this paper through rigorous mathematical formulations. It is found that by inverting the second-order dc ripple voltage using the conventional SVPWM, no harmful harmonics will be generated in the motor line voltage. This demonstrates the possibility of drastically reducing the dc capacitance of the proposed system. Induction motor as well as H-bridge performance with respect to different dc capacitance values is demonstrated by experiments, which lays the foundation for cost reduction and reliability enhancement of the proposed system. [ABSTRACT FROM PUBLISHER]

At 13.56 MHz, the circuit parasitic elements strongly affect the stability, performance, and efficiency of the inverter. In this paper, the effect of parasitic elements in the 13.56-MHz half-bridge inverter is analyzed in detail based on the point of view of the high-frequency ringing in the circuit. A proposed inverter design that aims to attenuate the influence of the parasitic elements is presented, including optimized printed circuit board (PCB) design and ringing damping design. The simulation and experiment results show that the proposed PCB design not only reduces the parasitic inductance in the ringing loop but also improves the stability of the inverter by avoiding the subresonant at low frequency and reducing the radiation electromagnetic interference noise. This paper also points out that the ringing current exists in the circuit even with the proposed optimized PCB design lead to the instability of the inverter at high voltage operating condition. The proposed damping circuit significantly suppresses the ringing in the circuit and improves the stability as well as the efficiency of the inverter. The experiment results confirm that by using the proposed design, the half-bridge inverter module using Silicon mosfet is stable at 13.56-MHz switching frequency and its efficiency obtains \text93.1\% at 1.2-kW output power. [ABSTRACT FROM PUBLISHER]

This paper proposes an active switching harmonic current reduction method within the dc-link capacitor of two-level, three-phase, back-to-back converters. This method is based on the derived analytical solution for switching harmonic currents in the dc-link. It is shown that by controlling the pulse width modulation carrier waveform's phase angles, the harmonics in the second carrier band of the rectifier and the inverter can be synchronized such that cancellation occurs in the dc-link capacitor. This synchronization is provided by harmonic phase feedback control. The feasibility of the proposed approach has been verified experimentally and results are presented in this paper. [ABSTRACT FROM PUBLISHER]

This paper presents a hybrid nonisolated dc–dc commutation cell, which is generated by the integration between conventional commutation cell and ladder-type passive switched capacitor (SC) cell. From the resulted hybrid cell are derived three different dc–dc converters: a buck-type, a boost-type, and a buck–boost-type. The three structures are analyzed in this paper and are presented the topological stages, static gain characteristics in continuous conduction mode and discontinuous conduction mode, steady-state analysis. The analyses are generalized in relation to the number of switched-capacitor cells employed, which allows the increase of the rated gain of the converters by adding more SC cells. In addition, the proposed hybrid nonisolated dc–dc commutation divides naturally the voltage stress among the semiconductors and capacitors of the power stage. A 1-kW prototype was developed to verify the operation of the three proposed converters and their theoretical analysis. For the buck-type topology, designed with an input voltage of 600 V and output voltage of 450 V, a peak efficiency of 99.2% and efficiency at rated power of 99% were obtained. [ABSTRACT FROM PUBLISHER]

Hysteretic control provides unique advantages in dc–dc converter applications but it is less popular than other types of control because the switching frequency depends on the operating point, the feedback ripple, and the component parasitics. Furthermore, it is difficult to predict the frequency due to the complex interaction of those factors. This paper proposes harmonic balance analysis to systematically determine the switching frequency of the buck and boost-like converters with hysteretic current control, and extends the method to buck converters with hysteretic voltage control. The analysis includes the most important second-order effects (feedback ripple, component parasitics, a second output capacitor, and switching delays). For the less complex cases the switching frequency is expressed in closed form, and for the more complex cases the paper proposes a graphical solution. The predictions are verified by simulations and, for the buck converter with hysteretic current control, by experiments. The derived results are useful for designing a converter with predictable switching frequency, and can also be employed during the design process of a converter with synchronized or stabilized frequency. Given an arbitrary control scheme or circuit variation, the switching frequency can be readily obtained by following the proposed approach. [ABSTRACT FROM PUBLISHER]

Sheppard–Taylor power factor correction (ST-PFC) rectifier could obtain a high power factor due to its capability of overcoming the control detuning issue. However, it needs a bulky electrolytic capacitor at the load side to buffer the double-frequency ripple power (DFRP), which reduces the reliability and power density significantly. This paper proposes a control method to divert the DFRP to the small energy transfer capacitor. Consequently, the bulky electrolytic capacitor is replaced with a small film capacitor. The proposed method is carried out by introducing the freewheel state (one switch is turned on and the other is turned off) into the control. So no extra hardware is added, which makes the proposed method cost-effective. A low electromagnetic interference emission is also achieved due to the continuous input–output currents. In addition, the proposed method can be extended to other topologies easily. This paper first gives the detailed analysis of the proposed control method, and then introduces the controller design. The selection of the passive components is also briefly discussed. Finally, the simulation and experimental results verify the effectiveness of the proposed control method. [ABSTRACT FROM AUTHOR]

These days, constant on-time current mode (COTCM) control scheme is widely used in the voltage regulator (VR) controllers because it has a higher light-load efficiency and a higher BW design capability while maintaining a simpler compensation requirement. One issue plaguing the COTCM control is its slow transient response which is caused by its fixed TON operation. During the heavy-load step-up transient, the duty cycle becomes saturated and the inductor current increment becomes limited by TON and the minimum off time (TOFF$\_$ MIN) ratio, which can create a large undershoot at load step up. On the other hand, in the load step-down case, if the load step down occurs at the beginning of TON, a large overshoot can be created at the output. To solve this issue, this paper presents a method designed to increase the TON at load step up and then very quickly, decrease at load step down in order to reduce the undershoot and overshoot at output or otherwise save the output capacitor. In this proposed method, the increase or decrease of T ON is proportional to the output change which eliminates the chance of any overcorrection or ring-back problem unlike the methods presented in prior forums. This feature enables the control to work seamlessly in a high-frequency load repetitive case in VR applications. Since this TON change occurs only in the transient period when duty cycle is saturated, it does not affect the small-signal property of the COT control. Moreover, the proposed methods are very much compatible with the state-of-the-art single and multiphase COT control structures. Simulation and test results in both single and multiphase operations are also presented in the paper to verify the proposed concept. [ABSTRACT FROM PUBLISHER]

SiC mosfet has low on-state resistance and can work on high switching frequency, high voltage, and some other tough conditions with less temperature drift, which could provide the significant improvement of power density in power converters. However, for the bridge circuit in an actual converter, high dv/dt during fast switching transient of one mosfet will amplify the negative influence of parasitic components and produce the significant negative voltage spikes on the complementary mosfet, which will threaten its safe operation. This paper proposes a new gate driver circuit for SiC mosfet to attenuate the negative voltage spikes in a bridge circuit. The proposed gate driver adopts a simple voltage dividing circuit to generate a negative gate-source voltage as traditional and a passive triggered transistor with a series-connected capacitor to suppress the negative voltage spikes, which could satisfy the stringent requirements of fast switching SiC mosfets under the high dc voltage condition with low cost and less complexity. An analysis is presented in this paper based on the simulation and experimental results with the performance comparison evaluated. [ABSTRACT FROM AUTHOR]

A novel soft-switching interleaved coupled-inductor boost converter is proposed in this paper. Only a single active soft-switching module is needed to simultaneously achieve the soft-switching property of the two switches in the interleaved coupled-inductor boost converter. The better efficiency is achieved with the less components and cost. The two main switches can achieve the ZVT turn-on and smaller-current turn-off simultaneously when the single active soft-switching module is active. Due to the coupling characteristic of the inductors, the voltages across the two inductors are changed at the same time; therefore, the equivalent circuit is equal to the parasitic capacitors of the two main switches in parallel to resonate with the auxiliary inductor. By coupling two input inductors, the volume and cost of the circuit can be reduced. The interleaved coupled-inductor topology can also reduce the input and output current ripples and share the input and output currents. The operating modes, analysis, and design of the proposed circuit have been discussed in this paper. Simulation and experiments are finally conducted to verify the validity of the proposed circuit. [ABSTRACT FROM PUBLISHER]

This paper presents a comprehensive analysis about bus bar design procedure. Some applications in terms of rated power and shape are investigated regarding their particular requirements and challenges. The dc-link capacitor selection is one of the first and most important steps. It not only dictates the bus bar complexity but also is the key to accomplish a high-power density prototype. Current density and distribution is discussed in this paper based on simulation results. Moreover, the effects of stray inductance and capacitance are explained along with the dc-link capacitors and power semiconductor devices. Simulated results are compared with measurements by a high precision impedance analyzer, which shows the reliability of 3-D modeling-based designs. [ABSTRACT FROM PUBLISHER]

The modular multilevel converter (MMC) has become a very attractive solution for interfacing high voltages in hybrid networks. The MMC enables scalability to different power levels, full controllability provided by insulated-gate bipolar transistors, and can achieve very high efficiencies by using a low-switching-frequency method as the nearest level modulation. However, the nearest level modulation requires a capacitor voltage-balancing algorithm, which can result in unbalanced loading for the power semiconductors in the different submodules. Particularly at low-power-factor operation, which could occur in the case of low-voltage ride through and of reactive power injection, the conventional algorithm is no more effective. This paper provides thermal stress analysis of the MMC in operation and proposes a thermal balancing approach, which is embedded in the capacitor voltage-balancing algorithm. The purpose of the thermal balancing is to achieve similar stress distribution among the different submodules to enhance the lifetime. The junction temperatures in the different submodules are studied for HVDC applications, and this paper proves experimentally that the thermal balance within the submodules is significantly improved. [ABSTRACT FROM PUBLISHER]

DC electric springs (DCES) are emerging technologies for the (i) regulation of mains voltage against the intermittent renewable generations and (ii) harmonic cancellation in dc microgrids. When conventional converter topologies (e.g., half-bridge or full-bridge converter) are adopted as DCES, the battery storage of the DCES has to process both the dc power and the ac harmonic power. The pulsating ac power can severely reduce the lifetime of the battery. To address this issue, a hybrid-DCES (H-DCES) is proposed in this paper to perform (i) and (ii) in a decoupled manner. With a modified topology and control method, the H-DCES can divert the ac current to the ground and retains the function of manipulating noncritical load for dc voltage regulation. The immediate benefits of this H-DCES are the reduction of storage capacity and a prolonged lifetime of the battery. Both the operating principle and the mathematical model of the proposed H-DCES are analyzed in this paper. A prototype of the H-DCES is practically tested in a 48-V dc grid. The experimental results show that the H-DCES can realize the decoupled operation of dc voltage regulation and harmonic cancellation. Simulation studies further demonstrate that the H-DCES requires less storage capacity than its counterparts. [ABSTRACT FROM AUTHOR]

The modular multilevel converter (MMC) with nearest level modulation (NLM) is widely used in the high voltage applications for low switching frequency and easy implementation. Existing literature has not provided a complete submodule (SM) fault ride-through scheme for MMC with NLM. In this paper, a strategy including fault detection, localization, redundancy, and recovery is proposed to ensure continuous operation of MMC under IGBT open-circuit faults conditions. It only requires a few hardware and software resources. The features of MMC and SMs with three types of failures are studied, respectively. Based on these, the fault detection method is proposed by using a simple hardware circuit, thus high computation complexity is avoided. Since current fault localization schemes are limited to MMC with carrier phase shifted pulse width modulation, this paper further proposes a strategy for MMC with NLM to locate the faulty SM and identify the fault type. After this, the fault redundancy and the proposed fault recovery method are applied to eliminate the fault and then exit the failure state. Therefore, the ability of SM fault ride-through can be realized. Analysis of failure characteristics are verified in simulation. Experimental results based on a single-phase MMC prototype with 11 SMs per arm are presented to demonstrate the validity of the proposed fault ride-through strategy. [ABSTRACT FROM AUTHOR]