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This paper proposes a novel polygonal voltage space vector structure (SVS) having 30 sides, for a star-connected induction motor drive. The SVS eliminates the presence of harmonics up to 25th order from motor phase voltage throughout the entire modulation range, providing a torque profile devoid of lower order pulsations. Linear modulation is extended till 99.63% of base speed without exceeding the motor phase voltage rating. Topology consists of a dc-link fed primary inverter and two equal low voltage modular capacitor fed secondary inverters. Here the harmonics generated by the primary inverter is canceled by the secondary inverter which acts as a switched capacitive filter. Detailed description of the SVS generation and timing calculations are provided in this paper. Effectiveness of the proposed scheme is validated using experimental results, inverter loss calculations, and harmonic analysis. [ABSTRACT FROM AUTHOR]

First harmonic analysis (FHA) is arguably the most widely used analytical technique for wireless power transfer (WPT) circuits due to its simplicity. Although FHA can provide closed-form solutions, the existence of rectifier diode forward voltage drop and higher order harmonics, especially the second and third harmonics at variable duty cycle operation, can significantly deteriorate its accuracy. This paper presents an accurate and efficient method called enhanced multiple harmonic analysis (eMHA) for the optimal design and optimal control of WPT systems. The eMHA method considers the nature of nonlinear rectification networks under nonsinusoidal current and reexamines the concept of the equivalent load. As a result, the rectified WPT system is transformed into a series of linear systems with complex load impedances. The steady-state electric quantities can be then explicitly calculated. This enables eMHA to seamlessly work with numerical optimization algorithms to facilitate the automated design and optimization of WPT systems. An example of optimal design and optimal control of a 10 W WPT system is demonstrated. The results obtained by eMHA and FHA are also compared. A prototype of the designed circuit was constructed. The accuracy and effectiveness of eMHA are verified by experimental measurements. This paper is accompanied by a MATLAB-based analytical tool with a graphical user interface demonstrating the effects of circuit variables on electrical quantities and waveforms. [ABSTRACT FROM AUTHOR]

This paper proposes a novel discontinuous pulse-width modulation (DPWM) method to reduce the current harmonics and improve the system efficiency for a single-phase three-level neutral-point clamped inverter. In single-phase inverters, the unipolar pulse-width modulation (UP-PWM) method is commonly used. However, this method has the disadvantage of power losses due to numerous switching operations. Conventional DPWM methods reduce the power losses and improve efficiency but increase the current total harmonic distortion (THD). To overcome these weaknesses, this paper proposes a hybrid DPWM switching method combining two PWM methods: the UP-PWM method and the conventional DPWM method called one-pole clamped PWM method. Since the proposed DPWM method offers all the advantages of both PWM methods, the optimal performance—with regard to the power losses and current THD—is obtained. The combination of two PWM methods is investigated by analyzing the power losses and current THD. Based on the analysis, the process determining the optimal operating condition is introduced. The effectiveness of the proposed DPWM method is demonstrated through simulations and experiments. [ABSTRACT FROM AUTHOR]

This paper proposes generation of a 15-level (14 concentric) dodecagonal voltage space vector structure (DVSVS) for a star connected induction motor drive. The proposed multilevel DVSVS is obtained by cascading two inverters, namely a primary and secondary inverter. The primary inverter is a five-level (5L) structure formed by stacking two three-level flying capacitors with individual reduced dc sources and the secondary inverter is also a 5L structure formed by cascading two capacitor-fed cascaded H-bridges (CHB). The active power is supplied by the primary inverter, while the secondary inverter acts as switched capacitor harmonics filter, and capacitors in the secondary inverter are balanced naturally irrespective of load power factor for entire modulation index. The high-voltage dc supply fed primary inverter is operated in quasi-square wave mode, while the high frequency switching is applied to low voltage CHBs, thus, reducing the overall switching loss. The proposed scheme gives the advantages of both DVSVS and multilevel structure, thus, making it one of the solutions for battery or stacked dc-fed applications. The paper also presents the experimental results as well as comparison study with the existing topologies to support the advantages of proposed scheme. [ABSTRACT FROM AUTHOR]

This paper proposes an active switching harmonic current reduction method within the dc-link capacitor of two-level, three-phase, back-to-back converters. This method is based on the derived analytical solution for switching harmonic currents in the dc-link. It is shown that by controlling the pulse width modulation carrier waveform's phase angles, the harmonics in the second carrier band of the rectifier and the inverter can be synchronized such that cancellation occurs in the dc-link capacitor. This synchronization is provided by harmonic phase feedback control. The feasibility of the proposed approach has been verified experimentally and results are presented in this paper. [ABSTRACT FROM PUBLISHER]

Switching harmonic attenuation has always been challenging for inverters used in high-power conversion applications, where ratio of switching to fundamental frequency is low. Addition of multiple LC-trap filters is no doubt a feasible cost-effective method, which has increasingly been used, but generally susceptible to filter parameter variations and harmonic resonances. This paper hence presents an alternative active trap filter (ATF), based on a series-LC-filtered inverter, for attenuating switching harmonics in a flexible, while yet not cost burdensome, approach. A direct impedance synthesis method has also been proposed for the ATF to better enforce its active switching harmonic bypassing ability. Compared with conventional schemes for controlling active power filters, the proposed method is more readily implemented, since it requires neither current reference generation nor high-bandwidth current control loop. Moreover, the use of a series LC filter at its ac side helps the ATF to reduce its inverter voltage and power ratings. Compensated frequency range of the ATF can hence be enlarged by using a comparably higher switching frequency and a proper step-by-step design procedure to be presented in this paper. Simulation and experimental results have confirmed the design procedures, and hence expected performance of the ATF. [ABSTRACT FROM PUBLISHER]

This paper presents an improved direct torque control (DTC) method for an asymmetrical six-phase induction motor using a two-level six-phase inverter. As is well known, a simple extension of three-phase DTC technique to an asymmetrical six-phase motor, using large vectors only, introduces significant current harmonics of the order 6 n±1 (n = 1, 3, 5,…), which are mapped into the nonflux/torque producing (xy) plane. These harmonics cause only losses in the motor winding as they do not take part in torque production. Hence, a number of different improved DTC techniques have been developed in the past for multiphase motor drives. The paper takes one such DTC method as the starting point and improves it further by using the concept of virtual voltage vectors. Developed vector selection algorithm, based on two virtual voltage vectors, requires the information on position of the flux in the auxiliary (xy) subspace and provides stator current quality commensurate with the currently available best DTC algorithm for six-phase drives. However, use of two virtual voltage vectors enables a substantial reduction of the torque ripple, which is achieved by means of a five-level torque comparator. Extensive experimentation is performed and it is shown that the reduction of the current harmonics is in essence almost the same as in another recently developed DTC scheme, based on the use of a single virtual voltage vector. However, the achieved torque ripple reduction, which is verified experimentally, makes the scheme superior when compared to the existing approaches. At the same time, developed scheme retains qualities of conventional DTC schemes, such as simple structure and fast response. Its additional beneficial feature is the easiness of implementation. [ABSTRACT FROM PUBLISHER]

This paper presents the circuit design and magnetic integration of push–pull class-E inverters for wireless power transfer (WPT) up to megahertz. The design criterion for achieving zero-voltage switching (ZVS) of a class-E inverter with coupled windings is derived mathematically. The approaches of magnetic integration for push–pull class-E inverters are analyzed and compared. Then, a new magnetic structure with hybrid magnetic materials is proposed to build the integrated inductors with either coupled windings or uncoupled windings. A 3-MHz WPT system is built to verify the analysis. The detailed comparison of the class-E inverters with magnetic integration is presented in terms of switch voltage, efficiency, harmonic currents, and thermal distribution. In the optimized design example, the switches keep ZVS over the entire load range without using any closed-loop control. The system efficiency reaches 87.1% at 350-W output power. [ABSTRACT FROM AUTHOR]

This paper presents a novel approach to derive a pulsewidth modulation (PWM) technique for the generalized multi-phase drive. This novel approach is called a phase traversing principle. The given phase traversing principle is applied to the proposed PWM technique for five-phase open-end winding induction motor drive fed from a single dc source. The proposed PWM technique has the benefits of phase clamping, symmetrical operation of inverters, and common-mode current (CMC) elimination. Thus, it reduces the switching losses and also minimizes the issue of the CMC. The symmetrical operation of dual inverters further helps in the even distribution of losses. Also, the proposed PWM technique gives a good harmonic performance. The performance of the proposed PWM technique is analyzed using the switching loss function and harmonic flux trajectory methods. The first analysis gives justification of the reduced switching losses. While the second analysis gives the deviations in the motor flux with respect to variation in. modulation indices The proposed PWM technique is verified with both simulation and hardware results. [ABSTRACT FROM AUTHOR]

This paper proposes a new pulse amplitude width modulation (PAWM) procedure for cascaded H-bridge multilevel inverters fed by dc voltage sources with unequal amplitudes. With proposed procedure, the generated output voltage is obtained modulating a sinusoidal reference signal at the desired fundamental frequency with equally spaced switching angles. It has been analytically demonstrated that, under these assumptions, all harmonics except those of order $n=2kl\pm 1$ , $k=1,2,\ldots$ are deleted from the output voltage waveform. After a detailed description of the method and a comparative analysis with others existing in the literature, its harmonics elimination capability has been experimentally verified with 5-, 7-, 9-, and 11-level cascaded H-bridge inverters, moreover, it has been mathematically demonstrated that it reduces total harmonic distortion below 5% with a 17-level inverter and it is capable of eliminating the first 49 harmonics considered by standards with a 27-level inverter. [ABSTRACT FROM AUTHOR]

In this paper, a new space vector pulse width modulation method to extend the linear modulation range of a cascaded five level inverter topology with a single dc supply is presented. Using this method, the inverter can be controlled linearly and the peak phase fundamental output voltage of the inverter can be increased from 0.577 to 0.637 V\text{dc} without increasing the dc bus voltage and without exceeding the induction motor voltage rating. This new technique makes use of cascaded inverter pole voltage redundancy and property of the space vector structure for its operation. Using this, the induction motor drive can be operated till the full speed range (0–50 Hz) with the elimination of lower order harmonics in the phase voltage and phase current. The five-level topology presented in this paper is realized by cascading a two-level inverter and two full bridge modules with floating capacitors. The inverter topology and its operation for extending the modulation range is analyzed extensively. Simulation and experimental results for both steady-state and dynamic operating conditions are presented in this paper. [ABSTRACT FROM AUTHOR]

The degradation in power quality causes adverse economical impact on the utilities and customers. Harmonics in current and voltage are one of the most commonly known power quality issues and are solved by the use of a hybrid series active power filter (HSAPF). In this paper, a new controller design using sliding-mode controller-2 is proposed to make the HSAPF more robust and stable. An accurate averaged model of a three-phase HSAPF is also derived in this paper. The design concept of the robust HSAPF has been verified through simulation and experimental studies, and the results obtained are discussed. [ABSTRACT FROM AUTHOR]

This paper presents a method for generating a multilevel dodecagonal voltage space vector structure using a single dc source for induction motor drives. Multilevel dodecagonal structure combines the advantages of both multilevel and dodecagonal structures, and hence, generates low dv/dt phase voltage along with the elimination of fifth- and seventh-order harmonics over the entire modulation range. This eliminates low-order harmonic currents and prevents the generation of sixth-order torque ripple in the motor. The topology used requires only one dc source making four-quadrant operation of the drive system simpler compared to previously proposed multilevel topologies generating dodecagonal space vector structures. The topology used consists of a three-level flying capacitor (FC) inverter cascaded with a capacitor fed H-bridge. The FC inverter operates at a lower switching frequency and the low-order harmonics are eliminated by the switching action of the cascaded H-bridge inverter. The capacitors in the cascaded H-bridge modules are maintained at a substantially smaller voltage compared to the dc-link voltage and are inherently balanced during the pulsewidth modulation operation. This results in low switching loss, in the FC inverter as well as in the cascaded H-bridge inverter. Experimental results are included to validate the operation of the topology and modulation scheme presented in this paper. [ABSTRACT FROM AUTHOR]

In this paper, the near-state pulsewidth modulation (NSPWM), adapted to be implemented in dual-voltage-source inverter (VSI) fed open-end motor, is proposed with the aim of mitigating low-order harmonics (which lead to current total harmonic distortion (THD) minimization). The following two proposed methods are studied in detail: 1) fixing phase angle displacement (PAD) between two VSIs to 120° while adjusting the modulation index (MI); and 2) fixing MI to the predetermined value (wherein low-order harmonics are highly mitigated) while adjusting PAD. Furthermore, the proposed approaches enhance efficiency by limiting the number of commutations within the switching interval. The paper also presents the mathematical approaches to accurately determine low-order harmonic components and switching losses for dual-VSI structure. The experimental setup, including dual-VSI and open-end induction motor, is assembled in the laboratory to evaluate performance of the proposed method. Finally, the simulation results, carried out in the MATLAB/Simulink environment, are found to be in close agreement with experimental data. [ABSTRACT FROM AUTHOR]

The paper proposes a method of active switching harmonics current reduction in the dc-link capacitor of a two-level, three-phase, back-to-back converter. Based on the derived analytical solution for switching harmonic currents in the dc-link, it is shown that by specific control over the pulsewidth-modulated (PWM) carriers’ phase angles, the targeted harmonics of the rectifier and the inverter can be synchronized in phase such that their cancellation occurs in the dc-link capacitor. This synchronization is provided by harmonic phase feedback control. A three-step procedure to implement the method is detailed in the paper. The effectiveness of the proposed approach is verified experimentally. [ABSTRACT FROM AUTHOR]

This paper proposes a new topological configuration for a unified power quality conditioner (UPQC). Generally, the power structure of the three-phase three-wire UPQC consists of two back-to-back connected six-switch inverters. For this configuration, out of 12 switches, six of the series inverter switches will be underutilized most of the time. To improve the semiconductor utilization and consequently to reduce the total switch count, this paper proposes a new reduced switch topology for the UPQC. The proposed topology is realized using only ten switches and retains all the performance merits of the 12-switch UPQC while minimizing its underutilization without increasing the switch VA rating. The paper provides a detailed analytical study and evaluation by comparing the proposed topology with the twelve- and nine-switch-based UPQC system configurations. The feasibility of the proposed topology is validated through experimental investigation. [ABSTRACT FROM AUTHOR]

The leakage current originated from the fluctuations of the common-mode voltage (CMV) is an issue in a transformerless grid-connected photovoltaic system. In this paper, a modified space vector modulation based on the Fourier transform analysis is proposed to reduce the leakage current in a three-phase quasi-Z-source inverter (qZSI). The CMV harmonic content in a qZSI contains low- and high-frequency harmonics that cause safety and electromagnetic interference problems, respectively. By implementing the proposed modulation in a three-phase qZSI, the low-frequency harmonics of the CMV are mainly reduced. The distribution of the high-frequency harmonics is also modified in a way they can be simply filtered. Passive filtering in a qZSI using other modulation techniques is less effective than using this method. Applying the proposed modulation in the presence of a high-frequency inductive-capacitive filter results in the strong suppression of both high- and low-frequency harmonics (more than 90% in the investigated case). A reduced-voltage prototype is designed to evaluate the modulation method. The experimental results from this prototype verify the accuracy of the proposed technique. [ABSTRACT FROM AUTHOR]

This paper proposes a high-frequency dc–dc converter with a synchronous rectifier (SR), which is suitable for the low-voltage output application. The proposed topology consisting of a Class Φ2 inverter and a synchronous Class E current-driven rectifier features low switch voltage stress, fast transient response, and high efficiency. First, the analysis and design method of the converter are presented. Concerning the coupling of amplitude and phase of the fundamental voltage and current in the rectifier stage, the duty cycle of the switch is considered in the proposed design method. For the design of the inverter stage, the impedance of the resonant tank across the main mosfet is utilized in the design process. Second, a self-oscillating resonant driver with dc bias voltage is proposed for the SR switch and features low component count and low driving power loss. A prototype with 12 V input and 5 V/10 W output was built to verify the theoretical analysis. [ABSTRACT FROM AUTHOR]

The three-phase four-wire inverter with split dc-link capacitors can supply unbalanced loads. For the purpose of reducing the filter inductors, a neutral inductor could be introduced into the neutral line. This paper analyzes the operation principle of the three-phase four-wire inverter with split dc-link capacitors when a neutral inductor is introduced. It is illustrated that the neutral inductor can reduce the zero-sequence switching harmonics in the voltages between the phase-leg midpoints and the output neutral point, thus the filter inductors can be reduced. The optimized design of the neutral inductor and filter inductors is proposed with the considerations of the inductor current ripple, the ability of supplying unbalanced loads, and the total energy stored in the inductors. The equivalent circuits of the three-phase four-wire inverter with split dc-link capacitors and neutral inductor is derived in the α–β–0 frame, and the zero-axis voltage regulator is modified to suppress the third-order harmonic in the zero-sequence current caused by the deadtime of the drive signals for the power switches. Finally, the experimental results from a 9-kW prototype are provided to prove the effectiveness of the proposed optimized design of the neutral inductor and filter inductors and the control strategy of the inverter. [ABSTRACT FROM AUTHOR]

In this paper, a modified selective harmonic mitigation pulse amplitude modulation (SHM-PAM) is presented to be capable of canceling all triplen harmonic orders and suitable for single-phase application of five-level type of voltage source inverters. To this end, a new constraint is established for the two switching angles (α1, α2) to derive the new formula for the harmonics’ amplitude, which results in self-elimination of all triplen harmonics (e.g., 3rd, 9th, 15th, …). The fifth and seventh harmonic orders are mitigated through normal operation of the proposed SHM-PAM technique. It is also shown that the proposed technique is extendable to other multilevel voltage waveforms and a flowchart of self-elimination of all triplen harmonics has been presented. Mathematical analysis supported by experimental investigations show the desired performance of the proposed SHM-PAM algorithm on a two-cell single-phase cascaded H-bridge inverter as a typical five-level configuration in dealing with linear and nonlinear loads. Then, it is demonstrated that the maximum number of harmonic orders would be controlled with the minimum number of available angles in a low switching frequency voltage waveform. [ABSTRACT FROM AUTHOR]

In this paper, a novel space vector modulation (SVM) strategy is proposed and designed for dual three-phase three-level motor drives based on vector space decomposition (VSD), which could be applied for high-power and high-reliability applications. The key of the proposed method is to design two decoupled groups of voltage vector candidates for synthesis on α − β subspace and x − y subspace, respectively. The two decoupled groups of voltage vectors will synthesize respective voltage references on α − β subspace and x − y subspace, while having no impact on each other. The redundant small voltage vectors and zero-sequence voltage vectors are utilized to mitigate voltage oscillation in midpoint of dc link and suppress zero-sequence current component for dual three-phase windings with a common neutral. For comparison, another VSD-SVM strategy is designed based on traditional solution, which cannot offer closed-loop control on x − y subspace. Both simulation and experiments have been given to verify that the proposed decoupled VSD-SVM can suppress harmonic components on x − y subspace besides tracking torque components on α − β subspace. Furthermore, the harmonic performance of the proposed decoupled VSD-SVM has been compared with the traditional VSD-SVM strategy and the carrier disposition based pulsewidth modulation. [ABSTRACT FROM AUTHOR]

High-step-up dc/dc converters are widely required in grid-connected applications with renewable energy sources. An extremely high-ratio step-up nonisolated dc/dc converter, in the form of a harmonics-boosted resonant converter, is proposed in this paper. This proposed converter consists of a high-frequency dc/ac inverter stage that is followed by a passive ac/dc rectifier stage connected in cascade. Conventionally, such a dc/ac inverter is designed to output a pure sinusoidal ac voltage with an amplitude several times the amplitude of the input voltage. However, for the proposed converter, the harmonics-boosted inverter stage is designed to contain selected voltage harmonics that significantly boost the amplitude of its output voltage. This greatly increases the overall gain of the converter. The adopted ac/dc stage is a diode-capacitor rectifier, which is of high efficiency and easily extendable to increase the voltage gain. Importantly, the proposed converter involves only one active switch. With only one active switch, the driver's loss is minimized and the converter's control is simplified. Zero-voltage switching is applied to reduce the switching loss, which also allows the converter to operate efficiently at high frequency, and thus can be designed for high power density. The optimal design of the two converter stages and their combined voltage gain is investigated and reported. Besides, a design guideline of the proposed converter is provided. A prototype of a 57-time harmonics-boosted resonant converter with 3.3 V input voltage, 500 kHz switching frequency, and 21 W output power, is built. The experimental result shows that the achieved converter's efficiency is as high as 88.6%. [ABSTRACT FROM AUTHOR]

This paper introduces a new analysis approach to modeling resonant converters that can be used to determine closed-form expressions for the exact resonant network waveforms. This approach, based on superposition of step responses to inverter and rectifier imposed steps, can easily be applied to resonant converters with high-order resonant networks, multiple inverters, and/or rectifiers. The usefulness of the proposed analysis approach is demonstrated first by applying it to a series-resonant converter, wherein it is used to determine accurate closed-form expressions for its tank current in different operating modes. These expressions are utilized to draw insights that help identify the converter's operating mode, and determine associated expressions for its output voltage and the switching frequency required to achieve a desired output power. The proposed approach is also applied to the multi-inverter multi-element impedance control network (ICN) resonant converter, wherein it is used to derive closed-form expressions for the converter's currents. These expressions are utilized to evaluate the behavior and optimize the design of an ICN resonant converter. A prototype 200-W 500-kHz ICN resonant converter optimized using the proposed approach is used to validate the modeling results. It is shown that there is an excellent agreement between the experimental and modeled waveforms during steady-state operation as well as during startup transients. [ABSTRACT FROM AUTHOR]

This paper proposes a new fault-tolerant strategy to revamp performance of three-phase multilevel converters with a single faulty switch. The proposed fault-tolerant strategy is based on the application of a modified selective harmonic elimination (SHE) technique in conjunction with the fundamental phase-shift compensation method. The proposed fault-tolerant strategy makes the most use of the converter capacity in the faulty condition, generates balanced line voltages, and eliminates a wide range of lower order harmonics to limit the total harmonic distribution of the converter voltages in the faulty condition. In this paper, first, a brief background about cascaded H-bridge multilevel converters and SHE technique is provided. Then, the proposed fault-tolerant strategy and the modified SHE technique are presented. Finally, several experimental results are provided to validate the operation of the proposed strategy. [ABSTRACT FROM PUBLISHER]

A virtual space vector modulation technique reducing both magnitude and third-order harmonic component of the common-mode voltage (CMV) in a two-level voltage-source inverter (VSI) is proposed in this paper. The presented method employs a set of virtual space vectors constructed from original stationary space vectors to conduct modulation. Since the created virtual vectors have the lowest instantaneous and zero average CMVs, both the magnitude and third-order harmonic component of the generated CMV are reduced, contributing to better overall CMV performance and common-mode filter design in VSI applications. Three variants of the proposed modulation method using different virtual space vector combinations are presented. The concept of the virtual space vector modulation technique demonstrated with two-level inverter in this paper can also be extended to multilevel inverters. Simulation and experimental results, as well as comparisons with existing methods are provided to verify the proposed technique. [ABSTRACT FROM AUTHOR]

This paper presents a new multilevel selective harmonic elimination pulse-width modulation (MSHE-PWM) technique for transformerless static synchronous compensator (STATCOM) system employing cascaded H-bridge inverter (CHI) configuration. The proposed MSHE-PWM method optimizes both the dc-voltage levels and the switching angles, enabling more harmonics to be eliminated without affecting the structure of the inverter circuit. The method provides constant switching angles and linear pattern of dc-voltage levels over the modulation index range. This in turns eliminates the tedious steps required for manipulating the offline calculated switching angles and therefore, easing the implementation of the MSHE-PWM for dynamic systems. Although the method relies on the availability of the variable dc-voltage levels which can be obtained by various topologies, however, the rapid growth and development in the field of power semiconductor devices led to produce high-efficiency dc-dc converters with a relatively high-voltage capacity and for simplicity, a buck dc-dc converter is considered in this paper. Current and voltage closed loop controllers are implemented for both the STATCOM and the buck converter to meet the reactive power demand at different loading conditions. The technique is further compared with an equivalent conventional carrier-based pulse-width modulation to illustrate its enhanced characteristics. The effectiveness and the theoretical analysis of the proposed approach are verified through both simulation and experimental studies. [ABSTRACT FROM AUTHOR]

Shunt active power filter (SAPF) is the preeminent solution against nonlinear loads, current harmonics, and power quality problems. APF topologies for harmonic compensation use numerous high-power rating components and are therefore disadvantageous. Hybrid topologies combining low-power rating APF with passive filters are used to reduce the power rating of voltage source inverter (VSI). Hybrid APF topologies for high-power rating systems use a transformer with large numbers of passive components. In this paper, a novel four-switch two-leg VSI topology for a three-phase SAPF is proposed for reducing the system cost and size. The proposed topology comprises a two-arm bridge structure, four switches, coupling inductors, and sets of LC PFs. The third leg of the three-phase VSI is removed by eliminating the set of power switching devices, thereby directly connecting the phase with the negative terminals of the dc-link capacitor. The proposed topology enhances the harmonic compensation capability and provides complete reactive power compensation compared with conventional APF topologies. The new experimental prototype is tested in the laboratory to verify the results in terms of total harmonic distortion, balanced supply current, and harmonic compensation, following the IEEE-519 standard. [ABSTRACT FROM AUTHOR]

Microinverters for grid-connected photovoltaic (PV) power conversion systems often require voltage boost due to the low dc voltage of the PV panels. A high-frequency (HF) transformer-isolated differential-mode Ćuk inverter (DMCI) is an attractive topology due to its inherent voltage boost capability and high power density. One of the significant operational issue of the DMCI addressed in this paper is the presence of lower order harmonic distortion in the injected grid current. It is shown that lower order odd and even harmonic voltages are generated with this topology. This problem is accentuated due to the low damping offered by the grid to harmonic voltages. A systematic low-complexity control design is proposed to address this issue. It is shown experimentally that the DMCI operates stably with effective attenuation of the lower order harmonics using the proposed design. Practical operational issues of the DMCI with fast switching GaN field-effect transistor (FET) devices are analyzed and solutions are proposed. It is shown that there can be significant HF noise generation in the DMCI with a frequency range higher than the switching frequency. Practical solutions for resolving HF issues using a combination of circuit layout design and additional passive components are proposed and validated. All of the experimental results are demonstrated on a 500-W GaN-FET-based microinverter prototype. [ABSTRACT FROM PUBLISHER]

In voltage-source inverters, it is necessary to add the dead time between gating signals of the upper and lower switches to prevent short circuit in a phase leg. But in current-source inverters (CSI), due to the large series inductor in dc link, it is necessary to add the overlap time in gating signals of switches during the commutation process for avoiding voltage spikes generated by the intermittent dc current. However, the overlap time will cause negative influence in the output current waveform. In this paper, the current commutation process of CSI within a carrier period is investigated, which shows that the overlap time can cause output-current-vector errors. The output-current-vector errors are then analyzed, which are equivalent to a superposition and introducing additional low-order harmonics in the output current waveform. The relationship between harmonic distortion and the overlap time is derived. An overlap-time compensation method is then proposed, which compensates the dwell time of vectors according to the relations of voltages at the ac side of the inverter. The proposed overlap-time compensation method can effectively decrease the current harmonics introduced by the overlap time and improve the output current of the inverter. Simulation and experimental results are finally provided to verify the feasibility and validity of the proposed method. [ABSTRACT FROM PUBLISHER]

As is well known, the additional low-order harmonic currents and the huge computation amount of the cost function value with all available control sets are the two special issues of finite-control-set model predictive current control (FCS-MPCC) for multiphase inverters. Thus, this paper proposes a FCS-MPCC scheme with duty-ratio optimization for five-phase inverters. First, a group of the reconstructed virtual voltage vectors (V3) with low-order harmonic elimination is defined and employed as the control sets in FCS-MPCC scheme. Thus, it leads to no requirement for harmonic items and weighting factors existing in the cost function. Then, a combination of zero vectors and the selected V3 during each control horizon is adopted to rearrange the pulse sequence, which can realize constant switching frequency. In addition, the durations of the selected V3 and zero vectors during each control horizon are also estimated to minimize the steady-state current ripples in different subspaces based on the cost function optimization. Finally, a comparison of the proposed V3-FCS-MPCC scheme and the other FCS-MPCCs are presented in simulation and experimental test. Simulation and experimental results verify that the proposed V3-FCS-MPCC scheme can remain the simplified structure, fast dynamic performance, constant switching frequency, and achieve minimum current ripples in different subspaces. [ABSTRACT FROM PUBLISHER]

Conventional voltage-source inverters used for induction motor drives generate a hexagonal space vector structure. In the overmodulation range, the hexagonal space vector structure generates low-order harmonics in the phase voltage resulting in low-order torque ripple in the motor. Inverter topologies with an octadecagonal (18 sided) space vector structure eliminate fifth-, seventh-, eleventh-, and thirteenth-order harmonics from the phase voltage, and hence, the dominant sixth- and twelfth-order torque ripple generation is eliminated. Octadecagonal space vector structures proposed in the past require multiple dc sources, which makes four-quadrant operation of the drive system difficult and costly. In this paper, the formation of a multilevel nine-concentric octadecagonal space vector structure using a single dc source is proposed. Detailed experimental results, using open-loop $V/f$ control and rotor field-oriented control, are presented to validate the effectiveness of the proposed drive scheme. [ABSTRACT FROM PUBLISHER]

This paper studies and proposes the vector space decomposition-based direct torque control (DTC) scheme for the T-type neutral-point-clamping (T-NPC) three-level inverters-fed double-stator-winding permanent magnet synchronous machine (PMSM) drive, which provides an effective solution for high-power high-reliability applications. The key is to propose a simple but effective space vector modulation (SVM) for DTC of T-NPC double-stator-winding drives-based two-step voltage vector synthesis, in such a way that good dynamic response and harmonic performance are obtained. The closed-loop controllers on harmonic subspace are incorporated to suppress the possible harmonics induced from back electromotive force and unbalanced parameters in phase windings of electrical machine. Furthermore, a hybrid current control is proposed for fault-tolerant operation of the T-NPC double-stator-winding PMSM drives under one-phase open-circuit conditions. In the hybrid current controller, the healthy winding still uses the SVM-DTC control while the faulty winding uses the closed-loop current controller to track the optimized current references. Both simulation and experimental results are presented to verify the performance of the proposed switching strategies and control schemes. [ABSTRACT FROM AUTHOR]

The injected grid current of the voltage-controlled grid-connected inverter has serious distortion due to the low frequency harmonic components in the output voltage, which is resulted by the dead time of the drive signals of the power switches, and the distortion cannot be eliminated even when an output voltage closed loop is incorporated. This paper introduces a virtual series impedance to increase the output impedance of the grid-connected inverter only at the dominated lower harmonic frequencies; thus, the injected grid current quality can be improved and the dynamic performance of the grid-connected inverter is not deteriorated. Experimental results from a 6-kW single-phase grid-connected inverter confirm the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

The six-step operation of surface-mounted permanent magnet machine drives in a flux weakening region has many advantages compared to the pulse width modulation mode, such as the reduced switching loss and fully utilized inverter output voltage. However, if the ratio of the sampling frequency to the fundamental frequency is low in fixed sampling system, the low-frequency oscillation in the current can be incurred in the six-step operation. The low-frequency current causes a system stability problem and reduces system efficiency due to an excessive heat and high power loss. Therefore, this paper proposes the variable time step controller for six-step operation. By updating an output voltage, sampling phase currents, and executing the digital controller synchronized with the variable sampling time, the turn on and off switch signals for six-step operation can be generated at the exact moment. As a result, the low-frequency oscillation in the phase current can be eliminated. In addition, the system transfer function of the proposed control method is discussed for the system stability and system dynamic analysis. The effectiveness of the proposed method is verified by the comparative simulation and experimental results. [ABSTRACT FROM AUTHOR]

Over recent years, the output power of micro-inverters [module-incorporated inverter (MIC)] is progressively pushed to higher levels, following the current photovoltaic (PV) modules market trends. The interleaved Flyback inverter—under discontinuous conduction mode of operation (DCM)—is an appealing solution for PV applications which are based on MIC technology. This topology provides increased power level for distributed PV generation exploitation with simple control configuration, high efficiency, and reduced filter size. In this paper, the harmonic injection capability is incorporated into the interleaved Flyback inverter for the implementation of an active anti-islanding scheme. A suitable technical solution is proposed that bypasses the unfolding H-bridge, without affecting the active power generation of the inverter and without requiring any hardware modification. In addition, a mathematical model based on the instantaneous power balance theory is presented, being a powerful analysis tool for inverters operating under complete magnetic discharge such as the Flyback inverter (either conventional or interleaved) under DCM or boundary conduction mode of operation. The proposed model predicts accurately the steady-state operational behavior of the Flyback inverter under current harmonic injection, either in grid-tied or islanding operation. The proposed technical implementation method and mathematical model are verified through simulation and experimental results. Finally, an anti-islanding set-up based on the proposed harmonic injection technique is presented and implemented into the Flyback micro-inverter. The proposed set-up is verified through experimental results on various quality factor values, as well as for weak grid conditions. [ABSTRACT FROM AUTHOR]

When employed as a modulator in power inverters, model predictive control has an equivalence to a recently proposed modulation technique known as feedback quantizer modulation (FBQM). Both schemes produce a random-like switching pattern that can facilitate explicit control over the shape of frequency spectra associated with inverter output voltages and currents. This is useful to satisfy electromagnetic interference and acoustic noise requirements, and to avoid excitation of external system resonances. However, it will be shown in this paper that inverter deadtime introduces a disturbance into FBQM that significantly degrades the ability to shape the frequency spectra. Several compensation techniques, designed to model the effect of deadtime inside the formulation of FBQM, are proposed and experimentally verified on a two-level three-phase inverter. [ABSTRACT FROM PUBLISHER]

A new zero-sequence circulating current (ZSCC) reduction method for multimodule voltage source inverters (MVSIs) consisting of P three-phase inverters that are connected in parallel is proposed in this paper. Four-switch inverter modules are used instead of the conventional six-switch modules to reduce the cost. In this paper, the effectiveness of the proposed ZSCC reduction method is studied using selective harmonic elimination pulse width modulation. The proposed ZSCC reduction method can remove about P times the number of harmonics using the same switching frequency as compared to more conventional methods, as explained later in this paper. The concepts discussed in the paper are confirmed with results obtained from an MVSI experimental prototype. [ABSTRACT FROM AUTHOR]

Distributed energy resources (DERs) are expected to provide ancillary functions including reactive power generation and harmonics compensation. Meanwhile, multilevel inverters and two-level converters with optimal pulsewidth modulation (OPWM) will be commonly used for DERs at high power levels. The challenge is to realize harmonic compensation with limited switching angles. This paper presents an online solution to realize the selective harmonics compensation (SHC), and power generation with DERs. For harmonics compensation, the selective harmonic components in the load current are detected. Then, the harmonic voltages are provided with DERs to cancel out these detected components. Since the power converter is requested to realize both harmonics filtering and power generation, limitations on harmonics compensation at the given power are discussed. Power hardware-in-the-loop-based online verifications are shown at the end of the paper. [ABSTRACT FROM AUTHOR]

Multilevel inverters with hexagonal and dodecagonal voltage space vector structures have improved harmonic profile compared to two-level inverters. Further improvement in the quality of the waveform is possible using multilevel octadecagonal (18-sided polygon) voltage space vectors. This paper proposes an inverter circuit topology capable of generating multilevel octadecagonal voltage space vectors, by cascading two asymmetric three-level inverters. By the proper selection of dc-link voltages and the resultant switching states for the inverters, voltage space vectors, whose tips lie on three concentric octadecagons, are obtained. The advantages of octadecagonal voltage space vector-based pulsewidth modulation (PWM) techniques are the complete elimination of fifth, seventh, eleventh, and thirteenth harmonics in phase voltages and the extension of linear modulation range. In this paper, a simple PWM timing calculation method is also proposed. Experimental results have been presented in this paper to validate the proposed concept. [ABSTRACT FROM PUBLISHER]

This paper investigates the suitability of selective harmonic elimination (SHE) for low-loss multimegawatt grid-connected photovoltaic (PV) inverters. The proposed system is able to meet utilities regulations, IEEE and IEC standards. In an attempt to substantiate the potential superiority of SHE over carrier-based or space-vector pulsewidth modulation (PWM), this paper demonstrates that SHE may allow grid-connected PV inverters to be controlled using a switching frequency of less than 1 kHz, while the inverter is still able to provide necessary operation features such as independent control of active and reactive powers and operation control simplicity. For system validation, experimental results with SHE are compared to the case when the inverter is controlled using third-harmonic injection PWM, with a 2-kHz switching frequency. Furthermore, the paper proposes a new implementation technique for SHE that utilizes the third harmonics to spread the switching angles over 90° instead of being located in a narrow range as generated when using conventional techniques, along with increases in modulation index. The advantages of the proposed technique include simplicity in implementation and flexibility in PWM waveforms. Simulation and experimentation demonstrate agreement, which validates the practicability of the proposed system. [ABSTRACT FROM AUTHOR]

This paper addresses the inverter nonlinearity of a three-level T-type inverter. The main causes of the nonlinearity are pulse shaping, pulse skipping due to narrow pulses for the dead time, and voltage drop of the switching devices. Although the same causes have existed in two-level inverters, the pulse skipping phenomenon and results are quite different in the case of the three-level T-type inverter. The effects of pulse shaping and skipping have been investigated and discussed. In addition, the voltage drop of the switching devices has been considered in conjunction with the conduction path of the T-type inverter. Compensation methods based on the pulse width modulation (PWM) of T-type inverter to alleviate the inverter nonlinearity have been proposed from research results. The proposed methods could be easily implemented by adding appropriate offset voltages to the voltage references of the inverter in PWM. Furthermore, a neutral voltage balancing method of a three-level T-type inverter has been proposed in conjunction with the proposed PWM methods using offset voltage. Through extensive experimental tests, the fifth- and seventh-harmonic components of the current are conspicuously reduced along with the even harmonics. The neutral voltage of the inverter can be balanced effectively with the proposed offset voltage adjustments as well. [ABSTRACT FROM AUTHOR]

Large-scale photovoltaic (LSPV) energy conversion systems have been installed at many places across the world. The essential component of the LSPV system is the dc–ac conversion stage. The usage of multilevel converters is one of the recent advances in the dc–ac conversion stage of the LSPV system to enable transformer-less inversion. Current-fed multilevel inverter has been chosen in this paper as it provides high power inversion with inherent voltage boosting, and thus, avoids the usage of transformer. High power conversion necessitates low device switching frequency operation in order to satisfy thermal constraint of semiconductor devices and also to improve efficiency. However, low device switching frequency operation leads to higher harmonic distortion of inverter output currents. Synchronous optimal pulsewidth modulation (SOP) technique is an emerging low device switching frequency modulation technique that has been successfully implemented for voltage-source multilevel inverters. However, the state-of-the-art SOP technique cannot be directly applied to modulate current-source multilevel inverter topologies due to additional constraints on the switching commutations. Therefore, the purpose of our study was to propose a modified SOP technique to achieve: low device switching frequency and minimal harmonic distortion of inverter output currents. The topology of current-fed five-level inverter was used for demonstrating the performance of proposed technique. A generalized conversion method was introduced in the modified SOP technique for including switching constraints of the current-fed inverter. In addition, a state-sequencing machine was developed by utilizing redundant inverter states to produce equal switching commutation among all semiconductor devices at minimal switching frequency of 350 Hz. The experimental results obtained from the five-level current-source inverter of 1.2 kW demonstrated the effectiveness of the proposed SOP technique. [ABSTRACT FROM AUTHOR]

This paper investigates a control method to significantly reduce the low-frequency current oscillation for six-step operation of a three-phase inverter. The six-step operation of an ac electric machine drive system under high speeds has a few advantages compared with pulse width modulation (PWM) operation including reduced switching losses, a better utilization of the dc bus voltage, and an enhanced speed capability. In digital implementation of the six-step control, power electronics may not be able to switch on and off exactly at the zero crossing points of reference voltages, which will result in a dc offset in phase voltages and cause a low-frequency oscillation in phase currents. The low-frequency oscillation will create issues such as higher power losses, lower efficiency, and excessive heat that may demagnetize magnets on the rotor for a permanent magnet synchronous machine. This research presents a control algorithm using asymmetric PWM to ensure that power electronics switch on and off exactly at the reference voltage zero crossing points. Both simulation and experimental results demonstrate the algorithm can reduce the low-frequency oscillation in phase currents by more than 90%. [ABSTRACT FROM AUTHOR]

This paper proposes a novel harmonic suppression scheme for two-level inverter fed three-terminal induction motor drives using switched capacitive filter. Capacitor fed H-bridges used as filters are cascaded to conventional two-level inverter to eliminate fifth- and seventh-order harmonics for the full modulation range including a six-step operation. For the first time, two-level dodecagonal voltage space vector is implemented with single dc supply for three-terminal induction motor drive. Enabling the switched capacitive filtering at low-voltage domain and shifting the high frequency switching to the switched capacitive filter is shown. A uniform pulse width modulation technique is shown which charges and maintains the capacitor voltages while eliminating the fifth- and seventh-order harmonics for the full speed range. [ABSTRACT FROM AUTHOR]

For multilevel converters, as their selective harmonic elimination (SHE) equations are highly related to the switching patterns, it is almost impossible to give a complete study for all the switching patterns under the traditional SHE framework. In this paper, a unified SHE approach is proposed, in which the various SHE equations for different switching patterns are merged into one group of unified SHE equations and the inequality constraints on the switching angles are eliminated at all. This unified SHE equations can be solved by any methods, which have been used in solving the traditional SHE problems. By using the theory of Groebner bases and symmetric polynomials, all the possible switching patterns and the corresponding switching angles can be solved simultaneously. The study on the case for four switching angles discovers some unusual switching patterns that have the lowest total harmonic distortion for low-modulation indices. Also, the case for nine switching angles with modulation index m=\text0.72 is studied; in total, there exist 43 groups of switching angles, which belong to 33 different switching patterns. Experiments on a 13-level cascaded-H bridge converter verify the correctness of this unified multilevel SHE approach. [ABSTRACT FROM PUBLISHER]

This paper presents the design and implementation of a Class EF$_2$ inverter and Class EF$_2$ rectifier for two -W wireless power transfer (WPT) systems, one operating at 6.78 MHz and the other at 27.12 MHz. It will be shown that the Class EF$_2$ circuits can be designed to have beneficial features for WPT applications such as reduced second-harmonic component and lower total harmonic distortion, higher power-output capability, reduction in magnetic core requirements and operation at higher frequencies in rectification compared to other circuit topologies. A model will first be presented to analyze the circuits and to derive values of its components to achieve optimum switching operation. Additional analysis regarding harmonic content, magnetic core requirements and open-circuit protection will also be performed. The design and implementation process of the two Class-EF $_2$-based WPT systems will be discussed and compared to an equivalent Class-E-based WPT system. Experimental results will be provided to confirm validity of the analysis. A dc–dc efficiency of 75% was achieved with Class-EF$_2$-based systems. [ABSTRACT FROM AUTHOR]

Typical algorithms of multidimensional space-vector pulsewidth modulation (SVPWM) divide (n –1) dimensional space into (n–1)/2 subplanes with decoupling matrix or symmetrical component approach. However, the determination of effective sectors and appropriate space voltage vectors takes a heavy computing burden. Taking the five-phase inverter as example, the relationship between the operation time of branch switches and the dwell times of active space vectors in the SVPWM method is analyzed in this paper. Then, the branch space voltage vector (BSVV) corresponding to the individual active branch voltage is defined and the synthesis of other active space voltage vectors using BSVVs is given. Furthermore, only the BSVVs are chosen as the base vectors to synthesize the reference voltage vector, and a novel SVPWM algorithm is present. The operation time of branch switch is deduced, and the equivalence of the normalized load-phase voltages and operation times of branch switches is emphasized and used to analyze the simulation results. The zero-sequence voltage vector is also included in the algorithm as a parameter and its effects on the dwell time of the BSVVs, the modulation index and the common-mode voltage are explicated. Finally, the extension to an n-phase system is discussed. The algorithm eliminates the selection of sectors and proper active space vectors, and can effectively control the dwell time of switches of multiphase inverter. Experimental results proved the feasibility and effectiveness of the algorithm. [ABSTRACT FROM AUTHOR]

The device switching frequency of current source converters (CSCs) in high-power medium-voltage (MV) drive applications is normally around 500 Hz. Conventional space vector modulation (SVM) features fast dynamic response but its output contains low-order harmonics with high magnitudes. In this paper, a natural-sampling-based SVM (NS-SVM) scheme is proposed to substantially suppress the low-order harmonics in practical CSC-based drives. This study proposes an equivalent discretization of NS-SVM wherein natural sampling pulse width modulation performance can be achieved with regular sampling frequency (same as a conventional SVM) instead of a high or even infinite sampling frequency. Equations for natural-sampling-based dwell time calculations for each selected vector are developed. The corresponding simplified but precise enough equations are derived on the basis of the Newton–Raphson algorithm to achieve fast online digital implementation. The proposed NS-SVM features superior low-order harmonic performance and inherits the high dynamic response and low sampling frequency of conventional SVM. Simulations and experiments are provided to verify the proposed NS-SVM scheme. [ABSTRACT FROM AUTHOR]

This paper presents the Bee optimization method for harmonic elimination in a cascaded multilevel inverter. The main objective in selective harmonic elimination pulsewidth modulation strategy is eliminating low-order harmonics by solving nonlinear equations, while the fundamental component is satisfied. In this paper, the Bee algorithm (BA) is applied to a 7-level inverter for solving the equations. The algorithm is based on the food foraging behavior of a swarm of a honeybees and it performs a neighborhood search combined with a random search. This method has higher precision and probability of convergence than the genetic algorithm (GA). MATLAB software is used for optimization and comparison of GA and BA. Simulation results show superiority of BA over GA in attaining accurate global minima and higher convergence rate. Also, its performance in 10 times run is the same as in 1 time run. Finally, for verifying purposes, an experimental study is performed. [ABSTRACT FROM AUTHOR]

The two common three-leg, two-level voltage source inverters of a six-phase drive are able to produce 64 different switching states, representable as voltage space vectors in two orthogonal subspaces. The discrete output voltage of the inverter legs is usually controlled by means of a space vector modulation (SVM) technique, the aim of which is to produce the same volt-seconds as the continuous reference voltage vectors in both subspaces within a certain time frame (switching cycle). Using a simplified phase model of the machine consisting in each subspace of a voltage source and a leakage inductance, the phase currents are found to exhibit unwanted distortion harmonics. A proper sequence of voltage vectors has to be applied in order to reduce these harmonics. By allowing each inverter leg to change its output twice during the switching cycle (continuous modulation), 518400 different space vector sequences can be generated. This paper demonstrates that, among these sequences, only 11 need to be considered to modulate the reference vectors. Further simulation shows that, for a certain pair of reference vectors and leakage inductance ratio, only one of them reduces the distortion to a minimum. Due to the high computational effort, however, this optimization problem is not solvable online. To overcome this drawback, four different modulation strategies, the standard three-phase SVM, the fragmented sector mapping, the optimal interleaved and the approximated interleaved SVM, are derived from and compared with an offline optimization. Each strategy is evaluated regarding the resulting current distortion and the influence of the reference vectors as well as the inductance ratio. The harmonic current of these online modulation strategies is calculated in simulation and validated by experiments. Applying the proposed modulation techniques leads to a great reduction in the machine losses caused by switching. [ABSTRACT FROM AUTHOR]