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This paper proposes a novel discontinuous pulse-width modulation (DPWM) method to reduce the current harmonics and improve the system efficiency for a single-phase three-level neutral-point clamped inverter. In single-phase inverters, the unipolar pulse-width modulation (UP-PWM) method is commonly used. However, this method has the disadvantage of power losses due to numerous switching operations. Conventional DPWM methods reduce the power losses and improve efficiency but increase the current total harmonic distortion (THD). To overcome these weaknesses, this paper proposes a hybrid DPWM switching method combining two PWM methods: the UP-PWM method and the conventional DPWM method called one-pole clamped PWM method. Since the proposed DPWM method offers all the advantages of both PWM methods, the optimal performance—with regard to the power losses and current THD—is obtained. The combination of two PWM methods is investigated by analyzing the power losses and current THD. Based on the analysis, the process determining the optimal operating condition is introduced. The effectiveness of the proposed DPWM method is demonstrated through simulations and experiments. [ABSTRACT FROM AUTHOR]

In this paper, a modified selective harmonic mitigation pulse amplitude modulation (SHM-PAM) is presented to be capable of canceling all triplen harmonic orders and suitable for single-phase application of five-level type of voltage source inverters. To this end, a new constraint is established for the two switching angles (α1, α2) to derive the new formula for the harmonics’ amplitude, which results in self-elimination of all triplen harmonics (e.g., 3rd, 9th, 15th, …). The fifth and seventh harmonic orders are mitigated through normal operation of the proposed SHM-PAM technique. It is also shown that the proposed technique is extendable to other multilevel voltage waveforms and a flowchart of self-elimination of all triplen harmonics has been presented. Mathematical analysis supported by experimental investigations show the desired performance of the proposed SHM-PAM algorithm on a two-cell single-phase cascaded H-bridge inverter as a typical five-level configuration in dealing with linear and nonlinear loads. Then, it is demonstrated that the maximum number of harmonic orders would be controlled with the minimum number of available angles in a low switching frequency voltage waveform. [ABSTRACT FROM AUTHOR]

A new zero-sequence circulating current (ZSCC) reduction method for multimodule voltage source inverters (MVSIs) consisting of P three-phase inverters that are connected in parallel is proposed in this paper. Four-switch inverter modules are used instead of the conventional six-switch modules to reduce the cost. In this paper, the effectiveness of the proposed ZSCC reduction method is studied using selective harmonic elimination pulse width modulation. The proposed ZSCC reduction method can remove about P times the number of harmonics using the same switching frequency as compared to more conventional methods, as explained later in this paper. The concepts discussed in the paper are confirmed with results obtained from an MVSI experimental prototype. [ABSTRACT FROM AUTHOR]

This paper investigates the suitability of selective harmonic elimination (SHE) for low-loss multimegawatt grid-connected photovoltaic (PV) inverters. The proposed system is able to meet utilities regulations, IEEE and IEC standards. In an attempt to substantiate the potential superiority of SHE over carrier-based or space-vector pulsewidth modulation (PWM), this paper demonstrates that SHE may allow grid-connected PV inverters to be controlled using a switching frequency of less than 1 kHz, while the inverter is still able to provide necessary operation features such as independent control of active and reactive powers and operation control simplicity. For system validation, experimental results with SHE are compared to the case when the inverter is controlled using third-harmonic injection PWM, with a 2-kHz switching frequency. Furthermore, the paper proposes a new implementation technique for SHE that utilizes the third harmonics to spread the switching angles over 90° instead of being located in a narrow range as generated when using conventional techniques, along with increases in modulation index. The advantages of the proposed technique include simplicity in implementation and flexibility in PWM waveforms. Simulation and experimentation demonstrate agreement, which validates the practicability of the proposed system. [ABSTRACT FROM AUTHOR]

Large-scale photovoltaic (LSPV) energy conversion systems have been installed at many places across the world. The essential component of the LSPV system is the dc–ac conversion stage. The usage of multilevel converters is one of the recent advances in the dc–ac conversion stage of the LSPV system to enable transformer-less inversion. Current-fed multilevel inverter has been chosen in this paper as it provides high power inversion with inherent voltage boosting, and thus, avoids the usage of transformer. High power conversion necessitates low device switching frequency operation in order to satisfy thermal constraint of semiconductor devices and also to improve efficiency. However, low device switching frequency operation leads to higher harmonic distortion of inverter output currents. Synchronous optimal pulsewidth modulation (SOP) technique is an emerging low device switching frequency modulation technique that has been successfully implemented for voltage-source multilevel inverters. However, the state-of-the-art SOP technique cannot be directly applied to modulate current-source multilevel inverter topologies due to additional constraints on the switching commutations. Therefore, the purpose of our study was to propose a modified SOP technique to achieve: low device switching frequency and minimal harmonic distortion of inverter output currents. The topology of current-fed five-level inverter was used for demonstrating the performance of proposed technique. A generalized conversion method was introduced in the modified SOP technique for including switching constraints of the current-fed inverter. In addition, a state-sequencing machine was developed by utilizing redundant inverter states to produce equal switching commutation among all semiconductor devices at minimal switching frequency of 350 Hz. The experimental results obtained from the five-level current-source inverter of 1.2 kW demonstrated the effectiveness of the proposed SOP technique. [ABSTRACT FROM AUTHOR]

For multilevel converters, as their selective harmonic elimination (SHE) equations are highly related to the switching patterns, it is almost impossible to give a complete study for all the switching patterns under the traditional SHE framework. In this paper, a unified SHE approach is proposed, in which the various SHE equations for different switching patterns are merged into one group of unified SHE equations and the inequality constraints on the switching angles are eliminated at all. This unified SHE equations can be solved by any methods, which have been used in solving the traditional SHE problems. By using the theory of Groebner bases and symmetric polynomials, all the possible switching patterns and the corresponding switching angles can be solved simultaneously. The study on the case for four switching angles discovers some unusual switching patterns that have the lowest total harmonic distortion for low-modulation indices. Also, the case for nine switching angles with modulation index m=\text0.72 is studied; in total, there exist 43 groups of switching angles, which belong to 33 different switching patterns. Experiments on a 13-level cascaded-H bridge converter verify the correctness of this unified multilevel SHE approach. [ABSTRACT FROM PUBLISHER]

This paper presents the design and implementation of a Class EF$_2$ inverter and Class EF$_2$ rectifier for two -W wireless power transfer (WPT) systems, one operating at 6.78 MHz and the other at 27.12 MHz. It will be shown that the Class EF$_2$ circuits can be designed to have beneficial features for WPT applications such as reduced second-harmonic component and lower total harmonic distortion, higher power-output capability, reduction in magnetic core requirements and operation at higher frequencies in rectification compared to other circuit topologies. A model will first be presented to analyze the circuits and to derive values of its components to achieve optimum switching operation. Additional analysis regarding harmonic content, magnetic core requirements and open-circuit protection will also be performed. The design and implementation process of the two Class-EF $_2$-based WPT systems will be discussed and compared to an equivalent Class-E-based WPT system. Experimental results will be provided to confirm validity of the analysis. A dc–dc efficiency of 75% was achieved with Class-EF$_2$-based systems. [ABSTRACT FROM AUTHOR]

The device switching frequency of current source converters (CSCs) in high-power medium-voltage (MV) drive applications is normally around 500 Hz. Conventional space vector modulation (SVM) features fast dynamic response but its output contains low-order harmonics with high magnitudes. In this paper, a natural-sampling-based SVM (NS-SVM) scheme is proposed to substantially suppress the low-order harmonics in practical CSC-based drives. This study proposes an equivalent discretization of NS-SVM wherein natural sampling pulse width modulation performance can be achieved with regular sampling frequency (same as a conventional SVM) instead of a high or even infinite sampling frequency. Equations for natural-sampling-based dwell time calculations for each selected vector are developed. The corresponding simplified but precise enough equations are derived on the basis of the Newton–Raphson algorithm to achieve fast online digital implementation. The proposed NS-SVM features superior low-order harmonic performance and inherits the high dynamic response and low sampling frequency of conventional SVM. Simulations and experiments are provided to verify the proposed NS-SVM scheme. [ABSTRACT FROM AUTHOR]

In this paper, three control schemes with variable switching frequencies are proposed and analyzed for the paralleled voltage source inverters (VSIs) fed permanent magnet synchronous motor (PMSM) drive. The proposed schemes could be applied in the low-speed operation region of high-power drive system, where the frequency modulation index is high. First, the field-oriented control (FOC) with phase-shifted chaotic space vector modulation (SVM) under synchronous frame and the FOC with phase-shifted chaotic sinusoidal pulse width modulation under stationary frame is proposed for the paralleled VSIs fed PMSM drive. The proposed phase-shifted chaotic PWM schemes not only eliminate specific switching harmonics completely but also suppress all remaining switching harmonic peaks in the spectrum. The avoidance of inherent circulating current is also considered in designing these two schemes. Second, the direct torque control (DTC) for the paralleled VSIs fed PMSM drive is proposed with circulating current suppression. Besides inheriting the advantages of DTC, the output currents of paralleled VSIs are kept balanced. The working principles of these three methods are presented in detail. Experimental results on a laboratory prototype are given to verify the validity of the three proposed control schemes for the paralleled VSIs fed PMSM with variable switching frequencies. [ABSTRACT FROM PUBLISHER]

The analysis and assessment of the pulsewidth modulation (PWM) techniques is commonly based on the comparison of the total harmonic distortion (THD) results. THD is usually calculated by application of the Fourier transformation and by taking a limited number of harmonics into the consideration. In this paper, derivation of analytical formulas for the phase voltage THD is presented. The considered system is a symmetrical multiphase star-connected load, supplied from a multilevel pulsewidth-modulated voltage-source inverter (VSI, three-phase case is also covered). The solution is based on the Parseval's theorem, which links frequency spectrum and time domain through the average power (i.e., root-mean-square (rms) squared value) of the signal. The assumption throughout the derivations is that the ratio of the switching to fundamental frequency is high. Derivations are based on the integration of the power of the PWM signal in a single switching period over the fundamental period of the signal. Only ideal sinusoidal reference voltages are analyzed, and no injection of any type is considered. Formulas for phase voltage THD for any number of phases are derived for two- and three-level cases, for the most commonly used carrier-based methods. Comparison of the analytically obtained curves with simulation and experimental results shows a high level of agreement and validates the analysis and derivations. [ABSTRACT FROM AUTHOR]

Sliding mode control (SMC) is recognized as robust controller with a high stability in a wide range of operating conditions, although it suffers from chattering problem. In addition, it cannot be directly applied to multiswitches power converters. In this paper, a high performance and fixed switching frequency sliding mode controller is proposed for a single-phase unipolar inverter. The chattering problem of SMC is eliminated by smoothing the control law in a narrow boundary layer, and a pulsewidth modulator produces the fixed frequency switching law for the inverter. The smoothing procedure is based on limitation of pulsewidth modulator. Although the smoothed control law limits the performance of SMC, regulation and dynamic response of the inverter output voltage are in an acceptable superior range. The performance of the proposed controller is verified by both simulation and experiments on a prototype 6-kVA inverter. The experimental results show that the total harmonic distortion of the output voltage is less than 1.1% and 1.7% at maximum linear and nonlinear load, respectively. Furthermore, the output dynamic performance of the inverter strictly conforms the standard IEC62040-3. Moreover, the measured efficiency of the inverter in the worst condition is better than 95.5%. [ABSTRACT FROM AUTHOR]

Bitstream-based control, which uses one-bit-wide signals to control power electronics applications, is a new approach for controller design. Bit-Stream signals can be directly applied to control electronic devices, but the high-frequency nature of bitstream signals can lead to excessive switching losses. Thus, it is essential to downsample bitstream signals to reduce switching losses to acceptable levels. This paper presents a novel modulator, which downsamples high-frequency bitstreams to low-frequency switching signals that are suitable for driving two-level half-bridge or three-level full-bridge inverters. Methods for compensating for switch dead time and balancing switching losses of the inverter legs are presented, and the performance of the proposed modulators are compared to the standard pulse width modulation strategies. Simulation and experimental results of a 2-kW single-phase inverter show that the proposed bitstream modulators consume fewer logic resources, produce spread-spectrum output currents, and can deliver lower total harmonic distortion than similar fixed-frequency pulse width modulators. [ABSTRACT FROM AUTHOR]