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DC–DC converters with voltage boost capability are widely used in a large number of power conversion applications, from fraction-of-volt to tens of thousands of volts at power levels from milliwatts to megawatts. The literature has reported on various voltage-boosting techniques, in which fundamental energy storing elements (inductors and capacitors) and/or transformers in conjunction with switch(es) and diode(s) are utilized in the circuit. These techniques include switched capacitor (charge pump), voltage multiplier, switched inductor/voltage lift, magnetic coupling, and multistage/-level, and each has its own merits and demerits depending on application, in terms of cost, complexity, power density, reliability, and efficiency. To meet the growing demand for such applications, new power converter topologies that use the above voltage-boosting techniques, as well as some active and passive components, are continuously being proposed. The permutations and combinations of the various voltage-boosting techniques with additional components in a circuit allow for numerous new topologies and configurations, which are often confusing and difficult to follow. Therefore, to present a clear picture on the general law and framework of the development of next-generation step-up dc–dc converters, this paper aims to comprehensively review and classify various step-up dc–dc converters based on their characteristics and voltage-boosting techniques. In addition, the advantages and disadvantages of these voltage-boosting techniques and associated converters are discussed in detail. Finally, broad applications of dc–dc converters are presented and summarized with comparative study of different voltage-boosting techniques. [ABSTRACT FROM AUTHOR]

Due to exponential (Moores law) scaling of advanced CMOS technologies, the challenges associated with delivering power to performance and mobile computing systems are outpacing the capabilities of conventional voltage regulator (VR) topologies. To continue to scale throughput at constant power density, the level of parallelism in microprocessor architectures is expected to increase substantially. In this paper, we present a power conversion topology to provide independent multicore regulation in the 0.8–1.4 V range from a 12-V dc bus. The topology uses a multistage ladder converter to manage power delivery to digital circuits stacked in vertical voltage domains. This approach has several advantages with regard to systems efficiency as it allows a more moderate conversion ratio of the main dc–dc converter. Moreover, the parallel converter only needs to process a fraction of the power of each core as the current can be “recycled” by adjacent cores in the stack. We develop a dynamical model for a multiple-input, multiple-output control scheme that uses a simple integral-control law, augmented with fast voltage- and current-mode feedforward. Measurement results of a discrete prototype verify the control scheme and demonstrate the potential advantages in system efficiency but also emphasize the remaining challenges in meeting stringent VR dynamic response requirements. [ABSTRACT FROM PUBLISHER]

This paper presents an interleaved boost converter (IBC) with ripple cancellation network (RCN). Based on the conventional IBC, two capacitors, two coupled inductors, and two inductors are added as RCN in the proposed converter. Therefore, the proposed converter shares the same advantages of the conventional IBC and achieves input current ripple cancellation without significantly increasing the current stress and loss of the converter. Finally, a 36-V input voltage, 50-V output voltage, and 1-kW output power prototype circuit operating at 100 kHz is implemented in the laboratory to verify the expected performance. The proposed converter can achieve input current ripple cancellation in all power range with the efficiency higher than 96%. The simulation and experimental results show that the proposed IBC with RCN has great potential to be applied in high-power, high-efficiency dc/dc conversion. [ABSTRACT FROM AUTHOR]