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The traditional neutral point clamped (NPC) inverter has short-circuit problem. The risk of short-circuit can be decreased by using dead-time in the switching signals. However, the dead-time decreases the achievable output voltage and causes distortion in the waveforms. To overcome the short-circuit problem, dual-buck NPC (DB-NPC) and split-inductor NPC (SI-NPC) inverters have been researched. However, the voltage stress of the two external diodes in the DB-NPC inverter is higher. On the other hand, the SI-NPC inverter has a problem of generating huge voltage spikes in the dead-time, which can destroy the semiconductor devices. In addition, the SI-NPC inverter cannot provide reactive power. This article presents a family of NPC inverters consisting of single-phase, three-phase, and cascaded inverters. The proposed inverters have no short-circuit and dead-time issues, therefore no high voltage and current spikes are caused. Also, the dead-time in the switching signals can be minimized. As a result, the magnitude of the output waveforms can be increased, and quality can be improved. Unlike the DB-NPC inverter, the voltage stress of all the semiconductor in the proposed inverter is lower, and unlike the SI-NPC inverter the proposed inverter provides reactive power. In this article, the proposed three-level NPC inverter is analyzed, designed, and tested. The voltage stress of the semiconductor devices in the proposed inverter is half of the source voltage, whereas in the conventional DB-NPC inverter the voltage stress of the two external diodes is the source voltage. In addition to the aforementioned benefits, the proposed cascaded inverter reduces the total number of inductors. To verify the analysis, detailed simulation, and experimental results of the proposed three-level inverter with input voltage 640 V, output power 1.2 kW, and output voltage 220 Vrms are provided. [ABSTRACT FROM AUTHOR]

Nine-Switch inverter (NSI) has been recently introduced for independent control of dual ac motors. Although this topology reduces the number of active switches by 25% compared to conventional inverters, it has a main conceptual shortcoming due to voltage gain limitations. In NSI, the voltage gains of both outputs are relatively low, while their maximum achievable magnitudes depend on the phase angle between the two sets. In order to mitigate this problem, this article introduces a new dual output nine-switch boost inverter (NSBI) topology with a minimum number of passive elements. The detailed analysis of NSBI is presented, while the required modifications to conventional pulsewidth modulation (PWM) strategies of the NSI are explained to ensure an acceptable voltage boosting ratio while a high-quality voltage output is obtained. Among different PWM schemes, a modified discontinuous PWM scheme is found optimum with this proposed topology to minimize the voltage stress across switches and improve the input current and output voltage quality. The proposed topology is also validated under both common-frequency and different-frequency modes of operations. Moreover, a clear picture of the NSBI performance compared with other possible counterparts is introduced. The theoretical findings have been corroborated using simulation and experiments. [ABSTRACT FROM AUTHOR]

This paper presents a dual modular multilevel converter (MMC) topology that utilizes energy exchange between adjacent-arm submodules (SMs), operating with out-of-phase modulation. The proposed configuration is applicable to medium-voltage high-power variable-speed drives incorporating open-end stator winding machines. A novel concept of power decoupling between adjacent-arm SMs in the dual MMC topology is realized through high-frequency transformer-based dc–dc converter modules. This concept offers a significant reduction in the sizing requirement of the SM capacitance and the stored energy in the MMC system, while avoiding the problem of wide voltage fluctuations of SM capacitors, especially at low operating frequencies. The proposed configuration can produce dc voltage; therefore, a machine speed range from zero speed to the rated speed is possible under the rated torque operating condition. The operating principles of the proposed dual MMC configuration are elaborated and necessary mathematical analysis is derived. Simulation and experimental results verify the concept of the proposed drive configuration. [ABSTRACT FROM AUTHOR]

Differential-mode buck-boost inverters have merits such as reduced switch number, ability to provide voltages higher or lower than the input voltage magnitude, improved efficiency, reduced cost and size, and increased power density, especially in low-power applications. There are five buck-boost inverters that can provide flexible output voltage without the need of a large electrolytic input side capacitor, which degrades the reliability of inverters. The continuous input current of these inverters is appropriate for maximum power point tracking operation in photovoltaic and fuel cells applications. Three of the five inverters can be isolated with high-frequency-link transformers where the common-mode leakage current can be mitigated. However, the performance and control of such converters have not been discussed in detail. In this paper, the five possible single-stage three-phase differential-mode buck-boost inverters with continuous input current are investigated and compared in terms of total losses, maximum ripple current, total harmonic distortion, and device and passive element ratings. In addition, the possible methods are presented for eliminating the input third-order harmonic current, resulting from the stored energy in the passive elements, as well as the output second-order harmonic currents. The ability for isolating the input and output sides of the inverters with a small–high frequency transformers is discussed. A changeable-terminal 2.5-kW bidirectional inverter is used to validate the design flexibility of the inverter topologies, when digital signal processor-controlled. [ABSTRACT FROM AUTHOR]

The four-switch three-phase (FSTP) inverter has been proposed as an innovative inverter design to reduce the cost, complexity, size, and switching losses of the dc–ac conversion system. Traditional FSTP inverter usually operates at half the dc input voltage; hence, the output line voltage cannot exceed this value. This paper proposes a novel design for the FSTP inverter based on the topology of the single-ended primary-inductance converter (SEPIC). The proposed topology provides pure sinusoidal output voltages with no need for output filter. Compared to traditional FSTP inverter, the proposed FSTP SEPIC inverter improves the voltage utilization factor of the input dc supply, where the proposed topology provides higher output line voltage which can be extended up to the full value of the dc input voltage. The integral sliding-mode control is used with the proposed topology to optimize its dynamics and to ensure robustness of the system during different operating conditions. Derivation of the equations describing the parameters design, components ratings, and the operation of the proposed SEPIC inverter is presented in this paper. Simulation model and experimental setup are used to validate the proposed concept. Simulations and experimental results show the effectiveness of the proposed inverter. [ABSTRACT FROM AUTHOR]

A multilevel topology with medium-frequency ac link for medium-voltage grid integration of utility photovoltaic (PV) plants is discussed in this paper. A megawatt-scale PV plant is divided into many zones, each comprising of two series-connected arrays. Each zone employs a medium-frequency transformer with three secondaries, which interface with the three phases of the medium voltage grid. An insulated-gate bipolar transistor full-bridge inverter feeds the MF transformer. The voltages at the transformer secondaries are then converted to three-phase line frequency ac by three full-bridge ac-ac converters. Second line frequency harmonic power does not appear in the dc bus, thereby reducing the dc capacitor size. Cascading several such cells, a high-quality multilevel medium-voltage output is generated. A new control method is proposed for the cascaded multilevel converter during partial shading while minimizing the switch ratings. The proposed topology eliminates the need for line frequency transformer isolation and reduces the dc bus capacitor size, while improving the power factor and energy yield. This paper presents the analysis, design example, and operation of a 10-MW utility PV system with experimental results on a scaled-down laboratory prototype. [ABSTRACT FROM AUTHOR]