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The traditional neutral point clamped (NPC) inverter has short-circuit problem. The risk of short-circuit can be decreased by using dead-time in the switching signals. However, the dead-time decreases the achievable output voltage and causes distortion in the waveforms. To overcome the short-circuit problem, dual-buck NPC (DB-NPC) and split-inductor NPC (SI-NPC) inverters have been researched. However, the voltage stress of the two external diodes in the DB-NPC inverter is higher. On the other hand, the SI-NPC inverter has a problem of generating huge voltage spikes in the dead-time, which can destroy the semiconductor devices. In addition, the SI-NPC inverter cannot provide reactive power. This article presents a family of NPC inverters consisting of single-phase, three-phase, and cascaded inverters. The proposed inverters have no short-circuit and dead-time issues, therefore no high voltage and current spikes are caused. Also, the dead-time in the switching signals can be minimized. As a result, the magnitude of the output waveforms can be increased, and quality can be improved. Unlike the DB-NPC inverter, the voltage stress of all the semiconductor in the proposed inverter is lower, and unlike the SI-NPC inverter the proposed inverter provides reactive power. In this article, the proposed three-level NPC inverter is analyzed, designed, and tested. The voltage stress of the semiconductor devices in the proposed inverter is half of the source voltage, whereas in the conventional DB-NPC inverter the voltage stress of the two external diodes is the source voltage. In addition to the aforementioned benefits, the proposed cascaded inverter reduces the total number of inductors. To verify the analysis, detailed simulation, and experimental results of the proposed three-level inverter with input voltage 640 V, output power 1.2 kW, and output voltage 220 Vrms are provided. [ABSTRACT FROM AUTHOR]

Nine-Switch inverter (NSI) has been recently introduced for independent control of dual ac motors. Although this topology reduces the number of active switches by 25% compared to conventional inverters, it has a main conceptual shortcoming due to voltage gain limitations. In NSI, the voltage gains of both outputs are relatively low, while their maximum achievable magnitudes depend on the phase angle between the two sets. In order to mitigate this problem, this article introduces a new dual output nine-switch boost inverter (NSBI) topology with a minimum number of passive elements. The detailed analysis of NSBI is presented, while the required modifications to conventional pulsewidth modulation (PWM) strategies of the NSI are explained to ensure an acceptable voltage boosting ratio while a high-quality voltage output is obtained. Among different PWM schemes, a modified discontinuous PWM scheme is found optimum with this proposed topology to minimize the voltage stress across switches and improve the input current and output voltage quality. The proposed topology is also validated under both common-frequency and different-frequency modes of operations. Moreover, a clear picture of the NSBI performance compared with other possible counterparts is introduced. The theoretical findings have been corroborated using simulation and experiments. [ABSTRACT FROM AUTHOR]

This paper presents a dual modular multilevel converter (MMC) topology that utilizes energy exchange between adjacent-arm submodules (SMs), operating with out-of-phase modulation. The proposed configuration is applicable to medium-voltage high-power variable-speed drives incorporating open-end stator winding machines. A novel concept of power decoupling between adjacent-arm SMs in the dual MMC topology is realized through high-frequency transformer-based dc–dc converter modules. This concept offers a significant reduction in the sizing requirement of the SM capacitance and the stored energy in the MMC system, while avoiding the problem of wide voltage fluctuations of SM capacitors, especially at low operating frequencies. The proposed configuration can produce dc voltage; therefore, a machine speed range from zero speed to the rated speed is possible under the rated torque operating condition. The operating principles of the proposed dual MMC configuration are elaborated and necessary mathematical analysis is derived. Simulation and experimental results verify the concept of the proposed drive configuration. [ABSTRACT FROM AUTHOR]

High-voltage (HV) pulses are used in electroporation to subject pulsed electric field (PEF) onto a sample under treatment. Pulse-waveform shape, voltage magnitude, pulse duration, and pulse repetition rate are the basic controllable variables required for particular PEF application. In practice, a custom-made pulse generator is dedicated for each PEF application with limited flexibility in changing these variables. In this paper, a universal pulse-waveform generator (UPG) is proposed, where the controller software algorithm can manipulate a basic generated multilevel pulse waveform to emulate many different PEF pulse waveforms. The commonly used PEF HV pulse waveforms can be generated as bipolar or monopolar with controllable pulse durations, repetition times, and voltage magnitudes. The UPG has the ability to generate multilevel pulses that have controllable $dv/dt$, which allows reduction of the electromagnetic interference generated by the converter. The UPG topology is based on half-bridge modular multilevel converter (HB-MMC) cells forming two transition arms in conjunction with two bistate arms, together creating an H-bridge. The HB-MMC cell capacitors provide a controllable energy source which charge from the dc input supply and discharge across the load, while the two bistate arms allow charging the HB-MMC cell capacitors. Hence, the UPG topology offers modularity, redundancy, and scalability. The HB-MMC individual cell capacitance is low and the cell voltages are balanced by employing the sorting and rotating algorithm used in conventional HB-MMC topologies for HV dc transmission applications. The viability of the proposed UPG converter is validated by MATLAB/Simulink simulation and scaled-down experimentation. [ABSTRACT FROM PUBLISHER]

Differential-mode buck-boost inverters have merits such as reduced switch number, ability to provide voltages higher or lower than the input voltage magnitude, improved efficiency, reduced cost and size, and increased power density, especially in low-power applications. There are five buck-boost inverters that can provide flexible output voltage without the need of a large electrolytic input side capacitor, which degrades the reliability of inverters. The continuous input current of these inverters is appropriate for maximum power point tracking operation in photovoltaic and fuel cells applications. Three of the five inverters can be isolated with high-frequency-link transformers where the common-mode leakage current can be mitigated. However, the performance and control of such converters have not been discussed in detail. In this paper, the five possible single-stage three-phase differential-mode buck-boost inverters with continuous input current are investigated and compared in terms of total losses, maximum ripple current, total harmonic distortion, and device and passive element ratings. In addition, the possible methods are presented for eliminating the input third-order harmonic current, resulting from the stored energy in the passive elements, as well as the output second-order harmonic currents. The ability for isolating the input and output sides of the inverters with a small–high frequency transformers is discussed. A changeable-terminal 2.5-kW bidirectional inverter is used to validate the design flexibility of the inverter topologies, when digital signal processor-controlled. [ABSTRACT FROM AUTHOR]

Conventional dual-active bridge topologies provide galvanic isolation and soft-switching over a reasonable operating range without dedicated resonant circuits. However, scaling the two-level dual-active bridge to higher dc voltage levels is impeded by several challenges among which the high dv/dt stress on the coupling transformer insulation. Gating and thermal characteristics of series switch arrays add to the limitations. To avoid the use of standard bulky modular multilevel bridges, this paper analyzes an alternative modulation technique, where staircase approximated trapezoidal voltage waveforms are produced; thus, alleviating developed dv/dt stresses. Modular design is realized by the utilization of half-bridge chopper cells. This way the analyzed dc-dc transformer employs modular multilevel converters operated in a new mode with minimal common-mode arm currents, as well as reduced capacitor size, hence reduced cell footprint. Suitable switching patterns are developed and various design and operation aspects are studied. Soft-switching characteristics will be shown to be comparable to those of the two-level dual-active bridge. Experimental results from a scaled test rig validate the presented concept. [ABSTRACT FROM AUTHOR]

The four-switch three-phase (FSTP) inverter has been proposed as an innovative inverter design to reduce the cost, complexity, size, and switching losses of the dc–ac conversion system. Traditional FSTP inverter usually operates at half the dc input voltage; hence, the output line voltage cannot exceed this value. This paper proposes a novel design for the FSTP inverter based on the topology of the single-ended primary-inductance converter (SEPIC). The proposed topology provides pure sinusoidal output voltages with no need for output filter. Compared to traditional FSTP inverter, the proposed FSTP SEPIC inverter improves the voltage utilization factor of the input dc supply, where the proposed topology provides higher output line voltage which can be extended up to the full value of the dc input voltage. The integral sliding-mode control is used with the proposed topology to optimize its dynamics and to ensure robustness of the system during different operating conditions. Derivation of the equations describing the parameters design, components ratings, and the operation of the proposed SEPIC inverter is presented in this paper. Simulation model and experimental setup are used to validate the proposed concept. Simulations and experimental results show the effectiveness of the proposed inverter. [ABSTRACT FROM AUTHOR]

An interline dynamic voltage restorer (IDVR) is invariably employed in distribution systems to mitigate voltage sag/swell problems. An IDVR merely consists of several dynamic voltage restorers (DVRs) sharing a common dc link connecting independent feeders to secure electric power to critical loads. While one of the DVRs compensates for the local voltage sag in its feeder, the other DVRs replenish the common dc-link voltage. For normal voltage levels, the DVRs should be bypassed. Instead of bypassing the DVRs in normal conditions, this paper proposes operating the DVRs, if needed, to improve the displacement factor (DF) of one of the involved feeders. DF improvement can be achieved via active and reactive power exchange (PQ sharing) between different feeders. To successfully apply this concept, several constraints are addressed throughout the paper. Simulation and experimental results elucidate and substantiate the proposed concept. [ABSTRACT FROM AUTHOR]