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This paper presents a unified framework for the modeling, analysis, and design of load-independent Class E and Class EF inverters and rectifiers. These circuits are able to maintain zero-voltage switching and, hence, high efficiency for a wide load range without requiring tuning or use of a feedback loop, and to simultaneously achieve a constant amplitude ac voltage or current in inversion and a constant dc output voltage or current in rectification. As switching frequencies are gradually stepping into the megahertz (MHz) region with the use of wide-bandgap (WBG) devices such as GaN and SiC, switching loss, implementing fast control loops, and current sensing become a challenge, which load-independent operation is able to address, thus allowing exploitation of the high-frequency capability of WBG devices. The traditional Class E and EF topologies are first presented, and the conditions for load-independent operation are derived mathematically; then, a thorough analytical characterization of the circuit performance is carried out in terms of voltage and current stresses and the power-output capability. From this, design contours and tables are presented to enable the rapid implementation of these converters given particular power and load requirements. Three different design examples are used to showcase the capability of these converters in typical MHz power conversion applications using the design equations and methods presented in this paper. The design examples are chosen toward enabling efficient and high-power-density MHz converters for wireless power transfer (WPT) applications and dc/dc conversion. Specifically, a 150-W 13.56-MHz Class EF inverter for WPT, a 150-W 10-MHz miniature Class E boost converter, and a lightweight wirelessly powered drone using a 20-W 13.56-MHz Class E synchronous rectifier have been designed and are presented here. [ABSTRACT FROM AUTHOR]

In this paper, direct torque control (DTC) of five-phase induction motor (FPIM) is implemented using three-level neutral point clamped (TL-NPC) inverter. One of the advantages of three-level inverter over two-level one for DTC operation is the low torque ripple. Also TL-NPC inverter through space vector modulation technique gives low $ dv/dt$ transition with better voltage waveform. By applying conventional lookup table for DTC, the TL-NPC inverter does not ensures lower $dv/dt$ transition. In this paper, a novel switching scheme for DTC of FPIM using TL-NPC inverter is proposed that ensures the low $ dv/dt$ transition and balancing of dc-link capacitor voltages of TL-NPC inverter. To form the lookup table for DTC operation, instead of using voltage vectors directly, virtual vectors (VVs) are utilized. Two switching states are used in one sample time to generate a VV in $\alpha \beta$ plane, which gives zero resultant voltage in $ xy$ plane. The switching strategy ensures low number of transitions to reduce the switching losses. The switching state redundancies are used in a novel way to balance the dc-link capacitor voltages without using any additional hardware. The proposed technique to balance the dc-link capacitor voltage gives lower switching frequency. The MATLAB/Simulink environment is used for the simulation and the results are validated through experiments. [ABSTRACT FROM AUTHOR]

A 1-φ hybrid nine-level inverter (H9LI) topology has been proposed in this paper. The proposed H9LI topology uses a simple phase disposition pulsewidth modulation strategy to generate nine-voltage levels in the output. The main advantage of this topology is that it has a low switch count (ten switches) compared to the existing nine-level inverter topologies. To regulate the voltage across auxiliary capacitor, two innovative control techniques are proposed, which are integrated with the inverter modulation technique itself. Hence, it does not require any extra voltage balancing circuits to maintain the voltage across the auxiliary capacitor and input dc capacitors. A major advantage of these control techniques is that they eliminate the sensing of the coupled inductor current. Another significant advantage of H9LI is that loss distribution among all the power switches is more uniform compared to existing nine-level inverters. Due to low part count and absence of extra voltage balancing circuits, the H9LI achieves higher efficiency (η ≍ 94.5%) and lower cost. Furthermore, the requirement of filter size reduces due to the presence of coupled inductor in H9LI. The proposed 1-φ grid connected H9LI is verified through MATLAB/Simulink simulations and validated through experiments on a laboratory prototype of 400-VA rating. [ABSTRACT FROM AUTHOR]

In this paper, a new control strategy for improving weighted efficiency in photovoltaic (PV) ac module-type interleaved flyback inverters (ILFIs) is proposed. The efficiency of the ILFI for PV ac modules has to be high, not only for the maximum power, but also for other power levels according to weather conditions. For PV power conversion efficiency improvement in all load ranges, a new control method for an ILFI according to the output of the PV module is proposed in this paper. The proposed method controls an active clamp circuit and each converter phase of an ILFI according to the output power of the PV module. Thus, the efficiency of an ILFI as a PV power conditioner can be improved in all power range of the PV module. Theoretical analysis, simulation, and experiment are performed in order to verify the proposed control method. [ABSTRACT FROM AUTHOR]

Diode-assisted buck–boost voltage-source inverter achieves high voltage gain by introducing a switch-capacitor based high step-up dc–dc circuit between the dc source and inverter bridge. As for the unique structure, various pulse width modulation (PWM) strategies are developed with regard to the chopped intermediate dc-link voltage. In order to maximize voltage gain and increase efficiency, this paper proposes a novel PWM strategy. It regulates the average value of intermediate dc-link voltage in one switching time period ( Ts) the same as the instantaneous maximum value of three-phase line voltage by controlling the front boost circuit. Then, the equivalent switching frequency of power devices in the inverter bridge can be reduced to 1/3fs (fs = 1/Ts). The operating principle and closed-loop controller design are analyzed and verified by simulations and experiments. Compared with existing PWM strategies, the new control strategy demonstrates less power device requirement and higher efficiency in high voltage gain applications. It is a more competitive topology for wide range dc/ac voltage regulation in renewable energy applications. Furthermore, with new control strategy, the dc-side inductor current and capacitor voltage contains six-time line-frequency ripples. To overcome the undesired influence of low frequency ripples, it is also suitable for 400–800 Hz medium frequency aircraft and vessel power supply system. [ABSTRACT FROM PUBLISHER]

This paper presents a generalized algorithm to eliminate spikes of common-mode voltages (CMV) caused by dead-time effect for common-mode voltage reduction pulse width modulation (CMVRPWM). The characteristics of the CMV spikes for the popular CMVRPWM strategies (AZSPWM1, NSPWM, CRLO-CMVRPWM, and SLO-CMVRPWM) are studied and compared by analyzing the extreme switch pulse patterns. The proposed CMV spikes elimination method directly adjusts the injected zero-sequence voltages instead of the durations of the adopted voltage space vectors to avoid the overlaps of the adjacent dead time periods. The CMV spikes can be eliminated regardless of the output voltages in the dead time periods; thus, the signs of phase currents are not needed to detect and overcome the problem caused by the resolution of the current sensors when the phase currents approach to zero. In addition, an effective method by online selecting low or high active pulses for the three legs is proposed to ensure that at most one leg switches between adjacent carrier periods. The proposed method is generalized and effective for all the CMVRPWM with symmetrical switch pulse patterns and no simultaneous switching problem. The simulation and experimental results validate the effectiveness. [ABSTRACT FROM AUTHOR]

In this paper, a new cascaded nonlinear controller has been designed and implemented on the packed U-cell (PUC) seven-level inverter. The proposed controller has been designed based on a simplified model of PUC inverter and consists of a voltage controller as an outer loop and a current controller as an inner loop. The outer loop regulates the PUC inverter capacitor voltage as the second dc bus. The inner loop is in charge of controlling the flowing current, which is also used to charge and discharge that capacitor. The main goal of the whole system is to keep the dc capacitor voltage at a certain level results in generating a smooth and quasi-sine-wave seven-level voltage waveform at the output of the inverter with low switching frequency. The proposed controller performance is verified through experimental tests. Practical results prove the good dynamic performance of the controller in fixing the PUC capacitor voltage for various and variable load conditions and yet generating low-harmonic seven-level voltage waveform to deliver power to the loads. Operation as an uninterruptible power supply (UPS) or ac loads interface for photovoltaic energy conversion applications is targeted. [ABSTRACT FROM AUTHOR]

An isolated multilevel dc–dc power converter is proposed in this paper. The proposed isolated multilevel dc–dc power converter consists of an isolated power converter, a series/parallel switching circuit, and an output L–C filter. The isolated power converter is composed of a half-bridge inverter, a three-winding transformer, and two full-bridge rectifiers. The half-bridge inverter is switched in constant duty to generate two output dc voltages through two secondary windings of the three-winding transformer and two full-bridge rectifiers, respectively. The series/parallel switching circuit is used to control the two output dc voltages of the isolated power converter connected in series or in parallel, to control the output voltage of isolated multilevel dc–dc power converter. To verify the performance of the proposed isolated multilevel dc–dc power converter, a prototype is developed and tested. The experimental results show that the proposed isolated multilevel dc–dc power converter has the expected performance. [ABSTRACT FROM PUBLISHER]

A capacitor voltage-balancing method for a nested neutral point clamped (NNPC) inverter is proposed in this paper. The NNPC inverter is a newly developed four-level voltage-source inverter for medium-voltage applications with properties such as operating over a wide range of voltages (2.4–7.2 kV) without the need for connecting power semiconductor in series and high-quality output voltage. The NNPC topology has two flying capacitors in each leg. In order to ensure that the inverter can operate normally and all switching devices share identical voltage stress, the voltage across each capacitor should be controlled and maintained at one-third of dc bus voltage. The proposed capacitor voltage-balancing method takes advantage of redundancy in phase switching states to control and balance flying capacitor voltages. Simple and effective logic tables are developed for the balancing control. The proposed method is easy to implement and needs very few computations. Moreover, the method is suitable for and easy to integrate with different pulse width modulation schemes. The effectiveness and feasibility of the proposed method is verified by simulation and experiment. [ABSTRACT FROM PUBLISHER]

The multizonal medium voltage dc architecture of all-electric ship shipboard power systems (SPSs) includes a variety of distributed energy resources, energy storage devices, and power electronic voltage source converters. Due to the limited fuel supply and tight space, control of the converters should be aimed at increasing their efficiency and compactness. In this paper, a novel approach to voltage control in all-electric ship power systems is proposed to fulfill these goals. In contrast to the traditional SPSs that emulate the land-based electricity grid, maintaining a steady bus voltage is no longer an objective here. On the contrary, the voltage is compelled to fluctuate in order to minimize switching losses in the converters. A method for calculation of the minimum required dc voltage level is described, and results of computer simulations of an SPS with a flexible-voltage dc bus are presented. The minimum-voltage operation of the system results in a significant efficiency increase. [ABSTRACT FROM AUTHOR]

This paper presents a new hysteresis current regulation strategy for the neutral point clamped and flying capacitor (FC) three-level inverters. The strategy uses the measured average of the switched phase leg output voltage to adjust the controller hysteresis band as the load back EMF varies to maintain a near constant phase leg switching frequency. The phase leg switchings are then fine tuned to a fixed frequency clock to further improve frequency regulation. Next, the zero-crossings of the measured phase leg average voltages are used to select between positive and negative switched output voltage levels, so that only one hysteresis current regulator is required for the full inverter switched output voltage range. For the FC inverter, a state machine is then added to select between redundant switching states to maintain balanced capacitor voltages. Finally, the controller is extended to a three-phase system by subtracting the common mode interacting current from the total phase leg current error before making any switching decision. The resulting controller achieves a line-to-line harmonic performance that is very close to open-loop phase disposition pulse width modulation, while retaining all of the dynamic benefits of hysteresis current regulation. [ABSTRACT FROM AUTHOR]

Hybrid cascade multilevel inverters combine semiconductor devices of different voltage ratings and technologies, which theoretically allow high efficiency to be achieved. The bottlenecks of these topologies are, however, the need for isolated supplies for the cells and the lack of modularity. This paper focuses on the design and control of high-resolution, high-efficiency multilevel inverters with simplified dc power supplies. It introduces several rules for systematically designing the dc voltages of the cells, for which all unsupplied capacitor voltages can be regulated. Six classes of inverters are obtained covering single- and three-phase, staircase and pulsewidth-modulated (PWM) inverters. New configurations of hybrid cascade multilevel inverters are obtained for each class. A double modulation strategy with two different frequencies is proposed that allows switching losses of PWM inverters to be reduced. Decoupled mechanisms are proposed for the total and internal energy balances. It is shown how to make the design robust by taking into account conversion losses and large dc-voltage imbalances in the design and control. An analysis of the maximum voltage utilization and efficiency of the resulting configurations is carried out. The effectiveness of the novel concepts is validated experimentally for two of the proposed topologies. [ABSTRACT FROM PUBLISHER]

Due to the long cold start time and slow dynamics of proton exchange membrane (PEM) fuel cell (FC) stack, operating modes transfer control strategy for fuel cell uninterruptible power supply (FC-UPS) is different from the traditional uninterruptible power supply (UPS) system. In this paper, a seamless transfer control strategy, which is suitable for FC-UPS, is proposed. The power conversion architecture of FC-UPS is presented with the characteristic analysis of PEMFC and the requirements of UPS. Then, the scheme of the seamless transfer control strategy is investigated. The proposed seamless transfer control strategy is not only capable of guaranteeing the uninterruptible load voltage, but also protecting FC against the power demands beyond its allowable bandwidth during the transition for long lifespan and safety. Finally, the control scheme has been verified on a 10-kW FC-UPS prototype. [ABSTRACT FROM AUTHOR]

AC test power sources are essential for testing electric equipment that is ac-mains connected. Typically, linear power amplifiers (LPAs) are mainly employed as ac test sources because of their high fidelity and excellent dynamic behavior. However, these LPAs have very high losses in their output stages, which make the systems bulky and expensive due to the large heatsinks that are required. In recent years, two approaches have attracted popular interest to improve the efficiency of ac power sources. These are hybrid operation, i.e., combination of linear and switch mode, and multilevel switch-mode inverters. In this paper, three types of multilevel power amplifiers, based on hybrid or switching technology, are presented, namely: hybrid multicell amplifier (H-MCA), amplitude-modulated (AM) + pulsewidth-modulated (PWM) MCA (AP-MCA), and PWM MCA (P-MCA). For each of these topologies, the operating principle and control scheme are introduced. Finally, a 1-kVA laboratory prototype, which can realize all the three topologies, is built, and the measured performance based on this universal prototype are compared. [ABSTRACT FROM PUBLISHER]