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In this paper, the third quadrant behavior of a high-voltage superjunction mosfet (SJ-FET) in cascode configuration (CC) with a low-voltage silicon mosfet is deeply studied by means of an analytical model and experimental data. The third quadrant dynamic behavior of the SJ-CCs is compared to the standalone counterparts by evaluating their reverse recovery time (tRR), reverse recovery peak current (IRRM), and reverse recovery charge (QRR). An analytical model and experimental results show that the SJ-CC avoids or mitigates the activation of the SJ-FET body diode during the third quadrant operation. As a consequence, the SJ-CC strongly improves the widely used figure-of-merit RON·QRR, which considers the on-state resistance of the transistors (RON). In addition, the results obtained using an SJ-CC are similar or better than those achieved by SJ-FETs with enhanced reverse recovery (i.e., irradiated SJ-FETs). This paper also includes a comparison with commercial wide bandgap switches, concluding that the RON·QRR value provided by the SJ-CC is around eight times higher than that provided by a commercial GaN cascode. [ABSTRACT FROM AUTHOR]

Superjunction MOSFETs in cascode configuration with low-voltage silicon MOSFETs are evaluated in this paper. The proposed structure combines the good switching performance provided by the cascode configuration with the benefits of the silicon technology such as its robustness, maturity, and low cost. This paper aims to explain and to demonstrate the reduction of switching losses of superjunction MOSFETs in cascode configuration with respect to their standalone counterparts (directly driven). A detailed simulation analysis of power loss contributions is carried out under hard-switching operation. Moreover, experimental evidence is provided using a boost converter (100–400 V) operating in continuous conduction mode for different switching frequencies (100–400 kHz) and output power levels (180–500 W). [ABSTRACT FROM AUTHOR]

Quasi-square wave mode with zero voltage switching (QSW-ZVS) is an operation mode in which the switching losses can be minimized. However, a large inductance current ripple is needed in this mode, which limits the maximum attainable power of the topology. A possible way to increase the power managed by a QSW-ZVS mode converter is to use a modular converter. An input parallel output parallel (IPOP) arrangement, in which the current can be shared among the modules, can increase the total power proportionally to the number of modules. This paper addresses two main proposals. The first one is a master–slave technique to extend the QSW-ZVS mode to an IPOP modular converter, achieving an interleaved solution which minimizes the total input current ripple and assures the current balance among the modules. The second one is a comparison of four different control techniques applied to the IPOP modular converter to improve the overall efficiency at light to medium load: balanced master–slave technique, master–slave with phase-shedding, asymmetrical master–slave, and burst mode (or hysteretic control). These four strategies are theoretically analyzed, experimentally validated and compared using a 150–400 V 2 kW modular IPOP prototype made up of four synchronous boost converter operating in QSW-ZVS mode. [ABSTRACT FROM PUBLISHER]

Envelope tracking (ET) is a technique designed to enhance the efficiency of radio frequency power amplifiers (RF PA). It is based on providing the voltage to the RF PA with variations that mimic the shape of the envelope of the communication signal that the RF PA is processing. As the bandwidth of these signals can be around several megahertz, the switching frequency of the switching mode power supply designed for ET applications has to be very high. The good switching characteristics of Gallium Nitride devices makes them suitable for this application. This paper presents two multiphase converters to be used as envelope modulators in envelope tracking applications. [ABSTRACT FROM AUTHOR]

This paper addresses the performance of the bidirectional dual active bridge (DAB) converter. One of the advantages of the DAB is the possibility to achieve the zero-voltage switching (ZVS) operation in all the switches of this converter. However, the ZVS operation range can be lost for light loads, especially if high voltage is required in at least one of the DAB ports and the phase-shift control is used to regulate the power processed by the converter. Theoretically simple averaged and small-signal models are presented for the DAB converter. Using the study presented in this paper, the boundaries of the ZVS operation can be easily evaluated. The proposed models and analysis of the ZVS boundaries allow the proposal and evaluation of two different design strategies with different purposes: on the one hand, increasing the ZVS operation range and, on the other, improving efficiency at full load. Moreover, some techniques are presented for increasing the ZVS operation range and improving the efficiency of the DAB at full load (both using phase-shift control) employing the aforementioned analysis to obtain certain design criteria and conclusions. Finally, the proposed models, design strategies, and techniques to improve the performance of the DAB are experimentally tested using a 1-kW prototype with input and output voltages of 48 and 400 V, respectively. [ABSTRACT FROM AUTHOR]

The new wide band-gap semiconductor devices provide new properties to be explored. Normally on silicon carbide (SiC) JFET power devices have several advantages, in particular low switching losses and the potential capabilities of high temperature and high reverse blocking voltage. Looking for improving the overall efficiency in power converters, new structures based on these power devices might be studied. In this paper, a cascode rectifier based on normally on SiC JFET is presented and analyzed. This rectification structure can be applied as front-end rectifier stage for ac-dc power converters, increasing the overall efficiency of these topologies. A second cascode rectifier based on silicon (Si) MOSFET is also studied, as a low-cost alternative. A simple static forward characterization and a brief dynamic behavior analysis of the proposed cascode rectifier structure are made. Both cascode structures are compared with traditional Si rectifier diodes and front-end rectifiers, using an active power factor corrector (PFC) interleaved boost converter. As a result of this comparison, an efficiency improvement as high as two points is obtained. An additional OR gate based on a diode is also used as second test circuit to compare the proposed structures to the traditional Si rectifiers. A reduction between 75% and 55% of the total loss are obtained in this second experimental test. [ABSTRACT FROM AUTHOR]

The efficiency of linear power amplifiers can be improved by modulating its supply voltage according to the peak value of the signal that is being amplified in a technique usually known as envelope tracking. High bandwidth dc/dc converters called envelope amplifiers (EAs) are used to carry out the supply modulation in an efficient manner. In the case of linear RF power amplifiers, the bandwidth requirements over the EA strongly depend on the signal being amplified: in modern telecommunication applications it can range from several hundred kilohhertzs to a few tens of megahertz. The path to achieve such bandwidths usually goes through increased switching frequencies and/or reduced ratio of switching frequency to converter bandwidth. However, these may lead to lower converter efficiency and increased distortion, making the design of EAs a challenging task. This paper addresses the analysis and design of the output filter for Buck converters operating as EA. The output filter must provide enough attenuation at the switching frequency and harmonics to guarantee a desired level of distortion while enabling tracking of wide-bandwidth envelope signals with high converter efficiency. This paper focuses on the use of high-order filters (up to sixth-order Bessel-Thomson, Butterworth, and Legendre-Papoulis filters) in a buck dc/dc converter working as an EA. The filters are analytically described and characterized, and a design procedure that takes into account the major design constraints is proposed, allowing the selection of the appropriate filter for a given application. The proposed analysis and design method are supported by simulation results, as well as by experiments obtained using a 1 MHz buck converter operating as an EA. [ABSTRACT FROM AUTHOR]