Search

This paper presents a novel seven-level inverter topology for medium-voltage high-power applications. It consists of eight active switches and two inner flying capacitor (FC) units forming a similar structure as in a conventional active neutral-point-clamped (ANPC) inverter. This unique arrangement reduces the number of active and passive components. A simple modulation technique reduces cost and complexity in the control system design without compromising reactive power capability. In addition, compared to major conventional seven-level inverter topologies, such as the neutral point clamped, FC, cascaded H-bridge, and ANPC topologies, the new topology reduces the dc-link voltage requirement by 50%. This recued dc-link voltage makes the new topology appealing for various industrial applications. Experimental results from a 2.2-kVA prototype are presented to support the theoretical analysis presented in this paper. The prototype demonstrates a conversion efficiency of around 97.2% ± 1% for a wide load range. [ABSTRACT FROM AUTHOR]

The output voltage of power electronic converters is a very important quantity for dynamic control of power electronic systems. In electrical drives without electromechanical position or speed sensor, the terminal reference voltage is used to obtain the rotor position. Dead-time effects and semiconductor voltage drop lead to distortion in the actual output voltage and degrade the control performance when the back electromotive force magnitude is low. Thus, for stable low-speed operation, output voltage sensing becomes necessary. Due to the switching nature of power electronic systems, this is not a trivial task, especially when instantaneous measurement of the terminal voltage is required. In this paper, an instantaneous switching-period average voltage sensing technique is proposed that utilizes a combined approach of oversampling and filtering. Based on the theoretical analysis of the sampling- and filter-induced measurement distortion, a general solution for an optimal filter design is derived. The additional sensing circuit is integrated into the low-side gate driver of the converter outputs. This paper includes details about the hardware implementation and extensive verification measurements. [ABSTRACT FROM AUTHOR]

The pulse-width modulated (PWM) switching rectification that can achieve a high power factor (PF) for increasing the energy transfer efficiency between an LC resonator and a rectifier and voltage step-up and -down conversion is proposed for a wireless power transfer (WPT) receiver. The proposed method can emulate the switching rectifier as a resistive load by using an inductor and integrated phase synchronizers. Additionally, similar to a switched-inductor converter that controls the duty cycle ratio (D), the proposed PWM rectifier can control the output voltage VOUT when the input is a rectified, wirelessly coupled voltage instead of a constant voltage. Thus, unlike a conventional PWM switching rectifier for ac mains, an additional voltage conditioning circuit would not be needed after the proposed rectifier for WPT. The proposed PWM switching rectification is implemented in the AMS 0.18 μm 1.8 V/5 V CMOS process. PF = 1 is measured, indicating the most efficient energy transfer, compared to only 0.55–0.65 in a peak detection rectifier. Additionally, 88.2% of peak power conversion efficiency of the switching rectifier is achieved, and the maximum output power is 80.3 mW at 500 kHz of the WPT frequency. Moreover, the measured voltage conversion ratios ranging between 0.73× and 2× are demonstrated in this paper. [ABSTRACT FROM AUTHOR]

This paper proposes a generalized design framework for three-phase Vienna rectifiers to handle the neutral point voltage balance issue. On the basis of the design framework, it is convenient to construct various neutral point voltage balancing methods with the guarantee of stability. As demonstration, three representative neutral point voltage balance approaches are presented by choosing different zero-sequence voltages. A comprehensive comparison among the three approaches is given in the aspects of input current quality, capacitor voltage fluctuation, and system efficiency. The comparison results provide guidance for constructing the most appropriate approach based on the specific requirement. Finally, simulation and experimental results verify the correctness and effectiveness of the presented approaches and the related performance analysis. [ABSTRACT FROM AUTHOR]

In order to reduce switching loss of neutral point clamped three-level inverter (NPC TLI), generally discontinuous pulsewidth modulation (DPWM) is used. But it can result in dc offset and ac ripple on neutral point (NP) voltage. So a novel pulse sequence DPWM (NPSDPWM) is proposed to reduce switching loss and control NP voltage simultaneously in this paper. NP voltage is controlled by choosing proper clamping modes. To avoid unexpected switching action during changing clamping mode, an improved pulse sequence is also presented. The switching loss and NP voltage ripple of NPSDPWM, traditional and proposed DPWM in previous literature are compared, respectively. The experimental results show that NPSDPWM has well NP voltage control ability and the switching losses are reduced effectively. [ABSTRACT FROM AUTHOR]

In this paper, a novel discontinuous pulsewidth modulation (DPWM) modulation strategy for a neutral-point-clamped (NPC) three-level converter (TLC) is proposed to reduce the switching loss, reduce common-mode voltage (CMV), and remove dc offset from the neutral-point (NP) voltage simultaneously, which is named as RCMV_DPWM. Based on the space vector diagram with reduced CMV, all clamping modes under RCMV_DPWM are revealed. Then, the NP voltage is controlled by selecting proper clamping mode. The realization of RCMV_DPWM is also discussed. Moreover, the performances of RCMV_DPWM are analyzed and compared with other PWM strategies in term of the NP voltage ripple, switching loss, and waveform quality. Finally, the feasibility and superiority of RCMV_DPWM are verified by experiments. [ABSTRACT FROM AUTHOR]

Rotor position estimated with high-frequency (HF) voltage injection methods can be distorted by voltage errors due to inverter nonlinearities, motor resistance, and rotational voltage drops, etc. This paper proposes an improved HF square-wave voltage injection algorithm, which is robust to voltage errors without any compensations meanwhile has less fluctuation in the position estimation error. The average position estimation error is investigated based on the analysis of phase harmonic inductances, and deduced in the form of the phase shift of the second-order harmonic inductances to derive its relationship with the magnetic field distortion. Position estimation errors caused by higher order harmonic inductances and voltage harmonics generated by the SVPWM are also discussed. Both simulations and experiments are carried out based on a commercial PMSM to verify the superiority of the proposed method and the investigations in this paper. [ABSTRACT FROM AUTHOR]

In this paper, a novel space-vector pulsewidth modulation technique for a five-level active neutral-point clamped (5L-ANPC) inverter is proposed to eliminate the common-mode voltage (CMV). For the 5L-ANPC inverter, which produces a good output voltage performance and lowdv/dt, the total 125 voltage vectors can be generated, among which the proposed scheme employs only 19 voltage vectors producing a zero CMV. Due to the limitation of voltage vectors selected, the dc-link capacitor voltages of the 5L-ANPC inverter cannot be balanced by themselves. Therefore, the capacitor voltages of the inverter should be controlled by choosing the redundant switching states appropriately. The validity of the proposed modulation scheme has been verified by simulation and experimental results. [ABSTRACT FROM AUTHOR]

High step-down voltage conversion is necessary to bridge the voltage gap between main power converters and low-voltage auxiliary electronics in power conversion systems. Switched capacitor converters (SCCs) are an attractive candidate as a high step-down converter, but their poor voltage regulation capability may limit their applications. Pulsewidth modulation (PWM) SCCs with adjustable high step-down voltage conversion are proposed in this paper. The proposed PWM SCCs can be derived from traditional SCCs by replacing an energy transfer capacitor with a switched-capacitor-inductor (SCL) cell that comprises inductors, capacitors, and diodes to realize PWM-controllable voltage conversion. The voltage step-down ratio of the proposed PWM SCCs is not only PWM controllable but also adjustable with structures of SCCs and SCL cells. Two representative PWM SCCs were taken as examples to perform the operational analysis. The prototypes of both representative PWM SCCs were built and tested to demonstrate the proposed concept. [ABSTRACT FROM AUTHOR]

At present, virtual flux voltage oriented control strategy is one of the widely used control strategies without grid voltage sensor. To solve the dc bias resulting from voltage vector integration in vector calculation of virtual flux and further avoid the steady-state error, a virtual flux observer with negative feedback resonant filter is presented in this paper based on virtual flux principle and a delay compensation algorithm is also proposed to solve the delay of virtual flux. In addition, the control system diagram of the pulsewidth modulated rectifier without grid voltage sensor is brought forth. Then, simulation system and experimental platform are both established to simulate and test the rectifier. Eventually, the correctness and feasibility of the proposed algorithm are verified through the analysis of simulation and experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes the new clamping angle control (CAC) pulse width modulation (PWM) method to restore its maximum linear modulation range of voltage source inverters (VSIs) reduced by the duty ratio limitation in hardware implementation, which makes the VSIs to operate nonlinearly in the high modulation range. The deadtime and the bootstrap gate driver circuit mainly cause this duty ratio limitation in practice. In particular, the bootstrap gate driver circuit is used in many industrial applications by avoiding the additional power supply to apply the gate-source voltage of power switches, and therefore making the VSIs to be small size with the low cost. First, the proposed CACPWM method is theoretically analyzed. Then, it is applied in the high modulation range to overcome the limitation of the duty ratio due to the use of the bootstrap gate driver circuit. Thereafter, its practical effectiveness is verified by both simulation and experimental tests. Also, the resulting harmonic distortions are compared with those by the conventional PWM methods. [ABSTRACT FROM AUTHOR]

In this paper, a new pulse width modulation (PWM) scheme and commutation method is presented for one phase loss operation of three-phase isolated buck matrix-type rectifier. With the proposed PWM scheme, the maximum allowable voltage gain for one phase loss operation can be achieved, which permits the continuous operation of the converter to deliver two-third of the rated power and regulate the output voltage with maximum output voltage drop less than 5% of nominal output voltage. In addition, with the proposed commutation method, a safe transition from one phase loss operation to normal operation and vice versa can occur with minimum commutation steps (two-step) under zero-voltage switching condition. The performance of the proposed PWM scheme and commutation schemes with one phase loss operation is evaluated and verified by simulations and experiments on a 5 kW prototype. [ABSTRACT FROM AUTHOR]

This paper presents the active capacitor voltage-balancing (ACVB) methods based on the dynamic model for a five-level nested neutral-point piloted (NNPP) converter using hybrid carrier modulation. The traditional hybrid carrier modulation provides natural voltage balancing of floating capacitors and dc-link capacitors. First, the natural voltage-balancing ability under steady-state and ideal conditions is theoretically proved. However, there are accumulated errors and deviations of capacitor voltages in practical applications, especially under dynamic conditions. In order to address the accumulated errors and deviations of capacitor voltages, the dynamic models of floating-capacitor voltages and neutral-point voltage are established. Moreover, the ACVB method based on the dynamic model of the neutral-point voltage is proposed by injecting the zero-sequence voltage. And the ACVB method based on the dynamic model of floating-capacitor voltages is proposed by introducing the adjustment variables. The proposed ACVB methods have the advantages of simple formula, definite physical meaning, and high accuracy. Furthermore, the output voltage quality and current quality are evaluated in term of total harmonic distortion and the effect of model parameter mismatch on the proposed ACVB methods is presented. Finally, the comparative simulation and experimental results verify the correctness of the proposed ACVB methods based on the dynamic model under different conditions. [ABSTRACT FROM AUTHOR]

Full-bridge (FB)-boost converter is suitable for applications with wide input voltage range and galvanic isolation requirement, and a two-mode phase-shift (PS)-two-edge modulation (TEM) control scheme based on two modulation signals and one carrier can be used to achieve automatic mode shifting and high efficiency. In order to reduce the influence of the input voltage disturbance on the output voltage, the small-signal model of FB-boost converter is built and the input voltage feed-forward (IVFF) functions under different operating modes are derived in this paper. In view of the small-signal and large-signal control laws of the derived IVFF functions, the two-mode PS-TEM control schemes with small-signal and large-signal IVFF compensations are proposed, respectively. Both of them can realize automatic selection of operating modes and the corresponding IVFF compensations, and thus high efficiency and improved input transient response can be guaranteed. Besides, the IVFF function in boost mode is simplified for easy implementation, and the comparisons among the two-mode PS-TEM control schemes with small-signal, large-signal, and without IVFF compensations are presented in this paper. Finally, a 250-500-V input, 360-V output, and 6-kW-rated power prototype demonstrates the effectiveness of the proposed control schemes. [ABSTRACT FROM AUTHOR]

This paper presents a new multilevel selective harmonic elimination pulse-width modulation (MSHE-PWM) technique for transformerless static synchronous compensator (STATCOM) system employing cascaded H-bridge inverter (CHI) configuration. The proposed MSHE-PWM method optimizes both the dc-voltage levels and the switching angles, enabling more harmonics to be eliminated without affecting the structure of the inverter circuit. The method provides constant switching angles and linear pattern of dc-voltage levels over the modulation index range. This in turns eliminates the tedious steps required for manipulating the offline calculated switching angles and therefore, easing the implementation of the MSHE-PWM for dynamic systems. Although the method relies on the availability of the variable dc-voltage levels which can be obtained by various topologies, however, the rapid growth and development in the field of power semiconductor devices led to produce high-efficiency dc-dc converters with a relatively high-voltage capacity and for simplicity, a buck dc-dc converter is considered in this paper. Current and voltage closed loop controllers are implemented for both the STATCOM and the buck converter to meet the reactive power demand at different loading conditions. The technique is further compared with an equivalent conventional carrier-based pulse-width modulation to illustrate its enhanced characteristics. The effectiveness and the theoretical analysis of the proposed approach are verified through both simulation and experimental studies. [ABSTRACT FROM AUTHOR]

Insertion of dead time, transfer links between micro control unit (MCU) and voltage source inverter (VSI), VSI's nonideal characteristics all lead to deviation that cannot be ignored between the actual output voltage and the command voltage, which seriously affects the performance of the ac induction motor (ACIM) control system. Among many dead-time effect compensation methods, VSI usually operates under an open-loop condition, thus making complete compensation hard to achieve. This paper studies methods to obtain the two key elements of compensation voltage amplitude and current polarity and a novel phase voltage compensation method is proposed. In this method, a simple hardware circuit is applied to obtain the actual output of the VSI as feedback with which precise compensation amplitude can be calculated. And judgment of current polarity is accurately realized by reconstructing phase current from filtered current components under M-T coordinate with a Kalman filter. The compensation in a zero-crossing region is also closely discussed in this paper. To verify the validity of the method, simulations and experiments are carried out. The experiments emphasize on the efficacy of feedback, steady-state, and transient performance of current reconstruction; and the performance of a conventional method to that of the proposed method are also compared. Results show that the proposed method proves to be effective. [ABSTRACT FROM AUTHOR]

The flying-capacitor modular multilevel converter (FC-MMC) overcomes the low/zero-speed operation issues of conventional MMC-based drive. The FC-MMC injects no common-mode voltage (CMV) to the drive system. However, the pulse width modulator (PWM) introduces switching ripples, which appear as CMV on motor stator windings. To completely get rid of the CMV, an elimination method based on a new modulation scheme is proposed in this paper. The modulation algorithm places the switching pulses end to end for upper and lower arms, respectively. The consistent switching positions between upper and lower arms lead to the complete CMV elimination for FC-MMC-based drive system in entire speed range. Although the proposed method slightly increases the switching frequency as compared to conventional phase-shifted PWM, it is still acceptable in medium-voltage applications. The validation of the proposal is proved by simulations and experiments. [ABSTRACT FROM PUBLISHER]

The noninverting buck–boost converter has attracted significant attention in the photovoltaic (PV) module integrated application, as it offers high efficiency while maintaining a low cost and a simple topology. When this converter is employed, special care must be taken at the transition between buck and boost operating modes, as a dead-zone in the voltage transfer function can cause abrupt perturbations in the controlled voltage, decreasing the regulation quality and ultimately lowering the power conversion efficiency. In this paper, a new dead-zone compensation technique is proposed with the scope of smoothing the transition between operating modes, eliminating the voltage ripple and improving the regulation performance, while maintaining high efficiency. The converter under analysis is studied together with its gate driving circuit, which is based on a bootstrap capacitor power supply for the high-side switches. The proposed dead-zone compensation technique is deduced by using the principle of maintaining the ideal voltage gain function across the converter operating range. The technique is analyzed, implemented and tested on a purposely built PV module integrated noninverting buck–boost converter. The experiments reveal a sensible improvement of the voltage regulation during mode transition, confirming the effectiveness of the proposed technique and its fitness for the PV application. [ABSTRACT FROM AUTHOR]

Five-level hybrid-clamped (5L-HC) converter is a newly proposed topology which is suitable for high-performance medium-voltage high-power conversions without switches directly connected in series. The critical issue of this converter is that two flying capacitor voltages of each phase and two neutral-point potentials of the dc-link need to be balanced. This paper presents a decoupled voltage balancing method for this 5L-HC converter based on modified phase-shifted pulse width modulation (PS-PWM) and optimal zero-sequence voltage injection. The voltages across the central dc-link capacitor and two flying capacitors are balanced first by adjusting the width of four PWM signals. Second, the relationship between the neutral-point currents and the output phase voltage is studied and the upper and lower dc-link capacitor voltages are balanced by zero-sequence voltage injection. Both steady-state and dynamic-state simulation and experimental results are presented to confirm the validity of this method. [ABSTRACT FROM AUTHOR]

Presently, the neutral-point potential offset is an inherent problem for three-level converters on three-phase four-wire active power filters. The conventional three-dimensional space vector pulse width modulation (3-D-SVPWM) strategy is adopted as a normal solution to the problem, but the selection of space vector sectors for four-wire converter is both abstract and complicated in practice. This paper proposes a new PWM strategy accordingly to simplify the selection process and the calculation of duration. Compared to the conventional 3D-SVPWM, the proposed method locates the sector of optimal vector directly with the polarity of three-phase reference voltage. Then, by applying voltage–second balance rule, it can perform a fast calculation of the duration and generate PWM signals to control the switching devices’ on/off. As an approach to correct the imbalance dc-link capacitor voltage, this strategy reconstructs the switching sequence. A portion of state O duration is disassembled into states P and N to suppress the neutral-point potential offset. The proposed strategy is validated with a range of experiments. The results indicate that this simplified PWM strategy can effectively reduce the computational burden, and also the dc-link capacitor voltage is well controlled. [ABSTRACT FROM PUBLISHER]

The objective of this paper is to propose an efficiency model to evaluate the impact of the pulse width modulation (PWM) duty cycle jitter on the efficiency of switching-mode power converter. By taking the product of two perturbation terms into consideration, which is ignored in the conventional average small-signal model, the average efficiency model is proposed first. Due to the nonlinear characteristic of the PWM generator, the multifrequency efficiency model is also developed by considering the sideband frequency. Three different perturbation waves are induced to the control loop of the converter to generate the jitter to observe its impact on the efficiency. The mathematical expression of the efficiency drop based on the proposed multifrequency model is derived. The reason of control-to-output gain's magnitude spike on the Bode plot can be explained by the derived equations. Eventually, the methods to reduce the efficiency drop caused by the jitter are suggested. In spite of various perturbation frequencies, amplitudes, and waveforms, the mathematical calculation, the computer simulation, and the hardware measurement of the efficiency drop are consistent which validate the accuracy of the proposed multifrequency efficiency model. [ABSTRACT FROM AUTHOR]

Dynamic voltage restorer (DVR) technology has become a mature power quality product. In high-power applications, DVR using a multilevel converter is commonly used. However, DVR using a multilevel direct pulse width modulation (PWM) ac–ac converter has not been well studied. This paper presents a new DVR topology using a cascaded multilevel direct PWM ac–ac converter. In the proposed scheme, the unit cell of the multilevel converter consists of a single-phase PWM ac-ac converter using switching cell structure with coupled inductors. Therefore, the multilevel converter can be short- and open-circuited without damaging the switching devices. Neither lossy RC snubber nor a dedicated soft commutation strategy is required in the proposed DVR. This improves the reliability of the DVR system. The output voltage levels of the multilevel converter increase with the number of cascaded unit cells, and a high ac output voltage is obtained by using low-voltage-rating switching devices. Furthermore, a phase-shifted PWM technique is applied to significantly reduce the size of the output filter inductor. A 1-kW prototype of single-phase DVR is developed, and its performance is experimentally verified. Finally, the simulation results are shown for a three-phase DVR system. [ABSTRACT FROM AUTHOR]

This paper proposes a current-fed isolated bidirectional dc–dc converter (CF-IBDC) that has the advantages of wide input voltage range, low input current ripple, low conduction losses, and soft switching over the full operating range. Compared with conventional CF-IBDCs, the voltage spikes of the low-voltage (LV) side switches in the proposed converter can be eliminated without additional clamp circuits. The converter adopts the pulse width modulation plus hybrid phase-shift control scheme such that the bus voltage can match the output voltage by means of the transformer. Thus, the current stresses and conduction losses of the converter become lower. In addition, the practical zero voltage switching (ZVS) of the secondary-side switches can be realized by adjusting the phase-shift angle within the secondary side when in light load or no load condition. The operating principles and characteristics including the power transfer, root-mean-square (RMS) current, and soft switching are investigated in detail. Then the design guidelines of inductors are also given. Finally an experimental prototype with 30–60 V input and 400 V/2.5 An output is built to verify the correctness of theoretical analyses. [ABSTRACT FROM PUBLISHER]

In signal injection sensorless drives, the injection voltage cannot be reduced under a certain value. The lower limit of the injection voltage is mainly enforced by the inverter nonlinearity that causes distortion of the injection voltage and degradation of the position estimation performance. After analyzing the inverter nonlinearity during the voltage injection, it is revealed that parasitic capacitances of insulated-gate bipolar transistors have positive effects on inverter output linearity and sensorless control. Based on this analysis, this paper proposes a method to reduce the injection voltage by connecting additional capacitors to the output terminals of the inverter. Simulation and experimental results are provided to verify the effectiveness of the proposed idea. In the experiments, using the capacitor-integrated inverter, it is shown that the injection voltage can be reduced by more than half without degrading the position estimation performance. [ABSTRACT FROM AUTHOR]

Several novel digital assistant power integrated technologies (DAPITs) for power management unit (PMU) to reduce the designing complexity, as well as to keep good performance in scaling CMOS process, are proposed in this paper. The DAPITs include segment power driving with pulse skip modulation/pulse width modulation and loop regulating with digital regulation circuit for dc-dcs in PMU, calibrating digital-to-analog converter (DAC) with resistance compensation network for dynamic voltage scaling (DVS), and separating phase clock for multi-dc-dcs in PMU. With these DAPITs, the efficiencies and output accuracies of dc-dcs are increased, the DVS signal sent by DAC is linear, and current ripples in PMU are reduced. In this paper, a PMU embedded into system-on-a-chip (SoC) is designed based on a 0.13-μm CMOS process. The designed PMU includes four dc-dc buck converters and two LDOs. This paper introduces the top structure of the PMU and the main proposed DAPITs. Simulation and test results show that the output voltages of the dc-dc converters in the PMU can be changed by external resistors and regulated from 0.7 to 1.8 V stepped with 25 mV by SoC load through interface. And the maximum efficiency of the dc-dcs with DVS in the PMU is more than 90%, while, with an external resistor, it can reach to 95%. [ABSTRACT FROM AUTHOR]

The five-level active neutral-point-clamped (5L-ANPC) converter has been widely studied for its excellent performance in high-power medium-voltage applications. This paper analyzes the space vector pulse width modulation (SVPWM) strategy of the 5L-ANPC converter in the virtual coordinate, and presents an optimized control strategy which can balance the neutral point (NP) voltage and avoid the dead-time effects for the first time. In this strategy, on one hand, the 125 space vectors are combined by 96 triangles in the seven-segment vector synthesis method, then the triangles are divided into seven categories which have different characteristics of balancing the NP voltage, and every category has its own principles to choose the vector sequence and compute the vector durations. On the other hand, the dead-time effects of the 5L-ANPC converter are studied in detail and the transitions between different switching states are constrained in the optimized control strategy to avoid the dead-time effects that cannot be compensated by traditional pulse-based dead-time compensation methods. Finally, the optimized SVPWM strategy is experimentally verified in this paper. [ABSTRACT FROM AUTHOR]

A synchronous rectification buck converter in parallel with a Class AB linear amplifier is presented in this paper to construct an envelope-tracking (ET) power supply. To eliminate the influences of the output voltage on the linear amplifier output current, a full feedforward of the output-voltage scheme with two feedforward terms is proposed in this paper, which can counteract all the two load admittances of the linear amplifier, respectively, consequently decreasing the linear amplifier output current substantially. An ET power supply prototype with 100-kHz sine-wave tracking, 5-15 V output voltage, and 75-W-peak output power is fabricated and tested in the lab. The experimental results are well in agreement with the theoretical analyses, and the system efficiency is improved significantly. [ABSTRACT FROM AUTHOR]

Active power control plays an important role in a pulse width modulation (PWM) rectifier under both balanced and unbalanced network conditions. The prior methods to achieve active power oscillation cancellation (APOC) under unbalanced grid voltages are usually implemented by forcing the grid current to track appropriate current references. They require fine tuning work of a current controller and positive-/negative-sequence extraction of grid voltage/currents and/or converter voltage, which complicates the design of the controller. This paper presents two APOC methods in the frame of direct power control (DPC) for the PWM rectifier and reveals their inherent relationship. In the first method, an appropriate power compensation is added to the original power references without modifying the internal control structure. In the second method, a novel definition of reactive power is employed to replace conventional reactive power, which achieves the aim of APOC automatically. Both methods can be easily integrated with existing DPC schemes with a slight modification. The sequence extraction required in prior methods is eliminated. The inherent relationship between these two methods is investigated, and it is found that they are completely equivalent. The two APOC methods are comparatively studied and implemented in the basic table-based DPC. Simulation and experimental results confirm the theoretical study and the effectiveness of the two methods. [ABSTRACT FROM AUTHOR]

Primary-side controlled universal-line flyback converters have been widely used in low-power applications due to their simplicity, low standby power, and low cost. However, conventional OCP schemes normally cause too large a variation in output current when the input voltage varies. This paper proposes a self-compensating OCP circuit to achieve a high-precision constant current at different input voltages which can be used in flyback converters working in discontinues conduction mode. It consists of a CS S/H circuit and a dynamic OCP voltage reference circuit. Compared with conventional OCP circuits, it does not need an extra compensation circuit. To verify the feasibility and performance of the proposed circuit, an IC controller that uses the proposed OCP circuit has been designed and fabricated in 0.35 μm 5-V/40-V high-voltage CMOS technology. Experimental results show that the constant output current precision of the prototype is within ±1% when the input line voltage changes from 85 to 265 Vac. In the common line voltage range (\rm110-220\ Vac ), the output current regulation accuracy can reach a level as high as ± 0.3%. [ABSTRACT FROM AUTHOR]

This paper proposes a simplified instantaneous output power control to suppress the second harmonic dc-bus voltage due to asymmetry in a three-phase pulsewidth-modulated (PWM) converter system without any sequential component decomposers. Normally, in the instantaneous output power control, the positive and negative sequence output voltages and currents are required, and they are usually decomposed by notch filters or dual second-order generalized integrals that are difficult to tune and complicated. While in the proposed method, the positive-sequence and negative-sequence currents are regulated by PI plus resonant (PI-R) controllers in the dq frame. Therefore, the sequential current decomposers can be avoided. Meanwhile, the positive-sequence and negative-sequence output voltages, which are essential for calculating the positive-sequence and negative-sequence current references, are simply obtained from the outputs of the proportional−integral (PI) and resonant controllers, respectively. The proposed method is robust to any asymmetries and its effectiveness is verified on a prototype asymmetric three-phase permanent-magnet synchronous generator (PMSG) system with inherent and externally added asymmetries. [ABSTRACT FROM AUTHOR]

This paper presents a pulse width modulation strategy for the cancellation of common-mode (CM) voltage generated by three-phase back-to-back two-level inverters. This method theoretically provides complete elimination of the CM voltage by synchronizing all the commutations of one converter with commutations of the other one, so that the overall resulting CM voltage does not vary. The degrees of freedom of this strategy are studied and an experimental implementation is carried out on a 15-kW motor drive prototype to validate the method effectiveness. Taking into account deadtime compensation, measurements in time and frequency domains show that the CM voltage is strongly reduced and that more than 15 dB reduction is achieved in a wide frequency range. [ABSTRACT FROM AUTHOR]

In this paper, a single-phase buck–boost matrix converter is proposed which can both buck and boost the input voltage with step-changed frequency. It consists of only six unidirectional current flowing bidirectional voltage blocking switches, two input and output filter capacitors, and one inductor. It has following advantages over the existing single-phase matrix converters: 1) it can both buck and boost input voltage solving the limited voltage transfer ratio (only boost or buck) problem; 2) it also has enhanced reliability as it is immune from shoot-through problem of voltage source when all switches are turned-on simultaneously, and, therefore, it has no need of PWM dead times and RC snubbers or dedicated soft-commutation strategies to solve the commutation problem; 3) it can also use high-speed power MOSFETs as their body diodes never conduct, which eliminate their poor reverse recovery problem. The operation principle of the proposed converter is given, and switching strategies are developed to obtain various multiples and submultiples of input frequency. To verify its performance, a laboratory prototype is fabricated and experiments are performed to produce step-down and step-up voltage with three different frequencies of 120, 60, and 30 Hz. [ABSTRACT FROM PUBLISHER]

This paper presents a three-phase back-to-back transformerless inverter for online uninterruptible power supply applications. The inverter consists of a three-phase three-wire input rectifier stage and a three-phase four-wire output inverter stage with their ground wires tied together. Both of the two stages are with sinusoidal pulse width modulation based division-summation (D-∑) digital control. The input stage controls the power flow between utility grid and dc link, regulates the dc-link voltage, and fulfills power factor correction. While the output stage tracks three-phase ac reference voltages. The proposed control laws derived based on the D-∑ digital approach take into account the effects of dc-link voltage fluctuation, grid-voltage distortion, and inductance variation due to different current levels. Thus, distortion of input current and output voltage, and filter inductor core size can be reduced significantly. Moreover, circulating current through their common ground can be suppressed effectively. Simulated and experimental results from a three-phase back-to-back transformerless inverter have confirmed the analysis and discussion of the proposed control approach. [ABSTRACT FROM PUBLISHER]

Diode-assisted buck–boost voltage-source inverter achieves high voltage gain by introducing a switch-capacitor based high step-up dc–dc circuit between the dc source and inverter bridge. As for the unique structure, various pulse width modulation (PWM) strategies are developed with regard to the chopped intermediate dc-link voltage. In order to maximize voltage gain and increase efficiency, this paper proposes a novel PWM strategy. It regulates the average value of intermediate dc-link voltage in one switching time period ( Ts) the same as the instantaneous maximum value of three-phase line voltage by controlling the front boost circuit. Then, the equivalent switching frequency of power devices in the inverter bridge can be reduced to 1/3fs (fs = 1/Ts). The operating principle and closed-loop controller design are analyzed and verified by simulations and experiments. Compared with existing PWM strategies, the new control strategy demonstrates less power device requirement and higher efficiency in high voltage gain applications. It is a more competitive topology for wide range dc/ac voltage regulation in renewable energy applications. Furthermore, with new control strategy, the dc-side inductor current and capacitor voltage contains six-time line-frequency ripples. To overcome the undesired influence of low frequency ripples, it is also suitable for 400–800 Hz medium frequency aircraft and vessel power supply system. [ABSTRACT FROM PUBLISHER]

This paper investigates the problem of fluctuation of the neutral-point potential (NPP) in a three-level NPC inverter with a capacitor-voltage loop. The phase pulse width duty cycle disturbance pulse width modulation (PWM) method is proposed to suppress the NPP fluctuation efficiently. Based on the basic carrier-based phase-disposition PWM method, the average pulse neutral-point current model is established. Then, the frequency, amplitude, and equivalent initial phase of the NPP fluctuation are analyzed based on the current model. According to the alternating error of the dc-link capacitor voltages, a capacitor-voltage loop with a quasi-proportional resonant (PR) controller is presented. The control variable, which varies with the modulation index, phase current, load power factor, etc., can be obtained from the quasi-PR controller. Finally, an experimental three-level NPC inverter is described and the validity and feasibility of the proposed method are verified by experimental results. [ABSTRACT FROM AUTHOR]

Modular multilevel converter (MMC) is considered to be one of the most promising multilevel topologies from the medium- to high-voltage power applications. However, by reason of energy exchange between the dc side and ac side, the fluctuation of sub-module (SM) capacitor voltage for the MMC system is inevitable. Moreover, this fluctuation would deteriorate the total harmonic distortion (THD) of the output voltage. The influence of the fluctuation of the SM capacitor voltage on the output voltage is analyzed mathematically in detail. In this paper, an improved phase-shifted carrier (PSC) pulse width modulation (PWM) for the MMC is presented to suppress the influence of the fluctuation of SM capacitor voltage. This improved modulation can be regarded as a nonlinear compensation applied in the traditional PSC-PWM method. The THD of the output voltage is improved with this modulation method noticeably. Simulation and experiment results verify the effectiveness of the proposed modulation. [ABSTRACT FROM AUTHOR]

The paper presents an analysis on the output current ripple in zero common-mode voltage (ZCMV) PWM control of multilevel inverters. The modulation strategy for common-mode voltage (CMV) elimination in multilevel inverters is based on the “three zero common-mode vectors” principle. The space vector diagram, which consists of vectors of ZCMV, is fully explored by properly depicting the base voltage vectors and their corresponding active switching vectors. The switching patterns are limited to those of three switching states each of which is symmetrically distributed. Based on the PWM process simplified to that of a two-level inverter with three allowable switching states and the degree of freedom existing in the switching states arrangement, a novel carrier-based pulsewidth-modulated (PWM) method with optimized output current ripple is proposed. Compared to the existing PWM methods which utilize the same kind of switching patterns, the proposed PWM method has reduced considerably the rms current ripple and total harmonic distortion (THD) of the output current in a wide region of the modulation index. The effectiveness of the proposed method is validated by both simulation and experimental results. [ABSTRACT FROM AUTHOR]

In this paper, the concept of a modulated-ramp pulse-width modulation (PWM) generator is presented. The specific nonlinear behavior of this generator enables an exact linear control-to-output static conversion characteristic of DC-DC switching converters, such as the boost (step-up), buck/boost, Ćuk, or SEPIC, operating in continuous conduction mode. The resulting linearization leads to a significant improvement of the control accuracy and simplification of the converters, operating mainly in the open-loop architecture. In this paper, the concept of the modulated-ramp PWM generator is described, followed by a detailed steady-state and small-signal AC analysis. The key aspects for practical implementation are also highlighted. All results and benefits of the modulated-ramp PWM generator are demonstrated here on the boost converter power stage. [ABSTRACT FROM AUTHOR]

A family of isolated buck–boost dc/dc converter for wide input-voltage range is proposed in this paper, and the full-bridge (FB) boost converter, being one of the typical topologies, is analyzed. Due to the existence of the resonant inductor (including the leakage inductor), the FB-boost converter can only adopt the two-edge-modulation (TEM) scheme with the FB cell being leading-edge modulated and the boost cell being trailing-edge modulated to minimize the inductor current ripple over the input-voltage range, and a phase-shift-control-scheme-based TEM with the use of the market available controller IC such as UC3895 is proposed, which realizes phase-shifted control for the FB cell to achieve zero-voltage switching. In order to improve the reliability and efficiency of the FB-boost converter, a three-mode dual-frequency control scheme is proposed, in which the FB-boost converter operates in boost, FB-boost and FB modes in low, medium and high input voltage regions, respectively, and for which the expression of the inductor current ripple is derived in this paper. As the input voltage in the FB-boost mode is close to the output voltage, the inductor current ripple in this mode is much smaller than that in the other modes, and the switching frequency of the boost cell in this mode can be lowered to one-(2N+1)th of the preset switching frequency to reduce the switching loss, and hence, to improve the efficiency. A 250–500 V input, 360 V output, and 6 kW rated power prototype is fabricated to verify the effectiveness of the design and control method. The average efficiency over the input-voltage range is 96.5%, and the highest efficiency attained is 97.2%. [ABSTRACT FROM AUTHOR]

This paper discusses the control and design of the 6.6-kV back-to-back (BTB) system combining bidirectional isolated dc/dc converters and modular multilevel cascade pulsewidth modulation (PWM) converters. The system consists of multiple converter cells connected in cascade per phase at both front ends. Each converter cell consists of a bidirectional isolated medium-frequency dc/dc converter and two voltage-source H-bridge (single-phase full-bridge) PWM converters. Extremely low-voltage steps bring a significant reduction in harmonics and electromagnetic interference emissions to the BTB system. This paper designs, constructs, and tests a single-phase downscaled BTB system rated at 120 V and 3.3 kW to verify the viability and effectiveness, leading to the actual system. [ABSTRACT FROM AUTHOR]

This paper presents a single-phase power factor corrector based on a tapped-inductor buck–boost converter. This paper suggests simplified models of the power stage under current-mode control and derives small-signal transfer functions of both the current and voltage control loops. Design rules for implementation of the proposed power factor corrector (PFC) are also suggested. The proposed PFC features low dc bus voltage, arbitrary lower than the peak line voltage. The proposed PFC is suitable for applications in computers and communications, where dc isolation can be provided by the downstream dc/dc converters. Simulation and experimental results are also reported and stand in good agreement with theoretical expectations. [ABSTRACT FROM AUTHOR]

This paper proposes a new circuit topology for a multilevel pulse width modulation (PWM) rectifier. The proposed method forms a new circuit by combining a diode clamp-type topology with a flying capacitor-type topology. The proposed circuit uses only 12 switches, despite the use of a five-level three-phase PWM rectifier. Further, the proposed circuit can obtain good performance, same as a conventional multilevel circuit. This paper describes about the features of the proposed topology; the control strategy and the loss analysis that is estimated by a circuit simulator. In addition, the basic operation of the proposed method is confirmed by simulation and experimental results. The proposed converter achieved total harmonic distortion of 3.4% for the input current and efficiency of 97.4% for a 1 kW class experimental setup. [ABSTRACT FROM AUTHOR]

In the last decade, many methods for control of three-phase boost-type pulsewidth modulation (PWM) rectifier under unbalanced input voltage conditions have been studied and presented. These methods use the sequential components of input voltages, pole voltages, and input currents of the rectifier to analyze and control the instantaneous powers, of which dual (positive-sequence and negative-sequence rotating) frame control is the most common structure. Anyway, this paper analyzes the instantaneous powers of the PWM rectifier in two-phase stationary frame. Based on this analysis, the input-power-control, input-output-power-control, and output-power-control methods for PWM rectifier under unbalanced voltage conditions are proposed in single stationary frame. Compared with the existing methods, simplicity may be the major advantage of the method in this paper. Rotating transformation and phase detection of the input voltages are both eliminated. Moreover, sequential component extraction of the control variables is also not necessary, leading to much reduced time delay to the control system. Experimental results on a 9-kVA PWM rectifier show validity and effectiveness of the proposed methods. [ABSTRACT FROM PUBLISHER]

The modeling, modulation, and control of the three-phase four-switch (TPFS) PWM rectifier are investigated in this paper. Three space vector pulse width modulation methods using different equivalent zero vectors are developed, where sector identification and the trigonometric function are not required. Then, the high-frequency model for the current ripple analysis is proposed, and the effects of three SVM approaches on the ac current ripple are investigated. According to the analytical results, the method introducing the smallest current ripple is selected. With the optimized SVM approach, a control-oriented model, considering the capacitor voltage oscillation and deviation, is built in the dq synchronous frame to facilitate the controller design. Furthermore, a control strategy implementing the proportional controller is developed to eliminate the capacitor voltage deviation. Meanwhile, the dual-loop control of the TPFS is not affected by the proposed strategy as the capacitor voltage deviation is eliminated. Finally, a novel linear modulation index function is defined to reject the low-frequency harmonic current introduced by the overmodulation. Experimental results demonstrate that excellent current performance is achieved with comprehensive considerations of the modeling, modulation, and control strategy. [ABSTRACT FROM AUTHOR]

When faced with distorted grid voltage, more harmonics will appear in the output currents of the grid-connected inverters. The grid-voltage feedforward strategy, as the most direct solution to compensate the harmonics, however, is seriously affected by the errors in the grid-voltage feedforward loop, such as delays. This issue is more significant for high-power inverters, where the switching frequency is relatively low (< 5 kHz), and the grid-interface inductance is small (< 0.5 mH). The errors mainly include the signal distortion caused by the conditioning circuits, the control delay of the digital controller, and the zero-order hold (ZOH) characteristic of pulse width modulation (PWM). In this paper, several improvements have been made to reduce the signal distortion and compensate the delays. A second-order Butterworth low-pass filter in the conditioning circuit is carefully designed with the maximum flat magnitude response and the almost linear phase response to avoid distorting the measured grid voltage. Furthermore, based on the conventional repetitive predictor, an open-loop simplified repetitive predictor is proposed to compensate the delays in the grid-voltage feedforward loop. Three predictive steps are achieved by the open-loop simplified repetitive predictor to compensate the delays: one step for the delay caused by the conditioning circuit, the second step for the control delay of the digital controller, and the third step for the ZOH characteristic of PWM. The effectiveness of the improved grid-voltage feedforward strategy are experimentally validated on a 250-kVA solar power generation system, where the current harmonics are effectively attenuated. In addition, the inverter starting current is suppressed. [ABSTRACT FROM AUTHOR]

A pulse skipping modulation (PSM) technique improves the light load efficiency in a dc–dc converter by selectively skipping a few clock pulses. However, in existing PSM schemes, the number of charge and/or skipped cycles cannot be predefined. Therefore, it is difficult to predict the ripple parameters and ensure a stable periodic behavior. Further, it becomes difficult to further minimize power losses under light load conditions. This paper proposes a voltage-mode digital pulse skipping modulator which uses a digital pulse-width-modulator (PWM) as a building block, thus making it easy to operate the system in both PWM and PSM modes. Unlike in existing PSM schemes, the sequence and the count of charge and skip cycles can be fully prespecified in the proposed scheme, with the number of skip cycles optimally chosen to maximize the efficiency. Stability analysis is carried out using discrete-time modeling, which provides guidelines to ensure a stable periodic operation with predictable ripple parameters. Small-signal modeling and design of the proposed PSM scheme are discussed. A prototype buck converter was fabricated and tested. The proposed control scheme is implemented using an FPGA device, and the experimental results fully support the analytical predictions. [ABSTRACT FROM PUBLISHER]

The purpose of neutral-point voltage balancing algorithms in the three-level neutral-point clamped (3L-NPC) topology is to eliminate the voltage unbalance of top- and bottom-side dc-link voltages (neutral-point voltage). These algorithms are divided into dc unbalance and ac unbalance compensation methods. The dc unbalance causes distortion of output currents; therefore, this problem has to be solved. The ac unbalance implies that there is an ac ripple in the top- and bottom-side dc-link voltages. In applications using 3L-NPC topology, a large dc-link capacitor value is required to mitigate this ac unbalance problem. As a result, the size and the cost of applications become large and expensive. In this paper, a compensation method for mitigating the ac unbalance of the neutral-point voltage is proposed, which causes the dc-link capacitor value to be small, when a carrier-based pulse width modulation method is applied. The proposed method compensates the ac unbalance of the neutral-point voltage by adding an optimal compensation value to the reference duty signals. This compensation value is calculated simply by currents and reference duty signals. The calculation process of the optimal compensation value is discussed, and the effectiveness of the proposed method is verified with simulations and experiments. [ABSTRACT FROM PUBLISHER]

This paper proposes and evaluates an active voltage-balancing method for stacked multicell converters (SMCs) using phase-shifted pulse width modulation. The method is easy to implement and can be applied to SMCs with any number of levels. The proposed method balances the voltages of the capacitors by modifying the duty cycle of each switch of the SMC using a proportional controller. The direction of the output current and the crossed effect among the duty cycles of the switches is considered and used to improve capacitor voltage balance. The performance of the proposed voltage-balancing method is verified experimentally for different loads, such as linear and nonlinear loads, and under transient conditions. [ABSTRACT FROM PUBLISHER]

A capacitor voltage-balancing method for a nested neutral point clamped (NNPC) inverter is proposed in this paper. The NNPC inverter is a newly developed four-level voltage-source inverter for medium-voltage applications with properties such as operating over a wide range of voltages (2.4–7.2 kV) without the need for connecting power semiconductor in series and high-quality output voltage. The NNPC topology has two flying capacitors in each leg. In order to ensure that the inverter can operate normally and all switching devices share identical voltage stress, the voltage across each capacitor should be controlled and maintained at one-third of dc bus voltage. The proposed capacitor voltage-balancing method takes advantage of redundancy in phase switching states to control and balance flying capacitor voltages. Simple and effective logic tables are developed for the balancing control. The proposed method is easy to implement and needs very few computations. Moreover, the method is suitable for and easy to integrate with different pulse width modulation schemes. The effectiveness and feasibility of the proposed method is verified by simulation and experiment. [ABSTRACT FROM PUBLISHER]

This paper presents an adaptive-linear-neuron (ADALINE)-based dead-time compensation method for vector-controlled permanent-magnet synchronous motor drives. The proposed strategy is achieved by suppressing the sixth-order current harmonics in the dq-axes synchronous reference frame. Four ADALINEs are employed in the proposed algorithm. Two ADALINEs are used for estimating the sixth-order harmonic components of dq-axes currents and the other two are used for generating the dq-axes compensation voltages. The voltage compensators are self-tuned by minimizing the estimated current distortion by means of the least mean square algorithm. The proposed compensation algorithm does not require any additional hardware or complicated signal processing algorithms. Experimental results validating the proposed compensation method are also presented. [ABSTRACT FROM PUBLISHER]