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A boost converter with buck-store and boost-restore (BSBR) technique fabricated by 0.25 [micro]m CMOS BCD process can provide different supply voltages to drive series red, green, and blue LEDs in sequence for reducing the power consumption on the constant current generator. The proposed technique not only stores and restores extra energy during the transient time of the reference tracking response to improve the efficiency but also enhances the reference tracking response to greatly reduce load transition time. Experimental results show that the period of reference tracking response can be improved. When the load current is 100 mA, the periods of reference down-tracking and up-tracking are smaller than 10 and 20 [micro]s, respectively. Furthermore, this technique can also provide a regulated voltage to drive the subblock implemented in the liquid crystal display system. The maximum efficiency of charge recycling is up to 94%, and the maximum efficiency of this boost converter is 94.5%. Experimental results demonstrate fast and efficient reference tracking performance is achieved by the proposed BSBR technique. Index Terms--Charge recycling, dc--dc converter, field color sequential (FCS), reference tracking.

This paper presents a new adaptive window control (AWC) technique to adjust the hysteresis window to reduce the output ripple at heavy loads and keep the switching frequency higher than the acoustic frequency at light loads. Therefore, the driving capability and the power conversion efficiency of the hysteresis converter are improved at heavy loads. Besides, a new class AB current sensing circuit is also proposed to provide fast and accurate current sensing signal for achieving fast hysteresis window adjustment. Experimental results show that the proposed AWC technique not only reduces the output ripple smaller than 12 mV when load current is 800 mA to improve the power conversion efficiency but also keeps the switching frequency higher than acoustic frequency at light loads to avoid undesired noise. Index Terms--Adaptive window control, hysteresis converter, output ripple.

Power management is implemented in a multiple-input--single-output system in this paper. Actually, the design of the switching loss calculation circuit in a dynamic droop system (DDS) can decide the optimum driving solution according to the loading condition, i.e., more than one input source is disabled to reduce the switching loss at light loads. On the other hand, multiple-input sources are preferred to reduce the conduction loss at heavy loads. In other words, DDS with power management can achieve low drop output voltage and high efficiency over a wide load range. The positive/negative-compensated technique enhances the performance of the output voltage stability. Experimental results show that efficiency can be improved approximately 12% at light loads when two input sources are regulated at the switching frequency equal to 5 MHz. Simultaneously, good current sharing is also guaranteed. Index Terms--Dynamic droop, multiple input, positive/negative compensated (PNC), single output, switching loss calculation (SLC).

This paper proposes a low-ripple and dual-phase charge pump circuit regulated by switched-capacitor-based bandgap reference. Due to design of a buffer stage, a system can have better bandwidth and phase margin, and thus, the transient response and driving capability can be improved. Besides, the dual-phase control can reduce the output voltage ripple by means of only one closed-loop regulation in order to improve the power conversion efficiency. Besides, the proposed automatic body switching (ABS) circuit can efficiently drive the bulk of the power p-type MOSFETs to avoid leakage and potential latch-up. Usually, the regulated charge pump circuit needs a bandgap reference circuit to provide a temperature-independent reference voltage. The switched-capacitor-based bandgap reference circuit is utilized to regulate the output voltage. This chip was fabricated by Taiwan Semiconductor Manufacturing Company (TSMC) 0.35 [micro]m 3.3 V/5 V 2P4M CMOS technology. The input voltage range varies from 2.9 to 5.5 V, and the output voltage is regulated at 5 V. Experimental results demonstrate that the charge pump can provide 48 mA maximum load current without any oscillation problems. Index Terms--Bandgap reference, charge pump, dual-phase power stage, fast transient response, output ripple, system-on-chip (SoC).

An adaptive reference control (ARC) technique is proposed for minimizing overshoot/undershoot voltage and settling time of low-dropout regulators. Linear operation provided by the ARC technique can dynamically and smoothly adjust the reference voltage so as to increase the slew rate of error amplifier thus forcing the output voltage back to its steady-state value rapidly. The amount of transient revision is proportional to transient state output voltage variation and load condition. In addition, a dynamic push-pull technique is used to enhance transient response. Experimental results demonstrate that the undershoot voltage, settling time, and load regulation are improved by 31%, 68.5 %, and 70 %, respectively, when load current changes between 1 and 100 mA. Index Terms--Analog ICs, CMOS analog ICs, dc-dc power conversion, MOSFET ICs.

This paper proposes an adaptive pole-zero position (APZP) technique to achieve excellent transient response of dc-dc converters. The APZP technique triggers the two-step nonlinear control mechanism to speed up the transient response at the beginning of load variations. Before the output voltage is regulated back to its voltage level, the APZP technique merely functions as a linear control method to regulate output voltage in order to ensure the stability of the system. Fast transient response time, low output ripples, and stable transient operation are achieved at the same time by the proposed APZP technique. Experimental results in the UMC 0.18-[micro]m process show that the transient undershoot/overshoot voltage and the recovery time do not exceed 48 mV and 10 [micro]s, respectively. Compared with conventional design without any fast transient technique, the performances of overshoot voltage and recovery time are enhanced by 37.2% and 77.8%. With the APZP technique, the performance of dc-dc converters is improved significantly. Index Terms--Adaptive frequency control, current-mode dc-dc converter, fast transient response, load transient, on-chip compensation.

This paper proposes an advanced Q-reduction technique of pole-splitting compensations for low dropout (LDO) regulator. The output pole is load dependent and may cause the scenario of complex poles when load current changes. LDO regulators may oscillate because high-Q incurs the less gain and phase margins. The reasons of causing complex poles depend on the design methodology. For the design of capacitor-free LDO regulator, high-Q issue happens when load current changes from heavy to light. Recent literature provides a method to alleviate the high-Q problem. However, large dropout voltage in case of suddenly large loads forces designers to include a small load capacitor as an indispensable component for supplying system-on-chip (SoC) systems. Different to the case of capacitor-free LDO regulators, high-Q issue happens when load current changes from light to heavy. According to our proposed power MOSFET array, the high-Q problem can be alleviated and prevent LDO regulators from oscillating when load changes. Experimental results promise the stability and show the improvement of load and line regulations. Index Terms--Capacitor-free, complex pole, low-dropout regulator (LDO), power MOSFET array, Q-reduction.

Single-ended and two-ended bidirectional capacitor multipliers for providing on-chip compensation, soft-start, and fast transient mechanisms are proposed in this paper. The bidirectional current mode capacitor multiplier technique can effectively move the crossover frequency toward to the origin in the start-up period for a smoothly rising of the output voltage. Besides, the small time constant is set by the fast transient control circuit in order to get a higher crossover frequency. Thus, the output voltage can be regulated to its stable value as fast as it can when large load current changes. A test chip fabricated by the Taiwan Semiconductor Manufacturing Corporation (TSMC) 0.35-[micro]m process verifies the correctness of the bidirectional current mode capacitor multiplier technique. Experimental results demonstrate the transient speed by our proposed technique is faster than that by conventional control by about 2 times, and there is only about 76% dropout voltage of the conventional design with off-chip compensation. The proposed circuits consume more quiescent current about 10 [micro]A in single-ended capacitor multiplier and 20 [micro]A in two-ended capacitor multiplier. With the proposed bidirectional current mode capacitor multiplier technique, the performance of dc-dc converters is improved significantly and the external pins and footprint area are minimized. Index Terms--Capacitor multiplier, compensator, current mode, dc-dc converter, on-chip compensation.

Constant-on-time (COT) control with an additional current feedback path in conventional buck converters can remove the need of large equivalent series resistance (ESR) at the output capacitor but it induces degraded output voltage regulation accuracy and slow transient response owing to opposite reaction between the output voltage and the additional current feedback information. Therefore, this paper proposes the pseudowave tracking (PWT) technique to reduce the load-dependent dc offset voltage of output load regulation while keeping the fast transient response similar to conventional COT buck converter with large ESR. The PWT technique further improves the transient response instantly by extending on-time and off-time periods during light-to-heavy and heavy-to-light load changes, respectively. The test chip fabricated in 28 nm CMOS process has demonstrated the improvement of offset voltage from 42 to 4 mV, while the transient response can be improved to 4 and 5 μs with load changes from 0.3 to 1.7 A and vice versa, respectively. [ABSTRACT FROM PUBLISHER]