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Magnetic integration of the passive transformer and inductor is a key to realizing a high-performance LLC resonant converter. With the advent of wide-bandgap devices, magnetics must cope with the increased switching frequency to maintain high efficiency and push for higher power density. This article presents a novel five-leg magnetic core structure that uses a printed circuit board to integrate a matrix of four transformers and a resonant inductor. The proposed design allows for controllable leakage inductance within the footprint of the original matrix transformer, resulting in excellent power density for the magnetics. The five-leg core structure operates by relocating the center-tapped secondary winding while maintaining the primary winding unchanged from the original transformer. This obviates the need for a stand-alone, lossy resonant inductor and offers a minimal increase in winding loss. The proposed magnetic structure is utilized to implement a regulated CLL resonant converter, demonstrated on a 3-kW 400 V/48 V dc–dc converter intended for data center applications. The converter, including magnetics, is implemented on a four-layer printed circuit board and offers a power density of $\text{550}\,\text{W}/\text{in}^{3}$ and a peak efficiency of $97.3 \%$.

Multiphase voltage regulators (VRs) that power multicore processors must have a fast load transient response and good light-load efficiency. Multiphase current-mode constant on-time (COT) control based on pulse distribution method eliminates the phase-locked loops and interleaves the phases through a simple phase manager. Hence, power management industries widely use this control to meet VR requirements with reduced complexity. To handle large load currents, the VR's phase count continues to increase. With increased phase count, these converters operate with overlapping phases within the practical duty cycle range. This article finds that the total current exhibits variable on-time and off-time modulation under a small sinusoidal perturbation in the phase-overlapping region. Hence, the small-signal model of the single-phase COT control does not apply in this region. Therefore, Part I of this article presents a general small-signal model of this control applicable to the whole duty cycle range using the describing function method. Also, the proposed model is verified using SIMPLIS simulations and experimental results from a six-phase COT-controlled buck platform. Part II of this article identifies that the total current loop of this control will become unstable with overlapping phases and derives the critical conditions for stability using the model from Part I.

The proliferation of renewable generations significantly in power system increases the severity and possibility of subsynchronous oscillations (SSOs) recently. Monitoring SSOs is critical for setting up control strategies and mitigating SSOs effectively. In many SSO events, the oscillation frequency and magnitude are time-varying, which brings great challenges to SSO monitoring. This article proposes an adaptive-reset extended Kalman filter (AREKF) method for accurate estimation of SSO modes. Two improvements are made to the EKF method. The first one is establishing a four-state SSO signal model for the EKF algorithm to track damping factors of SSO modes. The second one is developing an adaptive-reset method to make the EKF algorithm capable of handling the time-varying SSOs by resetting the covariance matrix adaptively. The threshold in the adaptive-reset criterion is automatically tuned with the M2M4 estimator. The performance of the AREKF method is demonstrated under various conditions and compared with that of conventional KF-based and phase-locked loop-based methods. Simulation results validate the effectiveness and robustness of the proposed method as well as its superiority over conventional approaches. Real-time experiment results demonstrated the effectiveness of the proposed method in practical applications.

This letter proposes a fast overcurrent protection integrated circuit (IC) for silicon carbide (SiC) mosfet based on current detection. With the proposed protection IC, the voltage between the Kelvin source and power source of SiC mosfet is sensed through an off-chip resistance. Thus, a detection voltage proportional to the drain current of SiC mosfet is obtained. Comparing the detection voltage to on-chip reference voltages, the proposed protection IC can provide both overload (OL) and short circuit (SC) protections for SiC mosfet. Moreover, a soft turn-off circuit is integrated into the protection IC. The proposed protection IC is implemented in a 0.5-$\mu$m bipolar-CMOS-DMOS process and the die size is about 2 mm$^{2}$. With the 1200 V/80 m$\Omega$ SiC mosfet, the proposed protection IC is verified on our test bench. With the proposed protection IC, the response time of the SC protection is 24 ns and the SC duration time of the SiC mosfet is 43 ns. Owing to the soft turn-off circuit of the protection IC, the drain voltage overshoot of the SiC mosfet is lower than 90 V during the OL and SC protections.

Enabled by the adoption of wide-bandgap power devices, converters in many applications continue to push switching frequency and power density. These trends have the unintentional effect of strengthening parasitic inductive and capacitive couplings between different areas of the power converter. If not properly addressed, these parasitic near-field couplings may increase the converter's conducted electromagnetic interference (EMI). This article investigates the impact of parasitic near-field couplings on conducted common-mode (CM) noise in a buck converter with the EMI filter. Magnetic and electric coupling mechanisms are studied using near-field measurements. A CM model with capacitive couplings is developed and shown to accurately predict the CM noise spectrum under two different test conditions. The model is analyzed and two critical capacitive couplings are identified. Finally, shielding techniques are demonstrated to reduce CM noise up to 35 dB, and a novel shielded-windings PCB inductor structure is proposed.

The design challenges to power high-performance processors require the voltage regulator to be smaller, faster, and more efficient. Compared with the noncoupled-inductor-based solution, a multiphase coupled inductor helps a buck converter achieve a smaller current ripple and a faster transient response. Among different coupled inductor structures, a hybrid-coupled inductor (HCL) is a promising candidate. Based on the proposed equivalent circuit model, this article first analyzes a conventional HCL in detail to identify its benefits and limitations. Then, an improved HCL structure with a five-leg magnetic core structure is proposed. By splitting the magnetic flux into different areas of the core plate, a thinner plate can be applied, and the inductor size is greatly reduced. Furthermore, the coupling can be flexibly adjusted by controlling the flux in different core legs. The extra inductor used to adjust the coupling in the conventional solution is eliminated in the proposed structure. With all these benefits, the proposed HCL structure can achieve a 40% inductor size reduction while maintaining a small current ripple and fast transient response, as compared with the conventional solution.

Processor core voltage regulators (VRs) widely use pulse distributor-based multiphase current-mode constant on-time (COT) control to improve light-load performance, achieve fast transient response, and simplify phase interleaving. Part I of this article presented a small-signal model of this control for the whole duty cycle range. Part II of this article finds that the total current loop of an $N$-phase COT-controlled VR becomes unstable for duty cycle $D>1/N$ without a sufficient external ramp. Also, the minimum ramp (or critical ramp) required to preserve stability varies with the number of overlapping phases. Hence, this article derives the critical ramp in each phase overlapping region using the model from Part I. The unstable closed-loop poles of the total current loop in phase-overlapping regions cause this issue. Hence, we first identified the characteristic equation that introduces these poles. Then, we rearranged it to formulate a theoretical loop gain and derived a stability condition using the discrete-time Nyquist criterion. Finally, we evaluated this condition to determine the exact critical ramp expressions up to four overlapping phases and an analytical approximation for the same beyond four overlapping phases. The critical stability limits are verified using SIMPLIS simulations and experimental results from a six-phase COT-controlled buck platform.

Output capacitance (COSS) loss (EDISS) is produced when the COSS of a power device is charged and discharged, which ideally should be a lossless process. This loss was recently revealed to be a crucial concern for GaN high electron mobility transistors (HEMTs) in high-frequency soft-switching applications. Among various GaN devices, the composite-type, cascode GaN HEMT was reported to show the largest EDISS with a voltage dependence distinct from discrete GaN HEMTs. However, the physical origins of the EDISS in cascode GaN HEMTs remain unclear. This article fills this gap by identifying three loss components and, for the first time, experimentally quantifying them in the multi-MHz resonant switching. These loss components include: a) the avalanche loss of Si mosfet; b) the intrinsic EDISS of GaN HEMT; and c) the Si avalanche-induced GaN turn-on loss. The last component was found to dominate EDISS at high voltage. By eliminating the Si avalanche and the associated loss components (a) and (c), the EDISS of cascode GaN HEMTs can be reduced by up to 75% at the price of an increase in output charge and switching transition time. These results provide new physical insights and practical guidelines to trim the soft-switching loss of cascode GaN HEMTs in high-frequency applications.

To date, $LLC$ resonant converters have been deployed in many applications for improved efficiency, density, and reliability. With the introduction of wide-bandgap devices coupled with the soft switching feature, the switching frequency can be extended beyond megahertz. With the significant increase in operating frequency, complicated magnetic components can be broken down into a cellular structure, each with a few number of turns. They can be easily implemented using four to six layers of printed circuit board windings. Moreover, integrating the cellular cores using flux cancellation can further improve the power density. The proposed integrated magnetics can be automated in the manufacturing process. With the recently developed high-frequency core material, phenomena referred to as the dimensional effects on core loss are observed. The dimensional effects are discussed in the literature when using an unusually large core structure; however, at high excitation frequencies, it can be observed more frequently, particularly with integrated magnetic components. In this article, we give an overview of the dimensional effects on core loss, namely flux crowding, dimensional resonance, and eddy loss, with the latest being a dominant factor in the 1-MHz transformer loss. We also introduce a practical method for the characterization of the dimensional effects to help engineers better design their high-frequency converter. This includes measuring the ferrite material characteristics and evaluating the dimensional effects using finite-element analysis. Finally, a case study of 1-MHz 400-to-48 V converter design is presented, showing superiority in both power density and efficiency metrics compared to other reported literature from the same category. This shows the importance of including the dimensional effects and, specifically, the core eddy loss in the design procedure.

In recent years, there has been a considerable upswing in power usage by data centers. As a result, the 48-V power architecture has become increasingly favored due to its high efficiency. However, the cost of efficient power supplies remains challenging due to their complicated magnetic designs. The search for efficient and cost-effective power supplies continues. This article focuses on the implementation of the dc–dc stage of the power supply unit for the 48-V data center bus architecture. In this article, we present a design process for a high-efficiency high-power-density 3-kW 400-to-48-V $LLC$ converter for use in data centers. Through the optimization of the matrix transformer's geometry, turn number, and resonant frequency, we achieve superior efficiency and power density compared to state-of-the-art designs. To address challenges with the printed circuit board (PCB)-based inductors, we propose the use of a resonant matrix inductor, which reduces the number of stacked PCB layers, simplifies the winding implementation, and lowers the ac loss. By integrating the matrix inductor with the matrix transformer, we create a modular and scalable magnetic structure suitable for a wide range of voltages and currents. We also introduce electromagnetic interference shielding for the matrix transformer with a full-bridge rectifier, resulting in an 18-dB reduction in common-mode noise. The prototype achieved a peak efficiency of 98.8% and a power density of 600 W/in$^{3}$, demonstrating the effectiveness of the proposed design.