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Silicon carbide (SiC) power transistors have started gaining significant importance in various application areas of power electronics. During the last decade, SiC power transistors were counted not only as a potential, but also more importantly as an alternative to silicon counterparts in applications where high efficiency, high switching frequencies, and operation at elevated temperatures are targeted. Various SiC device designs have been proposed and excessive investigations in terms of simulation and experimental studies have shown their advantageous performance compared to silicon technology. On a system-level, however, the design of gate and base drivers for SiC power transistors is very challenging. In particular, a sophisticated driver design is not only associated with properly switching the transistor and decreasing the switching power losses, but also it must incorporate protection features, as well as comply with the electromagnetic compatibility. This paper shows an overview of the gate and base drivers for SiC power transistors which have been proposed by several highly qualified scientists. In particular, the basic operating principle of each driver along with their applicability and drawbacks are presented. For this overview, the three most successful SiC power transistors are considered: junction-field-effect transistors, bipolar-junction transistors, and metal-oxide-semiconductor field-effect transistors. Last but not least, future challenges on gate and base drivers design are also presented. [ABSTRACT FROM AUTHOR]

Operation of parallel-connected 4H-SiC vertical junction field effect transistors (VJFETs) from SemiSouth is modeled using numerical simulations and experimentally verified. The unbalanced current waveforms of parallel-connected VJFETs are investigated with respect to the spread in the critical parameters of the device structure and to the influence of the parasitic inductances in the measurement circuit. The device structures are reconstructed based on scanning electron microscopy (SEM) analysis, electrical characterization, and device simulations. The doping concentration and profile depth of a p-grid formed by angular implantation are studied as main contributors that influence the variation of the on-state characteristics, and the threshold voltage of the experimental devices. It has been shown elsewhere that similar differences in p-grid also lead to differences in gate-source breakdown voltage. The switching performance of the parallel-connected JFETs is measured using single and double gate drivers in a double-pulse test and compared with simulations. The switched current and voltage waveforms from measurements are reproduced in simulation by introducing the parasitics. From the analysis, it is found that reasonable differences in doping levels and profiles of the p-grid give rise to significant differences in device parameters. However, even with these parameter differences and circuit asymmetries, it is possible to successfully operate parallel-connected VJFETs of this type. [ABSTRACT FROM AUTHOR]