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In this article, a high efficiency and high power density Regulated dc Transformer (RDCX) is proposed for on-board charger (OBC). In this circuit, high input and output voltages are undertaken by series connected low-voltage devices. Owing to the low new figure of merit (NFoM, Rdson×Coss)(Il-Jung et al., 1995), (Wu and Shi, 2020) characteristic of low-voltage devices, the conduction loss of switches can be reduced. Mathematical modeling and verification are also carried out. In addition, by applying cascaded buck as the regulation part of RDCX, the volt-second of buck inductor can be reduced compared with the traditional two-level buck circuit. As a result, the size of the inductor can be reduced. Furthermore, since all dc buses of the cascaded buck converter are from the rectifiers whose windings are coupled to the same transformer, those bus voltages can be naturally balanced. A 2.3 kW prototype based on 60V device with 388–412 V input and 250–450 V output voltage range is built up to verify the analysis, achieving 98% peak efficiency and 910 W/in3 power density. [ABSTRACT FROM AUTHOR]

This letter proposes a multiagent soft actor-critic (MASAC) enabled multiagent deep reinforcement learning (MADRL) algorithm for output current sharing of the input-series output-parallel dual active bridge converter. The modular converter is partitioned into different submodules, which are treated as DRL agents of Markov games. Furthermore, all agents are executed decentralized to provide online control decisions after collaborative training. The proposed MASAC algorithm verified in a 150 V/50 V hardware prototype shows optimal dynamic performance. [ABSTRACT FROM AUTHOR]

Microgrids relying on cooperative control are supported by communications, which are highly vulnerable to cyberattacks. A significant amount of research is already carried out on the detection and mitigation of cyberattacks to secure the operation of dc microgrids. Although cyberattacks are fully capable of causing cascaded converter outages leading to full/partial system blackouts, disturbing the system stability can also be a viable target by the adversaries, which has been overlooked so far. Hence, this article focuses on addressing the instability caused by stealth cyberattacks, which can easily bypass the well-defined observability tests. In addition, this article also introduces a novel adaptive stabilization method to eliminate the unstable modes due to cyberattacks, which has been designed considering a previously defined cyberattack detection metric as an input. To investigate its feasibility, a detailed model of a stable dc microgrid is first developed. Then, considering stealth cyberattack as a nonlinear element, the describing function-based method is used to investigate system stability under attack conditions. Finally, theoretical analysis, simulation, and experimental results under various scenarios are presented to verify the effectiveness of the proposed stabilization scheme. [ABSTRACT FROM AUTHOR]

There is a certain amount of current harmonics in interior permanent magnet synchronous motor. In order to accurately control the current harmonic, this article focuses on three aspects: establishing current harmonic calculation model, extracting current harmonic, and designing current harmonic regulator. A current harmonic calculation model, which considers the effect of voltage harmonics induced by current controllers and digital control delay on the initial phase angle of voltage harmonics, is established for the first time. With the help of multiple synchronous rotating frame transformation, a current harmonic extraction method more suitable for motor drive field, which aims to extract the current harmonic characteristics of d-axis and q-axis currents, is proposed. On this basis, the controlled quantity and control quantity are unified in d–q coordinate frame for analyzing the coupling relationship of current harmonic characteristics. And then a PI current harmonic regulator, including current harmonic decoupling and voltage harmonic initial phase angle compensation, is constructed, so as to realize the effective control of current harmonics. Finally, the effectiveness and superiority of the proposed method are verified by simulation and experiments. [ABSTRACT FROM AUTHOR]

The overmodulation scheme plays an essential role in the dynamic performance of the current regulation under voltage limitation. This article analyses how the nonlinearity of the voltage hexagon affects dynamic overmodulation. Most dynamic overmodulation schemes had considered the voltage hexagon as the limit of the output voltage to maximize the voltage utilization. However, these schemes do not show uniform dynamic performance according to the rotor position on the voltage hexagon. To overcome this limitation, this article proposes an overmodulation scheme that is robust against the rotor position variation. The computer simulation and experimental results verify that the proposed method has the consistent performance regardless of the rotor position with less d-axis current overshoot keeping the fast dynamics. [ABSTRACT FROM AUTHOR]

A digital low-dropout (DLDO) regulator is described which is controlled by voltage-controlled oscillator (VCO) based feedback loop. There are two VCOs in the control loop whose frequencies are controlled by the output voltage and reference level, respectively. By comparing the phase between the output clocks of the two VCOs and modulating the number of enabled power transistors and their on-times, the output voltage is regulated. The proposed VCO-based control is a hybrid of digital and analog control schemes because the number of enabled power transistors is controlled in discrete step while the on-time is modulated continuously. In order to improve the transient speed, transient detector is employed in the DLDO regulator. The DLDO regulator with the proposed VCO-based control has been implemented in a 65-nm CMOS process. The DLDO regulator can provide the output from 0.5 to 1.1 V from the input ranging from 0.9 to 1.2 V. The load transient time is smaller than 90 ns for both step-up and step-down changes of load current. The peak current efficiency is 99.3%. [ABSTRACT FROM AUTHOR]

This article presents a 48–1 V merged-two-stage hybrid-switched-capacitor converter with a linear extendable group operated point-of-load (LEGO-PoL) architecture for ultrahigh-current microprocessors, featuring 3-D stacked packaging and coupled inductors for miniaturized size, fast speed, and vertical power delivery. The architecture is highly modular and scalable. The switched-capacitor circuits are connected in series on the input side to split the high input voltage into multiple stacked voltage domains. The multiphase buck circuits are connected in parallel to distribute the high output current into multiple parallel current paths. It leverages the advantages of switched-capacitor circuits and multiphase buck circuits to achieve soft charging, current sharing, and voltage balancing. The inductors of the multiphase buck converters are used as current sources to soft-charge and soft-switch the switched-capacitor circuits, and the switched-capacitor circuits are utilized to ensure current sharing among the multiphase buck circuits. A 780-A vertical stacked CPU voltage regulator with a peak efficiency of 91.1% and a full load efficiency of 79.2% at an output voltage of 1 V with liquid cooling is built and tested. The switched capacitor circuits operate at 286 kHz and the buck circuits operate at 1 MHz. It regulates output voltage between 0.8 and 1.5 V through the entire 780-A current range. This is the first demonstration of a 48–1 V CPU voltage regulator to achieve over 1-A/mm $^\text{2}$ current density and the first to achieve 1000-W/in $^3$ power density. [ABSTRACT FROM AUTHOR]

This article presents a merged two-stage 48-V-to-1-V point-of-load (PoL) architecture with a 24-V virtual intermediate bus (VIB) for CPU voltage regulator applications. The VIB-PoL architecture includes two power conversion stages linked by a 24-V VIB with a significant voltage ripple. The first stage is a 2:1 interleaved charge pump, which converts 48 to 24 V. The second stage comprises multiple interleaved four-level series-capacitor buck modules with coupled inductors, converting 24 V to regulated 1 V with an equivalent voltage conversion ratio of 6:1. The VIB-PoL architecture achieves high efficiency and high power density by reducing the power conversion stress of both stages and eliminating the intermediate bus capacitors. A 48-V-to-1-V 640-A CPU voltage regulator with a peak power stage efficiency of 95.2% (93.3%, including gate driver loss), a full-load efficiency of 84.4% (83.1%, including gate driver loss), and a power density of 463 W/in $^3$ (at 1-V output with liquid cooling) is built and tested to demonstrate the VIB-PoL architecture. [ABSTRACT FROM AUTHOR]

In a practical alternating current (ac) machine drive system, a zero-order hold equivalent discrete-time machine model motivates the development of a direct discrete-time current regulator structure. However, it is complicated to establish the direct discrete-time current regulator for asymmetric machine 1 Asymmetric machine denotes a ac salient machine in this article, whereas the symmetric machine denotes a ac non-salient machine. model due to the involvement of complex matrix exponential related to unequal machine inductance parameters. In order to overcome this barrier, a novel direct discrete-time current regulator based on the flux model is proposed, where a modified ac machine model considering delay compensation is developed and a new feed-forward voltage compensation is designed to eliminate the matrix exponential. In addition, a discrete-time flux observer is proposed and can work in the proposed current regulator to suppress the adverse one-step delay effect on the feed-forward voltage compensation and current regulator. The theoretical analysis has shown that the proposed discrete-time current regulator and flux observer have good parameter robustness and stability. Also, the experimental verification is performed on an ac machine drive test rig. [ABSTRACT FROM AUTHOR]

Flux-switching permanent magnet (FSPM) machines can provide high torque density, strong flux-weakening capability, and high reliability, which makes these machines attractive in electrical drive systems. FSPM machines always employ different control methods, such as the vector control (VC) and direct torque control (DTC) methods. These methods exhibit different electromagnetic torque dynamic performances; hence, the dynamic performances of their rotor speeds are different. However,the proportional integral (PI) controllers of the speed loop in these methods are linear regulators, which hardly guarantee the optimal dynamic performance of the rotor speed. This causes the rotor speed to have several adjustments, overshoots, and a relatively long recovery time during the response to a sudden load change. Therefore, to achieve the optimal dynamic trajectory of rotor speed and maintain the excellent performance of the steady-state simultaneously, a torque-current (Iq) integral balance (IQIB) method, which can eliminate the restriction of the PI controllers on the dynamic performance of the rotor speed, is investigated for the VC system of FSPM machines. In the dynamic process, a group of optimal switch vectors is obtained to achieve the shortest recovery time and the minimum number of adjustments for the rotor speed without overshoot, thereby achieving an optimal dynamic performance for the system. Comparative experiments between the IQIB-based VC, VC, DTC, and improved DTC are conducted, and the accuracy and effectiveness of the proposed method are validated. [ABSTRACT FROM AUTHOR]

The article presents a new approach to positive and negative sequence current vector control of a grid-connected three-phase three-wire power electronic converter operating under grid voltage imbalance conditions. The concept utilizes the representation of unbalanced converter current in the new coordinates frame in which the current vector components are constant. The nonlinear trigonometric transformation of two-dimensional current vector components from the stationary frame to the new frame is found online depending on the reference current asymmetry. The presented concept of new coordinates utilization allows implementation of proportional-integral terms as current regulators without the use of resonant terms and without the use of the measured current symmetrical sequences decomposition. The article presents the theoretical approach, simulation results, as well as laboratory tests results. [ABSTRACT FROM AUTHOR]

Switching regulators improve power efficiency and reduce cost of electronic devices. Continued advances in the performance of components have outpaced the models used for their analysis and design. Physical limits of the parts and their arrangement introduce nonideal parasitic effects that can no longer be ignored. This article introduces an extensible frequency domain model of buck regulators that can capture parasitic effects of arbitrary complexity. Such models are derived for both continuous and discontinuous conduction modes of peak current mode controllers. The proposed models are shown to be accurate when compared to other methods, while having lower computational cost. Numerical optimization is applied to design systems using the increased complexity models. Cost functions are developed, and shown to produce improved designs when compared to existing published examples. Experimental measurement finds the models accurately predict the performance of implemented designs. Additional parasitic elements are added to the model, showing improved fit to measured results, demonstrating the extensibility and accuracy possible. [ABSTRACT FROM AUTHOR]

This article proposes a new duty-ratio regulation-based strategy to improve the torque performance for the direct torque control (DTC) of three-phase permanent magnet synchronous motors (PMSMs). The conventional DTC schemes utilize two hysteresis regulators that are hard to be tuned to satisfy proper torque performance for wide speed ranges because of the contrary change in the positive and the negative torque deviations of the converter's voltage vectors with the rotational speed variations. In contrast, the proposed method uses a duty-ratio regulator that considers the operating speed impact on the torque deviation of the active voltage vectors and avoids triggering those of them that produce high torque deviations, therefore reducing the torque ripple of the DTC system. Moreover, it proposes a virtual reference generator to mitigate the steady-state torque error. The proposed method provides enhanced torque control performance, meanwhile maintaining the main advantages of the conventional DTC techniques, including simple structure, fast transient response, and good robustness. The feasibility and effectiveness of the proposed strategy are verified through a detailed comparative assessment with the conventional DTC scheme and two existing duty regulation-based methods using experimental results obtained from a 0.75-kW PMSM drive system. [ABSTRACT FROM AUTHOR]

This article presents a cell-level differential power processing IC to maximize the power yield under partial shading and mismatch condition in series-connected single junction photovoltaic (PV) cells. A 3-MHz bidirectional buck–boost converter is employed to realize voltage equalization technique forcing the PV cells to constantly operate close to their maximum power points. A novel and simple low-power low-area analog control circuit is proposed to maintain the high system efficiency at low and high levels of mismatch by obviating the need for power hungry blocks such as analog to digital converters, digital to analog converters, op-amps, saw-tooth generator, and regulators. The voltage of adjacent PV cells is used to drive the high-side switches through bootstrap supplies eliminating the need for voltage regulators. The performance of the proposed IC, fabricated in 130 nm CMOS process, is validated through simulation and experimental results. The converter is capable of processing mismatch currents up to 4 A while the control circuitry consumes less than 40 mW and a system efficiency above 95% is achieved. [ABSTRACT FROM AUTHOR]

This article presents an adaptively biased output-capacitor-free low-dropout regulator that achieves high power supply rejection for wearable biomedical system-on-chips (SoCs). Adaptive biasing is implemented to achieve both fast transient responses and high power conversion efficiency, and the common-gate current feedback loop enhances the dc gain of the error amplifier by 10 dB. The proposed supply ripple subtraction reference buffer constitutes a reversed-phase power supply rejection (PSR) path that counteracts the increase in the output voltage due to the in-phase PSR path, and PSR is enhanced significantly in the range of 1 MHz. The proposed pole-tracking-compensation maintains sufficient phase margin over a wide load current range. Designed and fabricated in a 0.18  $\mu$ m CMOS process, the prototype silicon area is only 0.0113 mm $^2$. The total quiescent current is 8.6  $\mu$ A at no load current, and the maximum current efficiency is 98.8 $\%$ at full load current of 20 mA. [ABSTRACT FROM AUTHOR]

In the receiver-side (RX) of the wireless power transfer (WPT) system, the RX is composed of compensation capacitors, a rectifier stage, and a dc/dc stage. Among them, the compensation capacitors are an essential component to minimize reactive power. Also, the dc/dc stage is an inevitable component to supply a stable output to the battery. However, to meet these aforementioned unavoidable requirements, a large number of components are required in RX of the WPT system, which increases the overall system size and cost. To relieve these drawbacks, a self-compensated planar coil with integrated single-switch regulator for the WPT system is proposed in this letter. The proposed converter can remove the many number of compensation capacitors by utilizing the intrinsic capacitance between adjacent layers of the planar coil as a self-compensated factor. Moreover, by integrating a single-switch into the rectifier stage, it is possible to supply a stable output to the battery with only a single power stage and low cost. Besides, the proposed structure can obtain reduced switching loss by securing the soft-switching operation under the rated load condition. The effectiveness of the proposed structure is verified experimentally by a prototype under 150VDC input and 60 W/33 V output. [ABSTRACT FROM AUTHOR]

This letter proposes a passivity-based dual-loop vector voltage and current control method for grid-forming voltage-source converters (GFM-VSCs). A passive output impedance of GFM-VSC is guaranteed in both the voltage control mode and the current-limiting mode with a wide range of time delay. The frequency-domain analysis, simulation and experimental tests validate the effectiveness of the approach. [ABSTRACT FROM AUTHOR]

This article presents a fully integrated flipped voltage follower (FVF) based low-dropout (LDO) regulator with enhanced full-spectrum power supply rejection (PSR) and unity-gain bandwidth over 400MHz for noise-sensitive circuits. Following the study of three types of FVF LDO's PSR performances, we propose a novel FVF LDO with a low-gain fast loop-1 and a high-gain slow loop-2. In prior FVF LDOs, their PSRs are either full-spectrum, or not, but with low PSR at low frequency. In this article, we fully utilize both dc gains of loop-1 and loop-2 for the low-frequency PSR, while the high-frequency PSR remains unchanged. In addition, we use dynamic compensation to push the loop-2's UGB to higher frequency for a better PSR bandwidth. This work, fabricated in 65 nm complementary metal oxide semiconductor (CMOS), with 1.2-V input and 1-V output, exhibits a measured quiescent current (IQ) varying from 27 to 82 μA for a load current ILOAD between 5 μA and 20 mA. The circuit achieves a low frequency PSR of –58 dB with the worst full-spectrum PSR of –9 dB in 20 mA ILOAD with a 300 pF on-chip output capacitor. Further, with an UGB over 400 MHz, the proposed FVF LDO reaches 0.9 ns response time when ILOAD changes between 100 μA and 20 mA with edge times less than 0.8 ns. [ABSTRACT FROM AUTHOR]

Torque ripple degrades the performance of a permanent magnet synchronous motor (PMSM). Harmonic injection method can minimize torque ripple well by suppressing the speed harmonic. But its performance under transient conditions is not satisfactory. Moreover, too much computation and complex parameter adjustment limit its application in multiharmonic suppression of speed. Therefore, this article proposes an order-domain-based harmonic injection (OHI) method for multiple speed harmonics suppression under both steady-state and transient conditions. In the OHI method, speed harmonics are extracted as feedback signals and suppressed by a speed harmonic controller. The speed harmonic controller is designed based on real and imaginary parts. The relations among the voltage, current, and speed harmonics are derived. According to these relations, speed harmonics are adjusted directly by voltage harmonics. For faster harmonic extraction, the real-time angular-domain Fourier transform (AFT) is proposed by improving an AFT algorithm. The OHI method has less calculation and simpler parameter adjustment compared with existing methods. So, it is more suitable for multiharmonic suppression of speed. Due to the extremely fast respond of speed harmonic control loop, the OHI method is effective even under transient conditions. The OHI method is simulated and experimentally evaluated in PMSM servosystem. [ABSTRACT FROM AUTHOR]

This article presents a novel control system for a regulated resonant switched-capacitor point-of-load converter, together with its steady-state and small-signal analyses. The output voltage is regulated through a combined frequency/phase shift on-chip controller that operates, thanks to a zero-crossing detector for the tank current. By using such a control technique, voltage regulation can be achieved for a wide range of conversion ratios. Different operation modes are adopted to maximize the efficiency at every load condition. A prototype based on an ASIC developed in a 130-nm CMOS technology has been designed, which achieves the 2.5 to 0.8–1.35 V conversion and supplies up to 3 A. The external resonant tank is composed of a 12 nH air-core inductor and a 4.7  $\mu$ F capacitor in a 0805 package, achieving high power density. The converter efficiency is demonstrated to be similar to that of an integrated buck converter designed for the same application, whereas the inductor size is reduced by a factor of eight. [ABSTRACT FROM AUTHOR]

To deal with the single-phase open-circuited fault, an enhanced fault-tolerant model predictive current control with continued modulation is proposed in this article. This method includes reconstructing the postfault vector distribution and adopting a multistep vector selection method. In the reconstruction procedure, the transition vectors are generating to realize standard pulsewidth modulation waveforms. Then, the unreachable area can be filled by creating new synthetic vectors. Finally, the vectors with oversized amplitudes are optimized by using null vectors. In order to cover the full modulation area, a multistep vector selection method is used to determine the phase angle and amplitude of the optimal vector. The phase angle can be determined by defining two cost functions and adopting duty cycle modulation technology. The amplitude of the optimal vector can be optimized by utilizing the duty cycle modulation technology again. The oscillation, due to the back electromotive force, is compensated in each step. A thorough experimental evaluation has been conducted to confirm the effectiveness and superiority of the proposed fault-tolerant method. [ABSTRACT FROM AUTHOR]

The variable switching frequency pulsewidth modulation (VSFPWM) is varying the carrier frequency of pulsewidth modulation (PWM) based on the prediction model to reduce the switching losses and lower the electromagnetic interference (EMI). However, it may cause some deterioration in digital dq current control of voltage source converters. This article takes the L-type grid-connected converter as the research object, and first presents the generation mechanism of the varying time delay caused by VSFPWM. In the case of proportional-integral current regulator implemented with VSFPWM, the varying time delay is accompanied by the frame rotation, which causes a varying phase lag in output voltages, degrading the system performance. Subsequently, an analytical method based on complex coefficient transfer functions is developed to provide an accurate explanation of the relation between the VSFPWM and the corresponding impacts. A compensation method is then proposed to eliminate the varying phase lag of output voltages when the VSFPWM is employed, improving the steady state and dynamic performance of dq current control. Finally, the simulation and experimental results are presented to verify the analysis and the effectiveness of the proposed compensation method. [ABSTRACT FROM AUTHOR]

Finite-control-set model predictive control (FCS-MPC) techniques have been widely applied for power electronics, and motor drive. Furthermore, the principles of FCS-MPC have been extended to phase-locked loop (PLL), which called finite-position-set PLL (FPS-PLL), for sensorless control of permanent-magnet synchronous generators (PMSGs) in wind turbine applications (WTAs). However, 64 iterations are essential to find the optimal rotor position, i.e., high computational burden. In this article, two computationally efficient (CE) FPS-PLLs are proposed for encoderless control of PMSGs in WTAs. The first CE-FPS-PLL1 reduces the number of iterations to 36 with slightly better accuracy than the FPS-PLL, while the second (novel) CE-FPS-PLL2 calls for only 24 iterations to find the best rotor position with significantly better accuracy than the FPS-PLL. The performance of the proposed CE-FPS-PLLs has been experimentally investigated, and compared with that of the FPS-PLL, and classical PLL using a 14.5-kW PMSG. Furthermore, the robustness of the proposed CE-FPS-PLLs is investigated against variations of the PMSG parameters. [ABSTRACT FROM AUTHOR]

This letter presents a periodically refreshed capacitive floating level shifter (CFLS) for applications that require a conditional switching signal. The proposed structure can generate a floating signal without additional bias voltage, and all coupling capacitors (CCs) can be simultaneously refreshed. Digital low-dropout (DLDOs) regulators are integrated to show how the leakage current from a CC affects the DLDOs that are driven by conventional and proposed CFLSs. Results are measured according to the temperature and supply voltage. With a 28-nm CMOS process, the proposed CFLS achieves a delay of 8.9 ns including the I/O buffer delay and an energy consumption of 788 fJ per cycle at VDD = 0.9 V. [ABSTRACT FROM AUTHOR]

This article proposes a bandgap reference (BGR) recursive low-dropout (LDO) regulator chip that achieves a high power supply rejection (PSR) in the low- to mid-frequency range. The presented LDO design enables the total PSR of LDO to be free from the finite ripple-rejection of the BGR circuit, resulting in low design complexity and low power consumption. To improve the PSR further, the gate buffer is modified to provide an additional ripple feedforward cancellation. The modified gate buffer also offers fast transient response and stable operation. Moreover, a light-load stabilizer loop is also suggested to provide high stability over all load conditions. A prototype chip able to supply up to 300 mA output current was implemented by 0.5-μm 5-V CMOS devices. The PSR was measured to be –102 to –80 dB at frequencies from 100 Hz to 0.1 MHz, which is higher than that of prior LDOs with COUT ≥ 1 μF. The proposed LDO consumes only 50 μA at a load current of 300 mA, and a peak current efficiency of 99.98% was achieved. The line and load regulations were measured as 0.003%/V and 0.28%/A, respectively. This chip shows a figure-of-merit of 11 ps in the transient response. [ABSTRACT FROM AUTHOR]

This article proposes a dual-parameters compensation control method to improve the torque accuracy of permanent magnet synchronous motor (PMSM) in flux-weakening region for rail transit. For the sake of the feature that six-step operation is the essential operation of rail transit and switching frequency is very low, the proposed method works on the single q-axis current regulator-variable voltage angle (SQCR-VVA) flux-weakening control strategy for PMSM operation. Based on SQCR-VVA flux-weakening control, impact of inaccurate parameters is analyzed in seven different conditions, and inaccurate parameters (d-axis inductance, q-axis inductance and permanent magnet flux linkage) result in the errors on d-axis current response and d-axis feed forward voltage. In order to eliminate the impact of the three parameters at the same time, dual compensation regulators are applied to the proposed method. Error of q-axis inductance is identified by the d-axis voltage regulator. The whole impact of inaccurate d-axis inductance and permanent magnet flux linkage is eliminated by the d-axis current regulator. The proposed method is subsequently tested on PMSM and shows quite good performance on the improvement of torque accuracy. [ABSTRACT FROM AUTHOR]

An advanced smooth pole tracking technique for a low dropout (LDO) regulator with a ceramic capacitor is presented in this article. Normally, the dominant pole is at the output of an LDO and becomes load dependent, which may cause a loop stability issue during the whole load-current application range. The proposed frequency compensation methodology with adaptive load resistor control of an error amplifier (EA) alleviates the problem and reduces the dependence of equivalent series resistance of an output capacitor. Moreover, combined with this compensation strategy, an ultrafast EA by utilizing a transconductance enhancement technique is proposed to greatly reduce output voltage spikes as well as response time of the LDO during transient. This circuit has been implemented in a 0.18-μm standard CMOS process and occupies an active chip area of 0.017 mm2. Experimental results show that it can deliver 150 mA load current at 200 mV dropout voltage. Good loop stability and transient responses are easily achieved without degrading other important LDO parameters. [ABSTRACT FROM AUTHOR]

In an islanded microgrid composed of droop-controlled parallel inverters, the system frequency endures deviations as the load changes. To compensate for frequency deviation without involving communication infrastructures among distributed generators (DGs), the proportional-integral regulator based secondary frequency control (PI-SFC) method has been proposed in the literature. However, PI-SFC may incur real power-sharing errors because the integrator accumulates disturbances and noise in each DG, leading to different compensation values of nominal real power. To achieve frequency restoration while maintaining equal real power sharing among DGs, this article proposes a small-ac-signal injection-based secondary frequency control (SACS-SFC) method, which is implemented by injecting an additional ac signal into the output voltage of each DG. Furthermore, a droop relation between the frequency of the injected SACS and the compensation value of nominal real power is innovatively established to trim the output real power of each DG to be equal. Frequency deviations caused by primary droop control are thus eliminated, and even real power sharing can be maintained among DGs. Moreover, the control parameters of the proposed SACS-SFC are comprehensively designed via steady state and dynamic model of the system. Simulation and experimental results demonstrate the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

A mixed-signal adaptive ripple canceller for reducing switching noise and spurious emissions in switching regulators is presented. The proposed mixed-signal ripple suppression technique tracks and cancels the switching noise by utilizing two schemes: A primary mixed-signal adaptive ripple canceller that provides large signal ripple cancellation up to 20 dB, and an auxiliary linear amplifier-based ripple canceller that minimizes the residual ripple content, achieving a combined ripple rejection of 24 dB. Proposed approach operates without the need for external components, reducing overall printed circuit board area without loss of efficiency. The adaptive ripple canceller is designed and fabricated in a 250 nm CMOS process with four levels of metal. The ripple-canceller is integrated with an on-chip buck regulator to characterize its rejection effectiveness. The ripple canceller can also be utilized as a stand-alone ripple cleaner module with an external commercial-off-the-shelf (COTS) switching regulator. The proposed ripple canceller can track and cancel power supply ripple up to 1 MHz with 24 dB rejection and reduces ripple content up to fourth harmonic by at least 20 dB while supporting dc loads up to 1 A and ripple currents up to 350 mApk-pk. The proposed approach achieves 30% lower quiescent current than using a linear low-dropout regulator without the need for any external components. [ABSTRACT FROM AUTHOR]

Thermal drift-caused current measurement offset error usually results in unfavorable torque ripples of fundamental frequency, and hence a compensation method for current offset error is proposed in this article, which is initially derived based on the nonsalient-pole machines and then extended to the salient-pole machines. By filtering the difference between the predicted currents from a simple nominal model and the measured currents, the offset error is directly estimated and then compensated with minimal effects on the current dynamics. It is proved that the estimation is accurate if the filter has unity gain at the frequency of the offset error. Therefore, the proposed method is free of the current regulator type and shows strong robustness against machine parameter deviations. It can also stably work even when the output voltage is saturated. Two kinds of filters are designed in the stationary reference frame, and the low-pass filter with low bandwidth is recommended for its easy implementation. Finally, the effectiveness of the proposed method is verified by simulations and experiments. [ABSTRACT FROM AUTHOR]

An adaptively biased low-dropout regulator (AB-LDO) with current mirror buffer has been proposed in previous literatures, which only solves a few of the specific problems of AB-LDO without additional synthetical analysis of the various performances. Based on the analysis, it is found that enhancing the current efficiency of operational transconductance amplifier (OTA) is a key factor to improve the performances of AB-LDO. A current reusing current-mode OTA (CRCM-OTA) with high current efficiency is proposed to apply to AB-LDO. Compared with the traditional AB-LDO, it can achieve an obvious improvement of AB-LDO performances including the current efficiency of AB-LDO, loop gain, and loop bandwidth without increasing the area and power consumption. This article also adopts an intuitive method different from the previous works to analyze the whole loop. The AB-LDO using an advanced CRCM-OTA was fabricated in SMIC 0.18 μm CMOS process, which has a transient undershoot of 26.25 mV with an output capacitor of 1 μF for a load step of 0–50 mA with edge time of 10 ns and realizes a performance figure of merit (FoM) value of 13.65 ps. [ABSTRACT FROM AUTHOR]

This article analyzes and discusses peak-current mode control (PCMC) in dc–dc voltage regulators using power inductors subjected to saturation. It is proved that the impact of inductors saturation on the operation of the PCMC regulators can be reliably predicted by means of the proposed mathematical model and technique. The results of circuit simulations and experimental measurements, regarding a dc–dc boost regulator, validate the theoretical analysis and the proposed model. The results confirm that the use of saturable inductors is a viable and reliable solution for PCMC regulators and demystify some concerns about the behavior of saturable inductors in the presence of line/load transients and overloads. [ABSTRACT FROM AUTHOR]

Power-electronics-based emulators have been showing promising prospects in advanced testing of various applications of power electronics systems. For electric machine applications, typical machine emulators calculate the references of stator current in response to terminal voltages via mathematical models of the machine system, and then, the current behaviors of emulators are regulated by using feedback controls. However, the dynamic and high-frequency performances of these machine emulators could be distorted by the introduced control loops, thus compromising the emulating performances. In this article, the limits of typical machine emulators are analyzed, and a new approach is proposed for the real-time emulation of permanent magnet synchronous machines (PMSM). A linear regulator without feedback control loop is proposed and designed to reshape the frequency-domain characteristics of the converter and current filter inside the emulation system. Compared with typical solutions, the proposed approach has frequency-domain characteristics closer to the target PMSM. The dynamic performances can be more accurately recreated, and the applicable frequency range for emulation can be extended. Simulations and experimental validations are also conducted to verify the effectiveness of the proposed approach. [ABSTRACT FROM AUTHOR]

This article describes the development of an 18 kV, 30 kW power supply for a pulsed current load with the maximum current of 20 A and a di/dt equal to 100 A/μs. The achieved output ripple is less than 0.01%. In such a high level of precision, the most important issues are considerable difference between the instantaneous and average output powers, as well as insufficient reaction speed of the converter to the fast load change. Very low level of the voltage feedback and its sensitivity to the noise. The first issue necessitates a notable overdesign of the converter switches if the output voltage precision is dedicated to the converter. The second issue raises the problems relevant to observing the voltage ripple and providing it for the control loop. This article proposes, a fast and high current linear regulator developed based on the load current feedforwarding. Using this approach, the fast regulator compensates the voltage change caused by a high level of instantaneous power. The main converter maintains the average power. Thus, there is no need for converter overdesigning. Furthermore, the problems relevant to the high voltage feedback and providing it for the control loop are removed. The voltage feedback is solely served to correct the current loop probable error. Hence, the sensitivity of the control loop against the existing noise is minimized. Despite existing a 600 nF capacitor as the output capacitor, the output voltage drop is less than 0.01% in a wide range of the output current pulse up to 250 μs. The power supply is constructed and experimental results are provided to verify the mentioned specifications. [ABSTRACT FROM AUTHOR]

Grid-tied inverters are widely used for interfacing renewable energy sources or storage devices to low-voltage electrical power distribution systems. Lately, a number of different control techniques have been proposed to address the emerging requirements of the smart power system scenario, in terms of both functionalities and performance. This article reviews the techniques proposed for the implementation of current-controlled or voltage-controlled inverters in microgrids. By referring to a voltage source inverter with an ${LCL}$ output filter, different control architectures are classified as single, double, and triple loop. Then, the functionalities that are needed or recommended in the grid-connected, islanded, and autonomous operating modes of the grid-tied inverter are identified and their implementation in the different control structures is discussed. To validate the analysis and to better illustrate the merits and limitations of the most effective solutions, six control strategies are finally implemented and experimentally compared on a single-phase, grid-connected inverter setup. [ABSTRACT FROM AUTHOR]

Intel's microprocessors are powered by high-frequency fully-integrated switching regulators implemented on die. Current products use non-magnetic inductors designed in the package substrate. This article investigates the use of magnetic thin film inductors fabricated on silicon wafers as an alternative that improves conversion efficiency while achieving higher inductance per area density. This article builds on the earlier work done on thin film inductors at Intel, and explores the feasibility of using them in a high volume product. A number of different design variations are studied to look at tradeoffs between efficiency, saturation characteristics, transient response, and voltage ripple. This is accomplished through a combination of passive measurements using a vector network analyzer (VNA) and active measurements on a fully functioning integrated voltage regulator system. [ABSTRACT FROM AUTHOR]

Deadbeat predictive current regulator features fast dynamic responses. However, it suffers from the steady-state current tracking error in a practical system due to the plant uncertainties, particularly the inductances. Instead of using observer-based disturbance voltage feedforward methods, this article proposes a new closed-form method to directly compensate the current tracking errors with a simple feedforward term added to the voltage commands. Zero steady-state error is achieved with negligible computation compared to the observer-based methods. The new method is first derived to tackle the inductance mismatch in the surface-mount permanent magnet synchronous motor, then the system close-loop transfer function is established to prove that the proposed method guarantees the zero steady-state error even with mismatches of the stator resistance and rotor flux linkage. Furthermore, based on the proposed compensation method, noise suppression schemes are added and designed to reduce high-frequency noise sensitivities in practical systems. Finally, the proposed method is extended to the interior permanent magnet synchronous motor (IPMSM). IPMSM system simulation and 68.5-kW experimental results are provided to validate the proposed method. [ABSTRACT FROM AUTHOR]

The proposed digital low-dropout regulator uses nonlinear switching control (NLSC) technique to suppress voltage ripple to less than 6 mV when the switching noise voltage of a switching regulator operating in a power-saving mode is greater than 50 mV. In addition, the NLSC technique improves the current efficiency by reducing the quiescent current to less than 10 μA and reduces the switching power loss through variable switching frequency control. With a load step of 1–20 mA, the transient response time is 1.3 μs and the peak current efficiency is 99.8% at heavy loads. [ABSTRACT FROM AUTHOR]

The variable dc-link voltage control methods can effectively improve the operation efficiency of the permanent magnet synchronous motor (PMSM) drive system. At present, the reported variable dc-link voltage control methods applied in the PMSM driven by a quasi-Z-source inverter (qZSI) are limited to the analytical calculation methods (ACMs) based on the system model. The ACMs demand measurement of qZSI's input voltage and usually need a larger margin index due to the inaccurate model to calculate the reference dc-link voltage. To overcome the restriction, this article proposes a novel variable dc-link voltage control method that can indirectly adjust the dc-link voltage with an extra proportional–integral (PI) regulator. Basic principle of the method is introduced and two design rules of the PI regulator are illustrated. Besides, necessary conditions that need to be met when obtaining the feedback signal of the PI regulator are analyzed. Finally, experiments are performed to validate the feasibility and effectiveness of the proposed method. In comparison with the ACMs, the proposed method gets rid of the dependence on an extra voltage sensor to measure the input voltage and can reserve less margin for the dc-link voltage, which contributes to less cost and higher efficiency of the drive system. Besides, the proposed method is easy and convenient to apply. [ABSTRACT FROM AUTHOR]

This article presents an agile supply modulator with optimal transient performance that includes improvement in rise time, overshoot and settling time for the envelope tracking supply in linear power amplifiers. For this purpose, we propose an on-demand current source module: the bang–bang transient performance enhancer (BBTPE). Its objective is to follow fast variations in input signals with reduced overshoot and settling time without deteriorating the steady-state performance of the buck regulator. The proposed approach enables fast system response through the BBTPE and an accurate steady-state output response through a low switching ripple and power efficient dynamic buck regulator. Fast output response with the help of the added module induces a slower rise of inductor current in the buck converter that further helps the proposed system to reduce both overshoot and settling time. This article also introduces an efficient selective tracking of envelope signal for linear PAs. To demonstrate the feasibility of the proposed solution, extensive simulations and experimental results from a discrete system are reported. The proposed supply modulator shows 80% improvement in rise time along with 60% reduction in both overshoot and settling time compared to the conventional dynamic buck regulator-based solution. Experimental results using the LTE 16-QAM 5 MHz standard shows improvement of 7.68 dB and 65.1% in adjacent channel power ratio (ACPR) and error vector magnitude (EVM), respectively. [ABSTRACT FROM AUTHOR]

As a combination of the switched-mode converter and linear amplifier, the switch-linear hybrid (SLH) envelope tracking (ET) power supply can achieve high efficiency and high tracking bandwidth simultaneously, and it can be classified into three types, namely, series-form, parallel-form, and series–parallel-form. In the SLH ET power supply, interaction may occur between the converters, and as a result, the controlled variable will deviate from its target. In this paper, the interaction in the series-form SLH ET power supply with different structures is analyzed first from the aspects of control and parasitic capacitances, and the feedforward control scheme and/or filter is adopted to eliminate the interaction. Then, for the parallel-form SLH ET power supply, four current control methods are introduced and compared from the current tracking and disturbance-rejection performances, and the method for suppressing the disturbance is presented. Since series–parallel-form SLH ET power supply contains at least three converters, the interaction is more complex. On the basis of the analysis of the series-form and parallel-form SLH ET power supplies, the interaction between the converters in series–parallel-form SLH ET power supply is analyzed and followed by the corresponding elimination method. Finally, one series-form, and one parallel-form SLH ET power supplies are implemented in the lab, and the experimental results verify the theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper establishes the first integrated silicon carbide (SiC) CMOS linear voltage regulator. The design provides for a continuous load current exceeding 100 mA and a 15 V output from an input voltage of 20 to 30 V. The foundation of the regulator's feedback loop is formed by a two-stage SiC operational amplifier. Both internal and external passive components are used in the frequency compensation network. An external 7.5 V supply is connected to the operational amplifier and acts as the reference voltage. At 400 °C, experimental results show a line regulation of better than 1.5 mV/V under a 100-mA load. The load regulation with a 30-V input and at 400 °C is shown to be 0.42 mV/mA. Sustained operation of the linear regulator is demonstrated over 30 h at 300 °C. [ABSTRACT FROM AUTHOR]

A current-mode buck regulator with delay-based hysteretic control for microcontroller applications is proposed. Unlike conventional hysteretic buck regulators with accurate explicit hysteretic bands, the proposed design relies only on the inherent delay of a low-speed single-threshold comparator to realize the hysteretic band, and can be seamlessly used across all loads in continuous conduction mode and discontinuous conduction mode without modifying the controller's parameters. Moreover, without additional adaptation circuits or frequency regulation loops, the proposed delay-based hysteretic operation does not increase variations in the switching frequency with process and temperature, and results in even less variations in the switching frequency with the input and output voltages when compared to corresponding designs with accurate explicit hysteretic bands. The simplicity of the design reduces silicon area and quiescent current significantly, which in turns enables achieving high efficiency at both heavy and light load conditions as strictly required by low-power microcontrollers. The regulator is designed in a 65 nm digital CMOS technology. It occupies 0.18 mm2 and supports a wide range of input voltages (1.8–4.2 V), output voltages (0.9–1.5 V), and load current (up to 300 mA). Measurement results show that the proposed regulator achieves 95% peak efficiency, while achieving between 62% and 87% efficiency at 10-μA load across all operating conditions. [ABSTRACT FROM AUTHOR]

Due to the requirements of multiple working conditions for induction motor in high-speed flux-weakening operation, conventional “maximum torque oriented” flux-weakening controller reveals its own limitations. This paper focuses on holistic torque performance optimization for multi-condition operation. Torque ripple and dynamic response under two kinds of specific working conditions (high-speed braking and load step change) are explicitly analyzed. The theoretically precise maximum torque point is derived to extract the possible output torque for deep flux-weakening operation. Further, an operating point selected flux-weakening controller (OPS-FC) is proposed. It retains the maximum output torque capability for step acceleration and full-load conditions, as well as holding other novel features for the changing working conditions. First, the selected operating point is automatically manipulated for torque ripple alleviation under non-maximum torque condition. Second, since the voltage reference in proposed OPS-FC is directly constructed, the system robustness is enhanced. Finally, speed range is extended to the deep flux-weakening operation, and the complex vector decoupling part of d-axis current regulator is first applied and shared as a flux-weakening path for closed-loop control. Hence, the complicated PI regulator tuning is averted. The proposed scheme is experimentally verified on a 3.7 kW commercial platform. [ABSTRACT FROM AUTHOR]

The flipped-voltage-follower-based low-dropout regulator (LDO) has drawn attention for its fast response and reduced complexity, while super source follower can be combined to push the pole at the gate of the pass device to high frequency. But the maximum load current and minimum load capacitance of this topology are limited, especially when the poles and zero from the SSF are omitted in previous designs. This paper proposes a solution to extend the ranges of the load current and load capacitance, by implementing a small feed-forward capacitor ($C_{F}$) and a damping factor control circuitry. In addition, a slew rate enhancement circuit is applied to reduce the voltage undershoot. The proposed LDO is verified in a 65-nm CMOS process with 0.008 mm2 active area. The measured voltage undershoot is 80 mV with a load steps from 100 μA to 50 mA with 2-ns edge times, with no external capacitor. And the maximum load capacitance can be extended to 2 nF. A figure-of-merit of 0.8 mV is achieved. [ABSTRACT FROM AUTHOR]

In this paper, to improve the robustness and realize the precision positioning as well as speed control of the servo drive system, an integrated sliding-mode control (ISMC) optimized by differential evolution (DE-ISMC) algorithm is proposed. ISMC guarantees that a motor can reach at given position with given speed, and given speed is set first. ISMC, which is combined with speed regulator and position regulator, is different from the conventional sliding-mode control (SMC) replacing speed regulator. ISMC can guarantee that motor speed is controlled under position control mode, which is a novelty and an advantage of ISMC in this paper. To achieve good control performance of ISMC, parameters of it should be chosen exactly, so DE algorithm is selected to optimize them. The most significant influence factor of DE algorithm is the optimization iteration. Once parameters of ISMC are optimized under convergent iteration, servo system performance reaches given indices in the shortest time. Experimental results indicate that robustness of the servo system is improved; correctness and effectiveness of DE-ISMC are verified. [ABSTRACT FROM AUTHOR]

A simple multiplier for the estimation of the maximum power yield of a solar panel may be realized with a pulsewidth modulator working as analog multiplier circuit. Though the output of the pulsewidth modulator multiplication is not proportional to the actual output power of the solar panel, it may be shown that its maximum follows the maximum of the power curve of the panel. The multiplier allows a complete analog implementation of the maximum power point tracker of the panel thus keeping the simplicity needed in robust electronic systems. This paper presents the working principle of the maximum power point regulator, its design procedure, and a practical implementation for a low power solar panel, 7.1 V and 487 mA, used in small satellite platform applications. [ABSTRACT FROM AUTHOR]

In order to match the long life span of light emitting diodes (LEDs), electrolytic capacitor-less off-line LED drivers have been intensely developed. However, the relatively low power efficiency is a common issue for many electrolytic capacitor-less designs. In this paper, a more efficient single-coupled-inductor multiple-output (SIMO) LED driver is proposed. The electrolytic capacitor-less design is targeted for lighting applications with color mixing and color temperature adjustment, where a small capacitance actively balances the power difference between the ac input and multiple dc outputs. Using energy-flow-path optimization, the proposed LED driver has some direct and efficient energy flow paths. In particular, additional energy flow paths are implemented, connecting directly from the small capacitance to multiple dc outputs. Thus, the overall power efficiency is improved. Furthermore, the proposed LED driver is designed with a carrier-based control without the high-precision current sensor for the single-coupled inductor, and thus simpler signal sampling and reduced control complexity can be achieved for independent regulations of multiple dc outputs. [ABSTRACT FROM AUTHOR]

In this paper, a load torque observer and two moment of inertia identification methods are developed for permanent magnet synchronous motor drive systems. First, the load torque identification method is proposed based on sliding mode observer, in which the mismatches of moment of inertia, electromagnetic torque, and viscous friction are all considered. It is analyzed that the chattering phenomenon will be well weakened if appropriate observer parameters are chosen. Second, based on the property that the mismatch of the moment of inertia will cause the load torque observation error, two types of moment of inertia identification methods, called direct calculation (DC) method and proportional integral (PI) regulator method, are presented to identify the moment of inertia. In addition, the identification errors of the DC and PI regulator methods are also analyzed theoretically. Simulation and experimental results show that compared with the conventional identification method of the moment of inertia, the proposed DC and PI methods have improved estimation accuracy. Moreover, the presented load torque observer also has high observation precision and fast convergence speed. [ABSTRACT FROM AUTHOR]

Stacked mosfet structures made of low-voltage devices suffer from degraded transient response or large footprint when a capacitorless or dominant-pole compensated low-dropout (LDO) regulator biases the driver. Due to the self-stabilizing nature, the proposed stacked mosfet driver (SMD) technology effectively drives the power stage and greatly reduces the noise at the switching nodes for low cross regulation (CR) in a single-inductor dual-output (SIDO) converter. In addition, two inherent LDO regulators in SMD technology fully regulate the dual outputs with the advantage of low quiescent current at no-load conditions. The experimental results show that the test chip fabricated under the 0.25-μm process has low CR of 0.015 mV/mA and ultralow quiescent current of 5 μA under no-load conditions. [ABSTRACT FROM AUTHOR]