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This paper describes the design of a two-level hierarchical production scheduling engine, which captures the industrial practice of mass production semiconductor fabrication factories (fabs). The two levels of the hierarchy consist of a mid-term scheduler and a short-term scheduler, and are aimed at achieving coordination between the fab-wide objectives and local shop-floor operations. The mid-term scheduler maximizes weighted production flow to reduce the fab-wide cycle time and ensure on-time delivery by properly setting daily production target volumes and reference work-in-process (WIP) levels for individual part types and stages. Mid-term scheduling results are further broken down into more detailed schedules by the short-term scheduler. In addition to the same set of operational constraints in mid-term scheduling, the short-term scheduler includes the consideration of batching effects. It maximizes weighted production flow while tracking the daily production targets and the reference WIP levels specified by mid-term scheduling. The schedulers adopt a solution methodology with three ingredients; the Lagrange relaxation approach, network flow optimization, and Frank-Wolfe method. The scheduling tool is reasonably efficient in computation.

Computational efficiency is one of the major challenges of applying simulation to short-term operation scheduling of semiconductor wafer fabrication factories (fabs), which are characterized by re-entrant process flows, stringent production control requirements and fast changing technology and business environments. The paper explores the application of the ordinal optimization (OO)-based simulation technique to efficiently selecting good rules for scheduling wafer fabrications. An efficient simulation tool, which makes use of OO and optimal computing budget allocation techniques, is developed. Experiments with the OO-based simulation tool are conducted for static selection of good rules under different factors such as initial state, performance index and time horizon. Results indicate that one to two orders of computation time reduction over traditional simulations can be achieved and that what rules are good varies with factors of initial state, performance index and time horizon. These results motivate our further investigation about applications to dynamic selection of dispatching rules upon the occurrence of two significant uncertain events: holding of significant amount of wafers-in-process due to engineering causes and major machine failures. Results demonstrate the value of dynamic rule selection for uncertainty handling, the insightful selection of good rules and the needs for future research.

This paper presents a Lagrangian relaxation-based approach for production scheduling of flexible flow shops (PSFFS) where sequence-dependent setup effects are significant. PSPFS is first formulated as a separable integer programming problem with synchronization constraints between production and machine usage. Lagrangian relaxation is then applied, and the scheduling is decomposed into part production and machine scheduling. In these subproblems, there are network flow structures in the equality constraints describing machine status change and production flow balance. Our iterative algorithm applies a minimum cost network flow algorithm to individual subproblems and adopts an efficient surrogate subgradient method to optimize Lagrangian multipliers. A machine availability-searching heuristic finally adjusts the solution to satisfy all synchronization constraints by exploiting the network structure, economic interpretation of Lagrangian multipliers, and the slack time policy. Numerical results of 16 cases, each having 20 test problems, demonstrate that differences between the schedules obtained by our approach and the true optima are on average within 15%, CPU times spent are all less than 17 min on a Pentium-II personal computer. Among the problem dimension factors, the number of part types has the most significant effect on both optimality and computation efficiency. Application of the methodology to daily scheduling of a realistic integrated circuit testing facility of 30 machines takes about 6 min of CPU time to generate a near-optimal solution.