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Transistor random threshold voltage variations due to process fluctuations seriously affects the stability of Static Random Access Memory (SRAM). In this paper, a SRAM bit transistors threshold voltage $({Vth})$ deviation monitoring scheme and system is proposed. This scheme ingeniously achieves on-chip measurement of all transistors threshold voltages without altering compact SRAM bit array layout. Control signal strategies and Transistor ${Vth}$ Determination Circuit (TVDC) for different types of Devices Under Test (DUTs) have been proposed. The system is implemented using a 65 nm CMOS process with a core area of 0.01875mm2. Through Monte Carlo analysis, the Weighted Average (WA) difference of the proposed scheme and the direct measurement method is not more than 10mV, and the Root Mean Square Error (RMSE) difference is not more than 3mV. This system can also effectively detect the cell position of the transistor threshold voltage mismatch simulated by modifying the substrate voltage. For SRAM arrays of different scales, the method proposed in this paper has area efficiency and flexible reconfigurability. [ABSTRACT FROM AUTHOR]

This paper studies simultaneous scheduling of production and material transfer that arises in the semiconductor photolithography area. In particular, the right reticle and right job both need to be present to process the job. Jobs are transferred by a material handling system that employees a fleet of vehicles. Reticles serving as an auxiliary resource are also transferred from one place to another by a different set of vehicles. This intricate scheduling challenge, encompassing jobs, reticles, machines, and two distinct sets of vehicles, is explored here for the first time. The paper introduces a multi-stage methodology that involves relaxation, a constructive heuristic, constraint programming, and a warm-start approach to address this complex problem. [ABSTRACT FROM AUTHOR]

The document is the table of contents for the May 2024 issue of the IEEE Transactions on Semiconductor Manufacturing. It includes papers on various topics such as yield modeling, analysis, and enhancement, advanced processing, advanced process control, equipment and automation technology, non-silicon materials, emerging areas, and environment, safety, and health. The articles cover subjects such as chip-scale chemical mechanical polishing, threshold voltage deviation monitoring, curvilinear standard cell design, fabrication of silicon nanocone arrays, improving the reliability of through silicon vias, energy consumption and carbon emission reduction in HVAC systems, low-k silicon dioxide synthesis, chemical mechanical polishing of diamond epitaxial layers, conditional variable selection based on deep learning, and eco-friendly dry-cleaning and diagnostics of silicon dioxide deposition chambers. The document also includes an announcement for the call for nominations for the 2024 IEEE EDS Early Career Award. [Extracted from the article]

Chemical mechanical polishing/planarization (CMP) combines physical grinding and chemical reactions to planarize the wafer surface. The complex mechanism of CMP brings great challenges to the mechanism-based modeling process. The data-driven CMP modeling process is limited by insufficient datasets. At the same time, these two types of models generally have high computational complexity. In this paper, we introduce the group method of data handling (GMDH)-type polynomial network to build the CMP model to address the above challenges. We designed and manufactured the test chip using a 28nm process. The measurement data from the test chip shows that compared with the mechanism-based CMP model, the trained CMP model based on GMDH-type polynomial network has higher accuracy and lower computational complexity, with the average simulation speed being 115x faster. Experiments based on silicon data show that this modeling method has a small demand for data, and 20 randomly selected sets of data can meet the needs for modeling the current CMP process. [ABSTRACT FROM AUTHOR]

This paper proposes a linear regression model for scalar-valued responses and two-way functional (bivariate) predictors. Our motivation stems from the quality evaluation of products based on optical emission spectroscopy data from virtual metrology of semiconductor manufacturing. We focus on multivariate cases where the smoothness and shapes of the data vary significantly across variables. We propose a two-step solution to this problem, consisting of decomposition and prediction. First, we decompose the two-way functional data into pairs of component functions using functional singular value decomposition. Next, we build functional linear models for the decomposed functional variables and obtain the final predictor by averaging the models. Results from numerical studies, including simulation studies and real data analysis, demonstrate the promising empirical properties of the proposed approach, especially when the number of predictors is large. [ABSTRACT FROM AUTHOR]

It has been a widely growing interest in using silicon carbide (SiC) in high-power electronic devices. Yet, SiC wafers may contain killer defects that could reduce fabrication yield and make the device fall into unexpected failures. To prevent these failures from happening, it is very important to develop inspection tools that can detect, characterize and locate these defects in a non-invasive way. Current inspection techniques such as Dark Field or Bright field microscopy are effectively able to visualize most such defects; however, there are some scenarios where the inspection becomes problematic or almost impossible, such as when the defects are too small or have low contrast or if the defects lie deep into the substrate. Thus, an alternative method is needed to face these challenges. In this paper, we demonstrate the application of coherent Fourier scatterometry (CFS) as a complementary tool in addition to the conventional techniques to overcome different and problematic scenarios of killer defects inspection on SiC samples. Scanning electron microscopy (SEM) has been used to assess the same defects to validate the findings of CFS. Great consistency has been demonstrated in the comparison between the results obtained with CFS and SEM. [ABSTRACT FROM AUTHOR]

This paper addresses the quality control of the photolithography process in the semiconductor industry. Overlay errors in the process seriously affect the wafer yield, and cause the wafer to be forced to rework and affect the production efficiency of the equipment. We examine the current state of its process control, develop a novel overlay predict model, and verify the prediction results. This study proposes a Global Attention Generative Adversarial Networks (GAGAN) model to precisely predict the overlay error for the feed-forward data of the front layer, which is used as the important information and process parameters for the advanced process control of the current layer. Experiment results on a semiconductor shop-floor confirms that our proposed method achieves high predictive performance while maintaining extensibility and visual quality. [ABSTRACT FROM AUTHOR]

A scheduling problem for parallel batch processing machines (BPMs) with jobs having unequal ready times in semiconductor wafer fabrication facilities (wafer fabs) is studied in this paper. A blended objective function combining the total weighted tardiness (TWT) and the total electricity cost (TEC) under a time-of-use (TOU) tariff is considered. A genetic programming (GP) procedure is designed to automatically discover priority indices for a heuristic scheduling framework. Results of computational experiments are reported that demonstrate that the learned priority indices lead to high-quality schedules in a short amount of computing time. [ABSTRACT FROM AUTHOR]

The "IEEE Transactions on Semiconductor Manufacturing" is a journal that publishes the latest advancements in the manufacturing of microelectronic and photonic components. It aims to enhance knowledge and improve manufacturing practices in the semiconductor industry. The journal covers various topics such as process integration, manufacturing equipment performance, yield analysis, metrology, and supply chain management. Papers submitted to the journal should focus on practical engineering techniques for solving manufacturing-related problems. The journal follows a peer-review process and encourages authors from low-income countries to submit their work. The standard length for regular papers is eight pages, and shorter contributions can be submitted as letters. The journal provides guidelines for manuscript preparation, including the use of the IEEE template style. It also accepts graphical abstracts and electronic supplements. Authors are responsible for preparing a publication-quality manuscript and may use English language editing services if needed. Plagiarism is strictly prohibited, and manuscripts found to have plagiarized content may be penalized. Authors are required to have an Open Researcher and Contributor ID (ORCID) and can submit their manuscripts online. The journal offers both traditional and open access publication options, with associated fees. Native language author names are supported, and page charges may apply for publication. The IEEE holds the copyright to the published material. [Extracted from the article]

As we enter a New Year, we can look back on another year of solid accomplishment at IEEE Transactions on Semiconductor Manufacturing. I am happy to report that our impact factor remains steady at 2.70, and our mean time to first decision remains competitive at 8.3 weeks. Our Editorial Board remains as strong as ever, with the addition of Dr. Jun-Haeng Lee in the area of machine learning and data science applications in 2023, and we are actively seeking new board members. Our submissions remain strong, as do the special sections from conferences (ASMC, ISSM and CS-MANTECH). The Special Issue on Production-Level Artificial Intelligence Applications in Semiconductor Manufacturing appeared in the November issue, and two additional special issues are in preparation. Prof. Duane Boning of MIT and Dr. Bill Nehrer of Technology Consultancy are co-editing a special issue on “Semiconductor Design for Manufacturing,” which will be a collaborative effort with the IEEE Transactions on Electron Devices. Drs. Oliver Patterson of Intel and Tomasz Brozek of PDF Solutions are also co-editing a special issue on sustainable semiconductor manufacturing. We are also happy to announce the Best paper Award for 2023, in the companion editorial appearing in this issue. Congratulations to all the honorees, and we hope we will continue to see their submissions in the future. Our thanks go to Drs. Jeanne Bickford, Dragan Djurdjanovic and Mahadeva Iyer Natarajan for their work on this committee. [ABSTRACT FROM AUTHOR]