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In this paper, an energy-efficient estimation and detection problem is formulated for low-power digital filtering. Building on the soft digital signal processing technique proposed by Hegde and Shanbhag, which combines algorithmic noise tolerance and voltage scaling to reduce power, the proposed minimum power soft error cancellation (MP-SEC) technique detects, estimates, and corrects transient errors that arise from voltage overscaling. These timing violation-induced errors, called soft errors, can be detected and corrected by exploiting the correlation structure induced by the filtering operation being protected, together with a reduced-precision replica of the protected operation. By exploiting a spacing property of soft errors in certain architectures, MP-SEC can achieve up to 30% power savings with no signal-to-noise ratio (SNR) loss and up to 55% power savings with less than 1-dB SNR loss, according to the logic-level simulations performed for an example 25-tap frequency-selective filter. [ABSTRACT FROM AUTHOR]