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In this paper, the potential of Silicon-Germanium (SiGe) technology for VLSI logic applications is investigated from a circuit perspective for the first time. The study is based on experimental measurements on 45-nm SiGe pMOSFETs with a high-\kappa/metal gate stack, as well as on 45-nm Si pMOSFETs with identical gate stack for comparison. In the reference SiGe technology, an innovative technological solution is adopted that limits the SiGe material only to the channel region. The resulting SiGe device merges the higher speed of the Ge technology with the lower leakage of the Si technology. Appropriate circuit- and system-level metrics are introduced to identify the advantages offered by SiGe technology in VLSI circuits. Analysis is performed in the context of next-generation VLSI circuits that fully exploit circuit- and system-level techniques to improve the energy efficiency through aggressive voltage scaling, other than low-leakage techniques. Analysis shows that the SiGe technology has more efficient leakage-delay and dynamic energy-delay trade-offs at nominal supply, compared to Si technology. Moreover, it is shown that the traditional analysis performed at nominal supply actually underestimates the benefits of SiGe pMOSFETs, since the speed advantage of SiGe VLSI circuits is further emphasized at low voltages. This demonstrates that SiGe VLSI circuits benefit from aggressive voltage scaling significantly more than Si circuits, thereby making SiGe devices a very promising alternative to Si transistors in next-generation VLSI systems. [ABSTRACT FROM PUBLISHER]

In this paper, a novel technique to reduce the leakage current of FinFET forced stacks under a given delay constraint is presented. This technique takes advantage of the unique feature of four-terminal FinFETs allowing different transistors to have separately tunable back bias voltages. In this work, a reverse back bias voltage is applied to one of the two stacked transistors to reduce its leakage at the cost of a delay penalty, whereas a forward back bias voltage is applied to the other one to compensate this delay degradation. The technique is assessed by means of mixed device-circuit simulations for FinFETs that are representative of 40- and 27-nm technology generations. Results show that a leakage reduction by up to 50\times can be achieved as compared with traditional transistor stacks, while keeping same speed, dynamic energy, and sensitivity to process/voltage/temperature variations. [ABSTRACT FROM PUBLISHER]

In this paper, resistance-capacitance (RC) tree net- works are modeled in terms of their energy consumption associated with an input transition. This work significantly extends the results that the same authors previously obtained in the specific case of ladder networks with only ramp signals. The proposed approach to model the energy consumption is based on a single-pole approximation, in which an equivalent time constant is analytically derived from an exact analysis for very slow and very fast input transitions. The model is then extended to arbitrary values of the input rise time by exploiting some intrinsic properties of RC tree networks. The approach is completely analytical and leads to closed-form results. Analytical results are explicitly derived for different inputs, such as the ramp and the exponential waveforms which are usually encountered in current VLSI circuits, as well as the saturated sine input. Due to its simplicity, the proposed energy expression is suitable for pencil-and-paper evaluation and allows for an intuitive understanding of the network dissipation. The energy expression proposed is shown to be accurate enough for modeling purposes through comparison with SPICE simulations. [ABSTRACT FROM AUTHOR]

Ultralarge-scale integrated (ULSI) chip design data is needed for an assessment of existing on-chip wirelength distribution models. Data extracted from modern chips such as high-performance microprocessors provide information about actual wirelength requirements in ULSI chip designs. These requirements are compared with wirelength estimates obtained by evaluating existing models as functions of Rent's parameters that are extracted from the designs. This brief assesses the extent to which existing models estimate wirelength requirements in 100 ASIC-like control logic designs in the 1.3-GHz POWER4 microprocessor. For each design, physical design characteristics and wirelength requirements are measured and compared with model estimates. Lack of agreement between the data and models is observed for most designs, and possible reasons for the lack of agreement are discussed. [ABSTRACT FROM AUTHOR]

Compares the main topologies on one-bit full adder block in submicron technology for speed, power consumption and power delay product. Performance of comparison on two classes of circuits; Comparison of performance for different supply voltage values; Proposal of novel figure of merit.