28 results on '"Benini, Luca"'
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2. Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters
3. A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS
4. RNN-Based Radio Resource Management on Multicore RISC-V Accelerator Architectures
5. FPnew: An Open-Source Multiformat Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing
6. Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes
7. An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power
8. Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI
9. The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology
10. Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices
11. Logic-Base Interconnect Design for Near Memory Computing in the Smart Memory Cube
12. Ekho: A 30.3W, 10k-Channel Fully Digital Integrated 3-D Beamformer for Medical Ultrasound Imaging Achieving 298M Focal Points per Second
13. Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory
14. A Modular Shared L2 Memory Design for 3-D Integration
15. Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits
16. Fast Computation of Discharge Current Upper Bounds for Clustered Power Gating
17. Performability/Energy Tradeoff in Error-Control Schemes for On-Chip Networks
18. Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers
19. Performability/Energy Tradeoff in Error-Control Schemes for On-Chip Networks.
20. Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors.
21. Memory Energy Minimization by Date Compression: Algorithms, Architectures and Implementation.
22. Scheduling Battery Usage in Mobile Systems.
23. Minimizing Memory Access Energy in Embedded Systems by Selective Instruction Compression.
24. Power-Aware Operating Systems for Interactive Systems.
25. Layout-Driven Memory Synthesis for Embedded Systems-on-Chip.
26. Logic-Base Interconnect Design for Near Memory Computing in the Smart Memory Cube
27. A Modular Shared L2 Memory Design for 3-D Integration
28. Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory
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