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Triple-modular redundancy (TMR), which consists of three identical modules and a voting circuit, is a common architecture for soft-error tolerance. However, the original TMR suffers from two major drawbacks: the large area overhead and the vulnerability of the voter. In order to overcome these drawbacks, we propose a new complementary dual-modular redundancy (CDMR) scheme for mitigating the effect of soft errors. Inspired by the Markov random field (MRF) theory, a two-stage voting system is implemented in CDMR, including a first-stage optimal MRF structure and a second-stage high-performance merging unit. The CDMR scheme can reduce the voting circuit area by 20% while saving the area of one redundant module, achieving at least 26% error-rate reduction at an ultralow supply voltage of 0.25 V with 8.33% faster timing compared to previous voter designs. [ABSTRACT FROM AUTHOR]

In this paper, we apply the voltage overscaling (VOS) technique to the residue-number-system (RNS)-based digital signal processing system for achieving high energy efficiency. To mitigate the soft errors caused by VOS, we propose a new method, called joint RNS-RPR (JRR), which is the combination of RNS and the reduced precision redundancy (RPR) technique. The JRR technology inherits the properties of RNS, including shorter critical path, low complexity, and low power. Moreover, JRR can achieve higher power reduction than RNS for VOS applications. Since the soft errors caused by VOS lead to significant performance degradation of RNS, we use the information from RNS and RPR to achieve a high recovering probability of the soft errors with low hardware complexity. From the case study of finite impulse response (FIR) filter design based on the 0.25-\mum 2.5-V CMOS technology, we find that JRR can save 62% more energy compared to the traditional FIR with a less than 2-dB signal noise ratio performance loss. We also find that JRR has lower complexity and better performance than the traditional soft error mitigation methods. [ABSTRACT FROM PUBLISHER]