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As design of digital systems become more complex and more transistors are incorporated into a single chip, design and verification methodologies moves into higher levels. Now that design at the register transfer level (RTL) has reached its maturity, the focus is shifting to electronic system level (ESL) design tools, languages and methodologies. At the centre of this and perhaps the most challenging are verification methods and tools to use for verifying designs at the ESL. This study presents a new concept of system‐level assertions for ESL verification. It also demonstrates an environment for functionally verifying system‐level designs using these system‐level assertions. The proposed environment adapts existing EDA simulation tools, which are mainly used for RTL design and verification, and utilises them for system‐level verification. In this environment, designs are modelled in SystemC‐transaction level modelling 2.0, and assertions are written in SystemVerilog. Design and verification parts are connected together using SystemVerilog Direct Programming Interface mechanism, and designs that are described in SystemC are verified against system‐level assertions in the course of SystemVerilog simulation. [ABSTRACT FROM AUTHOR]

This article proposes an efficient and accurate embedded motor imagery-based brain–computer interface (MI-BCI) that meets the requirements for wearable and real-time applications. To achieve a suitable accuracy considering hardware constraints, we explore BCI transducer algorithms, among which Infinite impulse response (IIR) filter, common spatial pattern, and support vector machine are used to preprocess, extract features, and classify data, respectively. With our hardware implementation of these tasks, we have achieved an accuracy of 77%. Our system is designed at register transfer level (RTL) targeting an ASIC implementation, which significantly decreases power consumption, latency, and area compared to the state-of-the-art (SoA) architectures for embedded BCI systems. To this end, we fold IIR filters using time-shared and RAM-based techniques and use hardware-friendly algorithms for the implementation of other tasks. The RTL design is realized on 45 nm CMOS technology consuming 4 mW power and 0.25 mm2 area, which outperforms the SoA platforms for embedded BCI systems. To further illustrate the outperformance of our design, the proposed architecture is implemented on Virtex-7 field program gate array as a prototyping platform consuming 6 μJ energy with 1.52% area utilization. [ABSTRACT FROM AUTHOR]