Search

Abstract The utilization of switched inductors, involving parallel charging and series discharging of inductors, is extensively embraced in diverse DC–DC converters for attaining high voltage gain; nevertheless, the stress on switch voltage and diode current escalates considerably with an increased count of inductors integrated into the switched inductors network. In the classical multistage switched inductor converter, the switch voltage aligns with the output voltage, and the diode experiences a high current as the number of stages increases. This research recommends a DC–DC multistage converter for energy conversion and high voltage gain with low stress. In this paper, a novel multistage switched inductor converter is introduced and designed to attain higher voltage gain while mitigating the stresses on switch voltage and diode current. The proposed circuit is created by replacing the standard multistage switched inductor converter's possible diodes with power switches. All of the switching devices are connected in such a way that the output voltage and input current are shared by all of the switches and diodes, respectively. As a consequence, the voltage stress on switches and the current stress on diodes are comparatively low, resulting in a high efficiency compared to a typical multistage switched inductor converter. It's interesting to note that the proposed converter and a typical multistage switched inductor converter both require the same amount of components. Different operation modes, analysis, a non‐ideal model, and a comparison of the suggested and recently constructed converters are discussed. The effectiveness and performance of the circuit are validated experimentally.

Abstract In recent years, common ground (CG)‐type transformerless (TL) inverters have been paid more attention. However, the existing topologies have more voltage stress on either switch or on capacitor voltage or in both. This article proposes a novel five‐level TL inverter topology with a CG type and a voltage stress reduction on power components. The proposed topology offers less component count and a simple structure. Here, the quasi‐soft charging (QSC) technique is proposed to minimize the high charging current during the capacitor charge. Since the proposed topology is the family of switched capacitors (SC), the determination of SC and QSC is presented. A detailed comparison of the proposed topology with other recent five‐level topologies is presented, and the proposed topology's advantage is highlighted. Further, the performance of the proposed topology is verified in simulation software and verified in a scale‐down hardware setup developed for 400 W. The various experimental results are presented to ensure the feasibility of the proposed topology.