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In this paper, a nine-level inverter topology is proposed with the least number of switches and other components for fault tolerant (FT) operation. The proposed fault tolerant topology requires only one additional switch to execute the fault tolerant operation. The proposed topology also results in reduced total harmonic distortion (THD) as compared with other reported fault tolerant topologies for a 9-level output. A detailed analysis of the topology is presented and the fault tolerant operation is demonstrated under any single, double, triple, and quadruple switch faults using MATLAB/ Simulation and OPALRT hardware in loop (HIL) real time simulator. The proposed concept is validated for single and multiple switch faults and R-L load variation on a low scale laboratory hardware set-up. [ABSTRACT FROM AUTHOR]

Linear Motors are potential candidates for replacing traditional rotary motors in high-speed transit systems. Linear Switched Reluctance Motor (LSRM) is the widely researched motor for such applications. This paper presents a design for linear switched reluctance motor (LSRM) with an improved propulsion force profile. The proposed motor consists of moving translator for direct drive transmission, without the use of mechanical gears. The stator contains a split-teethed stator structure. The proposed motor has more translator teeth than stator teeth. This paper includes a new design methodology for the proposed combination of stator and translator. The motor is designed and analyzed using 3-D finite-element method (FEM). The proposed motor has been optimized using a parameter-based cumulative deterministic optimization algorithm (PBCDOA) for further improving the force profile. The FEM results demonstrate the effectiveness of the design procedure and better force performance of the proposed topology. [ABSTRACT FROM AUTHOR]

Recently, multilevel inverter (MLI) is gaining immense popularity due to reduced total harmonic distortion, lower electromagnetic interference, and high quality output waveform in high/medium voltage applications. The reduced part count (RPC)-MLI has attracted the researchers by providing higher number of output voltage level with reduced part count as compared to the classical topologies (cascaded H-bridge, neutral point clamped, and flying capacitor). But the discussion over their suitability for particular application is not yet explored completely. In this paper, some of the recently proposed RPC-MLI topologies are reviewed and analysed. RPC-MLI topologies are compared on the basis of number of switches, driver circuits, diodes, standing/blocking voltage across the switches, and switching losses for grid interfacing application. These topologies are simulated here under the same load and input source condition using real time simulator. [ABSTRACT FROM AUTHOR]