Search

In this article, a semi-analytical model for germanium absorber-based SOI-tunnel field-effect phototransistor at 1550 nm has been proposed. The model works efficiently for a wide range of intensities i.e. 10−2 to 102 µW/µm2 under the application of a very low gate voltage of 0.54 V. Exhaustive simulations using numerical ATLAS 2D device simulation tool with LUMNINOUS optical module have been carried out to propose the merit of tunnel field-effect transistors (TFETs) over metal oxide semiconductor field effect transistors (MOSFETs) for optical applications. The proposed TFET design provides a way to assist the ultrasensitive optical interconnects at a very low gate bias of 0.54 V with a maximum sensitivity of 1.5 × 107, responsivity of 270 mA/W, and detectivity of 3.5 × 1012 Jones at low power density of 0.01 µW/µm2. The TFET performance has further been improved by introducing a heavily doped pocket in between source and channel, which serves as a potential alternative for photodetector applications. The proposed pocket-doped TFET design offers significant improvements in device optical response with optimized sensitivity of 4.1 × 107, a responsivity of 772 mA/W, and a detectivity of 9.9 × 1012 Jones at an optical intensity of 0.01 µW/µm2, gate bias of 0.45 V, and drain voltage of 0.6 V. Transient analysis has been carried out to optimize the response time of the phototransistor for both Ge-gated conventional TFET and pocket-doped architecture and the fall time of ∼0.22 ms has been achieved. [ABSTRACT FROM AUTHOR]

This investigation examines the performance of AlGaN/GaN MISHEMTs having single-gate and dual-gate with different biasing combinations to explore the linearity in terms of gmpeak, gate voltage swing (GVS) and higher-order coefficients for intermodulation distortion for low-noise amplifiers (LNAs). In addition, the influence of distinct gate biasing configurations of DG-MISHEMT on current collapse (CC) (in response to OFF-state stress in drain) has been studied using TCAD simulations. It has been observed that drop in drain current value after the gate–drain voltages return to quiescent voltages (VGSQ, VDSQ) reduces for DG-MISHEMT (when both the gates are shorted together) to 9.1% as compared with 19.4% for SG-MISHEMT. Besides, the CC phenomena for DG-MISHEMTs (for shorted gates) exhibit a slight increase from 9% to 11.8% when workfunction increases from 4.1 eV to 5.2 eV for gate G2. Further, linearity in terms of GVS is observed to be doubled for AlGaN/GaN DG-MISHEMTs with both the gates connected together as compared with device with screen gate G2 shorted to source. Additionally, radio frequency performance has been studied in terms of cut-off frequencies fT and fmax and minimum noise-figure NFmin for AlGaN/GaN SG-MISHEMT and DG-MISHEMTs for different gate to gate distance i.e., LGG =100 and 200 nm. It is observed that NFmin is minimum for AlGaN/GaN DG-MISHEMT (with gate G1 floating and gate G2 is biased and LGG =100 nm) i.e., 1.13 dB with corresponding power gain of 18.7 dB at 50 GHz. [ABSTRACT FROM AUTHOR]

This paper systematically studies the reliability of non-uniformly doped Double Gate Junctionless transistor using ATLAS TCAD simulation. The reliability analysis is mainly based on the understanding of Band-To-Band-Tunneling (BTBT) current, lattice temperature, drain conductance and gate leakage current. Presented results show that higher source/drain work-function is beneficial in reducing tunneling current (1 × 10−9 A to 4 × 10−11 A @ Vgs = −1 V) but eventually it will also degrade electrostatic current significantly (∼3 order). Source/Drain length has also been varied during optimization and it has been observed that, shorter source drain extension region degrades the device reliability (i.e. higher magnitude of tunneling current (7 × 10−9 A @ Vgs =−1 V for LS = LD = 5 nm)). Different doping profile considered for performance assessment are: uniform, step (i.e. low–low–high and high–high–low etc.) and different configurations of gaussian doping profile. Minimum variation in tunneling current with negative gate bias, i.e. ∼ 1 order has been seen from the device having uniform doping 1019 cm−3 but at the cost of significantly high off-state current (2 × 10−9 A @ Vgs = 0 V) and tunneling current (2 × 10−8 A @ Vgs = −1 V). Thus, instead of using uniform doping, step type profile (i.e. Case A) is the better choice which results in lower tunneling current (1 × 10−9 A @ Vgs = −1 V), moderate lattice temperature (326) and better Ion/Ioff ratio (243 × 108). Device lattice temperature has also been controlled by using step A doping profile even at the higher operating temperatures due to lower Self Heating Effect. [ABSTRACT FROM AUTHOR]

Dopingless tunnel field effect transistor (DL-TFET) exhibits a great potential for lowering the sub-threshold current and hence increases the ION/IOFF ratio because of its electrostatically doped source and drain. An analytical model for double gate dopingless tunnel field transistor (DG-DL TFET) is developed, for the first time, by calculating the source and drain work-function-induced doping and using it for solving the 2D Poisson's equation in various regions. Electric potentials, energy band diagrams, electric field, corresponding drain current characteristics, and trans-conductance are obtained through the developed model and are validated by performing extensive device simulation for different gate and drain bias voltages. An excellent match between modeled and simulated results proves the efficacy of the developed model. The ION current obtained in Si-based dopingless TFET is 0.16 µA/µm, IOFF has reduced to 0.296 fA/µm and ION/IOFF obtained from the proposed device structure is 5.4 × 108, and the sub-threshold swing is 50.77 mV/decade. The DG-DL TFET is analyzed for resistive load inverter characteristics and has been further investigated for realizing digital logic functions by controlling the gates of the device independently. The realization of NAND gate requires one "p-type DG-DL TFET", whereas OR gate requires one "n-type DG-DL TFET". The implementations of single bias-controlled logics are useful as they render energy-efficient operations and simultaneously increase the packaging density. [ABSTRACT FROM AUTHOR]

ATLAS TCAD-based comparative investigation (mainly breakdown voltage, cut-off frequency and leakage current) has been presented in this work for different length of gate field plate and source field plate. 127 V of breakdown voltage has been achieved at 0.25 µm gate length having 0.8 µm gate field plate length and 1 µm source field plate length. By amalgamating source field plate, maximum cut-off frequency of 38 GHz was achieved at 0.25 µm channel length. Passivation layer permittivity and barrier thickness has also been used to optimize the device performance. The improvement in breakdown voltage is less prominent than the deterioration in cut-off frequency with the enhancement in passivation layer permittivity. Leakage current of source field plate HEMT has also been studied for different passivation layer permittivity. [ABSTRACT FROM AUTHOR]

Dopingless Tunnel Field Effect Transistor is a prominent device because of its low sub-threshold swing and fast switching speed. In this paper, DL-TFET is investigated for enhancing the performance parameters by applying different engineering techniques. The hetero-junction is implemented in the DL-TFET for increasing the ION current. Further, for reducing the ambipolar current and enhancing the ON-characteristics by introducing the non-uniform oxide layer, hetero-gate and then further optimization is done by varying the "x" compositions of In1-xGaxAs for source side material. The various staggered hetero-gate hetero-junction DL-TFET structures with different EBeff are comparatively investigated for analyzing their performance parameters. Among them, highly staggered Hetero-junction DL-TFET with EBeff = 0.374 eV shows better performance as lower threshold voltage, higher ION current, high transconductance and lower sub-threshold swing. So, the In0.45Ga0.55As/In0.25Ga0.75As based hetero-gate at TG = 4.2 eV and Θ = 7.59° heterojunction DL-TFET structure can be chosen for fast switching and advanced circuit application. [ABSTRACT FROM AUTHOR]

TCAD-based numerical investigation of RingFET has been presented in this paper for the detection of gas molecules. Sensitivity of the device has been assessed by calculating the change in off-state current with the change in gate work-function (which changes due to the presence of gas molecule). The behavior of the device has also been compared with the equivalent bulk MOSFET and it was observed that RingFET architecture shows 23% higher sensitivity against gas molecules than equivalent bulk MOSFET. Also, the degradation in device sensitivity with applied drain bias is higher in bulk MOSFET. Optimization in the sensitivity parameter has been done by using different channel materials like GaN, InGaN, and GaAs. Compared to GaAs and silicon, GaN-based RingFET is more sensitive towards gas molecules in the sub-threshold region (due to the wider band gap) besides having lower drain current than GaAs and silicon-based RingFET. [ABSTRACT FROM AUTHOR]

This paper examines the DC performance of Dual-Gate MISHEMT with different substrate material such as sapphire, silicon carbide SiC, and silicon. The performance parameters evaluated are threshold voltage, drain current, transconductance, and drain conductance. It is observed that DG-MISHEMT with the sapphire substrate and HfO2 gate dielectric results in positive threshold voltage shift from −4.7 to −3.8 V(∼19%) and also degrades the drain current as compared to the device with silicon nitride gate dielectric due to the reduced channel charge concentration. But the device with HfO2/Al2O3 gate stack maintains 182 mA/mm of IDS along with a positive threshold voltage shift of 14.8% as compared to DG-MISHEMT with Si3N4 gate dielectric and sapphire substrate. A similar performance has been observed with Dual-Gate MISHEMT with SiC and silicon substrate. The device, having the silicon substrate and HfO2/Al2O3 gate stack, shows a positive threshold voltage shift of ∼53%, but as a trade-off the drain current reduces to 158 mA/mm as compared to 183 mA/mm of the device at low drain bias with the sapphire substrate and Si3N4 gate dielectric. [ABSTRACT FROM AUTHOR]

In the present work, impact of Double Gate RingFET (DG-RingFET) has been investigated for better gate control and suppressed Short Channel Effects (SCEs) using ATLAS 3D device simulator. The analog performance metrics explored in this paper are drain current (Ids - Vgs), trans-conductance (gm), device efficiency (gm/Ids), and early voltage (Vea). In addition to this linearity behaviour of DGRingFET has been investigated in terms of third-order voltage intercept point (VIP3), third-order current intercept point (IIP3), third-order inter modulation distortion (IMD3) and results are also compared with the single gate architecture. The two-dimensional analytical model for DG-RingFET architecture has also been developed in this paper using parabolic approach. Moreover, the impact of technology variations like drain radii and position of drain, i.e. inside or outside the channel ring on the performance of DG-RingFET architecture has also been assessed. [ABSTRACT FROM AUTHOR]

The paper focuses on a comprehensive study of linearity and analog performance aspects of tunnel field effect transistor (TFET) device architectures such as dual material gate (DMG) TFET, hetero-dielectric (H-D) TFET, and dual material gate hetero-dielectric (DMG H-D) TFET. The parameters governing the device linearity and analog performance trends have been investigated in terms of transconductance (gm1), drain conductance (gd1), and second- and third-order derivatives of current, i.e.,gm2andgm3. Further the linearity performance of DMG H-D TFET has been optimized by tuning the metal gate length and high-kdielectric length. [ABSTRACT FROM AUTHOR]