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Renewable energy such as wind and solar is a clean source of energy that can be integrated with convention ways of producing energy. Power utility companies are looking at ways to integrate renewable energy with convention methods. The Central and South West (CSW) company is investigating the role of solar and wind energy in a utility system. Although CSW is a profit making company, the CSW renewable project is research based with a goal of helping the company understand renewable energy for future use. The CSW project gives the opportunity to investigate the problems that are encounter when operating renewable energy sources and also to come up with solutions. One approach to help analysis a system is to develop model for the system. A mathematical model for a grid connected wind farm is developed and modeled in Mathcad. A circuit model representing a wind connected wind farm is also developed. The transient behavior of a wind farm under different conditions is also investigated. The availability of the turbines at the wind farm is calculated and the results are presented. The caused of blade passing and its effect on the turbine power and current is also investigated. The problems encountered since the turbines were on line will also be discussed. A method was developed which shows why the hub height wind velocity can be used to evaluate the power output of a wind farm.

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In this thesis work, we will achieve a decent voltage and frequency regulation in an islanding microgrid. In this project we will consider an emergency situation that happens by a fault or blackout so the system will be disconnected from the grid, in a concept that a home (or residence) is equipped with a PV (Photovoltaic) system and Electric Vehicle (EV) with V2G/V2H (Vehicle to Grid or Vehicle to Home) capability. A Phase to ground Fault (blackout) will be applied to the system to make it islanded; Purpose is to challenge the voltage and frequency and reach the regulation for this designed control system. Droop strategy and virtual inertia will be utilized in a unique Unified control with Virtual Inertia, further by adding another unique approach to the MPPT algorithm, by designing an active power point tracking system to give the system an extra capability for controlling the power flow with setting a reference voltage for DC link. In the end, it will be simulated by utilizing a real-time simulator (Opal-RT). This system should achieve the stability by this control method with the ability for fast-tracking either under a temporary fault, load change, connections, and disconnections or a sudden change in PV’s power production. This Thesis details the designs and modeling of a Home with a particular load profile. Simulink of Matlab is chosen as the simulation tool based on the ability to evaluate both transient and steady-state behavior. Furthermore, OPAL-RT will be utilized by using the RTLAB software for our real-time results.

With a low capacitance density, bulky sized conventional aluminum electrolytic capacitors (AECs) are incapable of being included in latest ultrathin and wearable technologies. To meet the need for the filtering and smoothing operations in such devices, the need for high density capacitors is becoming critical. Electrochemical capacitors (ECs), or supercapacitors have a capacitance density larger than AEC by several orders of magnitude, but their charge and discharge rate (frequency) is limited up to approximately 1 s (1 Hz) or even lower. Therefore, these conventional ECs cannot play the roles of AECs that work at much higher frequencies for ripple current filtering, decoupling, high-frequency pulse energy storage, and other similar functions. Keeping this uprising necessity in mind, we have been conducting our research towards developing supercapacitor with kilohertz (kHz) ultrafast frequency response, while maintaining a high capacity density. After introduction on background, principle, and experimental methods, in chapter 4, pyrolyzed bacterial cellulose based electrodes were investigated to obtain kHz supercapacitors with exceptional high capacitance density. For the pyrolysis process, we adopted rapid plasma technique which was found very effective in producing high conductive carbon network. In chapter 5, we studied edge oriented graphene (EOG) grown encircling carbon nanofibers. This gave high volumetric capacitance density with above 10 kHz operation and outstanding stability. In chapter 6, we studied electrodes made from EOG coated carbonized cellulose microfibers. In order to take these devices one step ahead for high voltage (3 V) operation, an appropriate organic electrolyte was applied and kHz functionality was achieved. With these capacitors, we successfully demonstrated practical applications. The final step is, to achieve a wide temperature range operation, with even wider potential window (> 3 V), we applied ionic liquid electrolyte. A detailed study on temperature dependent performance of kHz capacitors with ionic liquid electrolyte was presented in chapter 7. In addition to these different carbon nanostructure based electrodes, we also studied vertically oriented MoS2 nanoflakes based electrodes for fast supercapacitors, which was presented in chapter 8.

The focus of this dissertation is to provide an in-depth understanding of the Model predictive control (MPC) technique of a three-phase voltage source converter for use in a fuel cell power system and a battery energy storage system (BESS) in grid-connected applications. The work presented here will help the researchers to further explore the flexibility of the MPC controller for design, analysis, and implementation in a power conversion system. With the growing demand for electricity, renewable sources of energy have garnered a lot of support from all quarters. The problem with these renewable sources is that the output from them is independent of the demand. The storage of electricity gives us an opportunity to effectively manage and balance the supply and demand of electricity. The second part of the dissertation studies the model predictive control technique to integrate a BESS with the grid. As an energy source, fuel cell power systems offer clean and efficient energy production and are currently under intensive development by several manufacturers. The viability, efficiency, and robustness of this technology depend on understanding, predicting and controlling the unique transient behavior of the fuel cell system. In the third part of the dissertation, the mathematical model of a fuel cell power system is designed and the system’s dynamic behavior at a grid-connected mode is discussed. The model predictive control technique is used to integrate the fuel cell power system with the grid. Consequently, this thesis focuses on a novel controller approach in order to obtain a more reliable and flexible three-phase inverter to integrate distributed energy sources with the grid.

The electric power grid is a very large and complex system that is a necessity in todays society. Traditional grid monitoring systems such as SCADA are being replaced by the Phasor Measurements Units due to their superior capabilities such as real-time and synchronize measurements. PMUs have many applications from gird protection to grid control, the down side however is that commercial PMUs have a high price tag staring at $2,400 and can go up to $10,000 USD. This large price can make it difficult to install a large number of PMUs to achieve full observability in a power grid. This thesis discusses the development of a low-cost single phase voltage PMU. Including is part selection, circuit design and programing methods. The PMU developed has an estimated cost range of $800 to $1,000 USD which is significantly lower than other commercial available PMUs. The PMU developed was tested by comparing a single-phase voltage measurement with a commercial PMU. The comparison showed that the low-cost PMU closely followed that of the commercial PMU with low errors in RMS voltage, frequency and phase angle. These results validate the accuracy of the low-cost PMU and its ability to be an alternative solution to the higher priced commercial PMUs.

There has been a rapid advancement in the technology for the development of high performance DC-DC converters. Resonant switching buck converter is one such power conversion topology and is designed to achieve maximum power density and the ability to regulate the output voltage for different input voltages. This thesis discusses the design of a zero voltage switching buck converter operating at 1MHz. The design is implemented on C5 process. The design accommodated input voltage in the range of 5V-8V DC and gives a constant output voltage of 3V. The output power level is 300mW.The simulation was performed on Cadence platform to verify the operating conditions of the proposed converter. Finally this resonant converter was compared to the conventional converter to verify the efficiency increase and switching losses decrease.

High-performance low power arithmetic circuit with reduced area is essential for advanced arithmetic processes. This thesis proposes a modification of arithmetic units using a new design technique which is called Complimentary Based Logic Design (CBLD). CBLD is the design technique which minimizes the number of gates hence improves the area efficiency of the overall circuit. This new design approach can be issued in an arithmetic unit in which multiple blocks perform conditional operations in parallel at one stage or in series with dependency. As multiple module performs in parallel only one module functions and others stays idle. CBLD reduces such idle modules by compressing all modules with a single module. The functionality of CBLD can be verified by implementing it on an optimized module of BCD adder and BCD adder/subtractor module. Comparison of CBLD design with its’ older counterpart shows significant area power and delay efficiency. Second Part of this thesis proposes a novel design of Carry select adder implementing CBLD. Proposed design of conditional BEC-CSLA or modified ripple carry adder is compared with recently published Area power and time efficient Carry select adders.

Generally when we consider any system that deals with human assistance, basic requirements about the system are, it should be simple, user friendly and portable. As a person whoever is using this system need not be aware of all the operations which are taking place behind the screen, one must consider an ease of access to the user. Most of the human assistance systems are proposed to assist physically disabled people. In this project, we have proposed and tested a system which is based on the navigation and capable of proving information about the possible mapping of obstacles in surrounding. System consists of three phases. First phase is associated with the signal generation of chirp signal and echoing. Ultrasonic sensor array is used for this phase of the system. Second phase is associated with the signal processing unit. National Instruments myRIO1900 which is a Re configurable-Input-Output device is used to access all the pins of sensors. This device is made portable by using external power supply and a Wi-Fi module. It can be accessed and programmed using LabVIEW platform. The third phase is the output phase. The output is represented in terms of 2D maps, generated using LabVIEW and 3D maps, and generated using MATLAB. Design is proposed which is capable of providing some additional features in the system which makes it more reliable and can perform multiple tasks at the same time.

In this thesis, we propose the new methodology to achieve the minimum glitch standard cell based design. The Standard cell library has been designed using the logic cells designed in the CDM logic style. The CDM logic style has been analyzed and compared with the conventional CMOS logic style with the FinFET devices in super-threshold operation. Standard cell library with FinFET logic gates in CDM and static CMOS logic style has been developed in various selected technologies (7nm, 10nm, 14nm, 16nm & 20nm) and used to synthesize the ISCAS’85 benchmark designs to evaluate the performance improvement. Synopsys silicon smart and library compiler tool has been used to generate the standard cell libraries using FinFET device models from PTM and design compiler to synthesize the designs with developed standard cell libraries. The simulation results shows that CDM based standard cell library achieve the average power improvement of 17-21% and average PDP improvement of 7-26% for all benchmark designs compared with conventional CMOS standard cell library in 7nm, 10nm, 14nm, and 16nm & 20nm technology node respectively. Hence we demonstrated that our low power standard cell design is comparable to the contemporary custom design optimization techniques used to save power in the design.

There has been a significant improvement in Micro grid Technology to utilize the local distributed sources and also to minimize the transmission losses. In certain cases of power blackouts they serve as main sources of power for some emergency loads. Traditionally A.C grids are preferred over DC grids to transmit power over long distances even though there are many problems associated with A.C grids such as frequency dip, voltage drop due to reactance, charging currents, leakage currents, low power factor problems, skin effect, Ferranti effect etc. because the voltages can be easily stepped up or stepped down using transformers. Whereas in D.C grid systems voltage conversion accounts for switching losses and equipment costs But at the micro grid level the supply voltages are low, and most of the sources are DC. The Rapid development in power semiconductor technology makes it possible to convert voltages in DC with low cost and reduced power losses. Most of the problems associated with A.C grid can also be overcome by moving to D.C grid.AC and DC microgrid models were developed in MATLAB/SIMULINK environment and the stability and transient analysis is performed during faults and sudden load variations on both microgrids in real time using OPAL-RT real time digital simulator. Effects of weak main grid on stability of both microgrids have been analyzed.

A microgrid is a combination of Distributed Energy Resources (DERs), Energy Storage, and Controllable Loads. It is connected to the main grid through the Point of Common Coupling (PCC). The main objective of this research is to optimize energy flow within a microgrid with regards to economic dispatch, reliability and availability in both grid connected and islanded modes. A microgrid with Combined Heat and Power (CHP), Natural Gas Generator, Diesel Generator, Solar energy, Wind energy, and Battery Energy storage with power ratings 1.5MW, 1MW, 1MW, 500kW, 500kW and 500kW respectively is considered. A critical load of 2.5MW and non-critical load of 500kW are considered in this research. The critical load is always supplied with power in both modes of connection of the microgrid. In the grid connected mode, the main grid supplies power to the non-critical load. Reduced Gradient Algorithm method is implemented to find the economic dispatch of a microgrid. The total cost of microgrid in the islanded and grid connected modes is optimized using MATLAB code. The total cost includes the operation and maintenance cost, investment cost, fuel cost, replacement costs, etc. The optimization of generation cost is obtained by minimizing the cost function of the system while meeting the load demand. The minimum total cost of the system is obtained by comparing different scenarios of the micro sources along with the change in the wind profile of the microgrid. An event oriented analytical method called Fault Trees Analysis (FTA) is implemented for reliability optimization using PTC Windchill Solutions software in a microgrid. The reliability of each component in each micro source of the microgrid is calculated using Fault Tree Analysis. The reliability of critical and non-critical loads is evaluated. The quantitative and qualitative results of Fault Tree Analysis are evaluated in order to interpret the results of fault tree. The sensitivity and uncertainty of the fault tree results for both critical and non-critical loads are deduced by calculating the importance measures such as Risk Achievement Worth, Risk Reduction Worth, Criticality Importance and Fussel – Vesely Importance. Then from the results the components that are sensitive and at high risk are deduced. This illustrates that they must be maintained well to increase the reliability. Then Economic Dispatch using Reduced Gradient Method is implemented for the optimization of energy in the islanded mode of microgrid using MATLAB. The optimization of operation and maintenance cost of microgrid is obtained by minimizing the cost function of the system while meeting the load demand. The Operation & Maintenance cost (O&M) of each micro source is considered in its cost function. The minimum O&M cost of the system is obtained by comparing different scenarios of the micro sources along with the change in the wind and battery profiles in the microgrid. Lastly, the availability of microgrid is optimized by considering the total cost and Operating and Maintenance cost of microgrid in both islanded and grid connected modes. Then, the availability and generation cost of each micro source is compared and optimized in islanded as well as grid connected mode of microgrid. In the total cost and availability optimization, the optimized availability and minimal cost are obtained in both grid connected and islanded modes of a microgrid by considering the change in the wind profile. While in the O&M cost and availability optimization, the profiles with change in the wind forecast and battery energy storage are considered to obtain the optimized availability and minimal cost in both grid connected and islanded modes of a microgrid.

In order for pulsed power systems to improve as a whole, the individual components they are composed of must continue to improve. One of the key components of pulsed power systems are switching devices. Traditionally, switching devices utilized were of spark/gas-type. These types of devices boast high voltage and high current operation, making them quite desirable for pulsed power applications. Gas/spark-type switching devices do have several intrinsic deficiencies; specifically high conduction losses which must be dealt with via exhaustive cooling systems, large physical size and high maintenance. Solid state switching devices are an alluring solution to these issues with gas/spark-type devices. This thesis details experimental evaluation and simulation of a 4 kV n-type gate turn-off thyristor (GTO) designed for pulsed power applications. The primary criteria of evaluation are rate of current change (dI/dt), turn-on delay time (TD), and resistance of the device during turn-on events (Ron(t)). The device is an n-type, asymmetric-blocking GTO manufactured by Silicon Power (Part No. 14N40A10) with a DC blocking voltage of 4 kV. A test circuit was specifically designed to minimize stray inductance in order to capitalize on the dI/dt capabilities of the device under test (DUT). Experimental data collected from resistance measurements was used to develop a one-switch approximate model for use in simulation. Results of dI/dt experiments provide a profile of DUT operation at gate currents greater than initial test conditions (IG > ITG); specifically dI/dt > 70 kA/μs is achieved at IG ~3ITG. Turn-on delay time of the DUT is also characterized.

Renewable energy is opening a new window to solve the energy crisis of the world. Several countries along with USA are introducing a lot of wind energy to the grid. Wind energy is a relatively new technology and needs a lot of research to ensure proper operation and stability of the grid. The research needs to be carried out to better understand the wind energy characteristics, identify grid integration requirements of the wind energy and stable operation during energy production. During this study, different issues were addressed from each of these three aspects. The study initially works to identify an optical iteration process to conduct power quality analysis of a wind turbine. Proper power quality analysis of the wind turbine ensures better understanding of the turbine characteristics and provides better system planning. In this research a new method is proposed to carry out the power quality analysis process in a faster way with less computational burden. The method is validated by using real time data available from one of the wind turbine of ALSTOM. Next, the study focuses on grid Short Circuit Ratio (SCR) estimation procedure for wind energy. The grid SCR is critical to determine the performance of the grid connected wind turbine. During this study, a novel method is proposed to estimate the grid parameters and thus the SCR. The new method is validated using simulation data available from PSCAD/EMTDC software and real time data available from a commercial wind farm. The method is also compared with already available solutions to ensure better performance. Finally, a new method is shown to provide frequency response from Doubly Fed Induction Generator (DFIG) based wind turbine during frequency deviation. The method integrates an energy storage device with the grid through the DC capacitor and uses the already available AC/DC/AC converter for power conversion. The energy storage provides the required frequency response during power imbalance. The method is validated using simulation results available from MatLab/Simulink software.

Industrial sized test systems do not always have flexible applications in university laboratories, although they do provide invaluable learning opportunities for students looking to work in the field of semiconductor test. This project focused on tailoring a recently donated National Instruments Semiconductor Test System (STS) for the Program for Semiconductor Product Engineering Lab at Texas Tech, including the selection of new, cost-effective equipment to extend the flexibility of the system and the design and test of a new device interface board. This board allows students to test a wide variety of devices for the classroom and general research projects.

Half-Bridge modules are essential to the design of power electronic systems such as dc-to-ac converters, synchronous dc-to-dc converters, and motor drivers. Silicon carbide (SiC) modules are a state-of-the-art solution for the development of high power and high temperature systems; this is due the material having several inherent superior electrical and thermal characteristics. Although SiC devices are state-of-the-art, they have not been fully evaluated and therefore have not become a widespread solution. In addition to the superior electrical characteristics of SiC, the thermal conductivity is also increased and therefore higher temperature operation can be achieved. It is crucial to develop an understanding of these devices by empirical measurement to fully understand the device and how it operates. In this thesis, the work required to develop a system for characterization of these modules is outlined. After a system has been developed, the DC characteristics of the modules will be tested vs. temperature and gate-to-source voltage when applicable. After the DC characteristics are measured for the modules, the switching characteristics will be measured vs. temperature, external gate resistance, and drain-to-source current in a classic clamped inductive double pulse test. This test is used to collect the required measurement data needed for analyzing the switching loss, reverse recovery of the body diode, and voltage overshoot of three different SiC half-bridge modules.

Improvement of yields in wafer fabs is one of the most important goals in modern industry. A good yield results in customer satisfaction, higher revenues and job security. These are not negligible aspects in a successful company. To accomplish them a healthy production with a reliable process flow has to be established in the fab. In the semiconductor industry, common problems as electromigration or stress induced voiding in metal interconnections should be reduced as much as possible or eliminated. Therefore test structures must be built to explore design marginalities for these problems and give further information about the reliability of metal interconnections. This thesis covers different test structures which should detect layout marginalities to avoid any kind of voiding in via in an established process flow and evaluates their reliability. Problems with stress induced voiding, via undercuts caused by a higher etch rate, and resist shrinking due to an oven bake process have resulted in customer returns and need to be investigated. For each of these problems different structures have been designed to find the marginalities. To recreate each issue, process steps thought to be the root cause and already excluded have been reestablished in the flow. The results give information about design marginalities for these issues in the past. The main problem lies in the recreation of the previously observed phenomena, since the wafer fab process is influenced by many seemingly unrelated parameters. Furthermore, reliability test structures have been designed to investigate the robustness of metal interconnections. Additional testing for these structures must be performed to finalize the outcome. In sum, further investigation using the test structures designed in this thesis will enable valuable insights into process robustness.

In order to determine the safe operating limits of SiC 9 kV SGTOs a test system was designed and built to stress the devices with high current density pulses (over 10X the rated densities) for greater than 10,000 high current discharges. A total of 7 SiC SGTOs were pulsed on the test system for over 250,000 pulses total. The data from these pulses is then used to calculate the device performance. The DC characteristics were monitored as part of the automated test system as well as on an Agilent B1505A high power device analyzer. Using a combination of the switching characteristic information as well as the DC characteristic curves it was determined that for 100 µs square pulses the devices could operate without failure up to 2.0 kA for an extended amount of time (>> 10,000 shots). Above 2.0 kA the device characteristics degrade rapidly. The cause of this degradation is explored in order to identify the primary failure modes associated with operating these devices at such high current densities. The cause of the observed failures are partially due to packaging breakdown at high currents as well as a permanent reduction in high level lifetime and mobility of minority carriers. Based off the current body of knowledge it is postulated that the observed reduction is due to the formation of stacking faults in the device which serve as deep level traps for the minority carriers.

In this study the current state of 12 kV, N-channel, 4H-Silicon carbide Insulated-Gate Bipolar transistors (IGBTs) was investigated for use in high voltage and high power applications. These next-generation switches offer many potential benefits to the Army including cost, weight, and space reductions in power electronics as well as an increase in mission capabilities. Silicon carbide provides superior electrical, thermal, and mechanical properties at high voltages, but its fabrication process is relatively new in comparison to silicon. For this work, two methods were used to understand the IGBT’s internal operation, to identify failure mechanisms, and to quantify the device’s performance. The first method involved the creation of a calibrated, physics-based model for device and circuit simulations. The second method involved the development of high voltage infrastructure to enable the collection of laboratory parametric measurements. The impact of this study will be advantageous to the development of robust devices, the creation of new applications, and the improvement of current processes and circuit designs.

This thesis documentation summarizes the testing results of an ASIC chip designed for piezoelectric energy harvesting system. The practical results obtained after testing were compared with the simulation results. The RF energy harvesting system was designed to convert the RF energy available in the atmosphere into useful electrical energy which can be used to charge a battery of capacity 50 uAh. This battery requires a voltage in the range of 4- 4.2V to get itself charged. The system includes the design of rectifier circuit, DC-DC charge pump, Low dropout regulator (LDO) and a clock generator. All these components were designed using 0.6um complimentary metal-oxide semiconductor (CMOS) technology.

Integrating modern sensors in an on-chip system by using CMOS analog and mixed-signal circuit design has been gaining significant attention in the recent few years. As CMOS process technologies scale down and the demand for battery-operated portable equipment increases, low power and low supply voltage becomes an important design criterion. This dissertation includes two aspects of the CMOS analog and mixed-signal circuit design for modern integrated sensor front-end research: a second-order inverter-based sigma-delta modulator as an analog-to-digital converter in the modern integrated sensor applications to realize the low power and low voltage application and a digital DC-tuning variable gain amplifier as an analog signal conditioning circuit in a Doppler radar motion sensor application to solve the DC offset issues. In this dissertation, one of the research works focused on the design of the low voltage and low power sigma-delta modulator and its implementation in the smart sensor applications. The presented sigma-delta modulator uses a simple inverter to replace the operational transconductance amplifier in the traditional integrator block in the modulator. The supply voltage can be less than the summation of the threshold voltage of both PMOS and NMOS transistors in the inverter. Hence, the power consumption is reduced. Low-voltage-low-power dissipation of the circuit in each block is desired to avoid circuit self-heating in the temperature senor application in order to maintain the accuracy of the temperature sensor. Two second-order inverter-based sigma-delta modulators with feedback topology and with feed-forward topology were designed, fabricated and tested respectively. The second-order inverter-based sigma-delta modulator with feed-forward topology was implemented with a scattered relative temperature sensor system in a single chip. The experimental results demonstrate the low voltage operation of the inverter-based sigma-delta modulator and the sensing accuracy of the temperature sensor system by using the inverter-based sigma-delta-sigma modulator. In most of the traditional miniature Doppler radar systems, ac coupling is adopted between the radio frequency (RF) front-end and baseband amplifier to block the dc offset due to clutter reflection. However, ac coupling causes distortion to low frequency signals and loses the dc information, which represent slowly changing or stationary moment of the target. A DC-coupled radar sensor system using a variable gain amplifier with software-configured digital tuning architecture is presented in this dissertation to realize dc tuning and dc offset calibration. Furthermore, to process the output signals from the variable gain amplifier, a low voltage-low power inverter-based second-order sigma-delta modulator has been implemented in this sensor application. The frequency of mechanical motion can be detected from the spectrum of the output digital bit stream from the modulator presented here without a decimation filter, which can significantly reduce cost and power consumption. Experiments show that the presented digital dc–tuning architecture using variable gain amplifiers can completely relieve the radar sensor from circuit saturation and the inverter-based sigma-delta modulator can perform under low voltage and low power to accurately detect the movement frequency of the target. Both the presented VGA and modulator show great potential for integrating the whole Doppler radar sensor system into a low-power high-accuracy single chip in the future.

Gamma radiation detection has been part of research for a long period of time. Being able to detect gamma radiation when being exposed to radiation is a must. The gamma detector I have built will demonstrate that it is capable of detecting gamma radiation with a low budget. We were able to build and test a gamma detector. The circuit was tested with two different source types of gamma radiation. I will show that detector is efficient with a 42mCi source and can detect a smaller source of up to 1uCi.

This thesis presents a Blender System Truck used in land fracking operations. Its functioning is reviewed, a mathematical model is created in MATLAB to simulate its dynamic characteristics, and then a control law is designed, synthesized and simulated. A complex process control is installed on a Blender Truck to mix in real time, large amounts of slurry, which is then fed into a well head for fracking operations. The slurry is made from water, sand and chemical additives. Each of these components is poured into a mixing tank in precise quantities to maintain the output slurry at a constant density. Density cannot change over +/-5%.

The purpose of this research is to create an automated method to collect bench data for Automatic Test Equipment (ATE) tested parameters in order to identify correlation osets if any on critical device parameters and to identify root causes of these correlation osets. The devices under test are all single cell battery chargers that have stringent spec requirements over operating temperature range. In production test these parameters are tested for on the ATE and parts not meeting spec are screened out. Hidden correlation osets between ATE results and bench test results could mean that parts that actually lie outside specications could be shipped to end customers.

Nowadays, the reliability of wind turbine gearbox (WTG) is one of the biggest concerns remaining in the wind industry. WTGs have been prone to early failure rather than any mechanical part of modern wind turbines and are subjected to torsional and non-torsional loads which are not yet properly assessed. They are reported to fail within three to seven years, as opposed to the expected twenty years of operation. Their downtime and maintenance process is the most costly of any failure of subassembly of WTs. To improve the reliability of WTGs, a novel Probabilistic MultiBody Dynamic Analysis (PMBDA) framework has been developed and implemented. Gears and Gear systems, like any other mechanical system, have design parameter and loading uncertainties emanating from inherent randomness, measurement and manufacturing errors. However, state-of-the-art models of WTGs and wind turbine drive trains consider deterministic loading and design parameters. This research addresses the early life failure of gearboxes of wind turbines and inquires if a novel approach termed as PMBDA will have an impact on enhancing the reliability of gear systems of wind turbines. An implementation framework that amalgamates the two broad disciplines, probabilistic analysis and multibody dynamic analysis, has been developed, several loading, assembly and design parameters are considered as random variables and their uncertainty is quantified. Using multibody dynamics software called MSC.ADAMS, contact based rigid multibody NASA test-rig gear pairs, a rigid-body and flexible WTG’s high-speed-parallel-helical-stage gear pairs and a flexible WTG’s compound-planetary-helical-stage models, with variable loading, assembly and design parameters, were developed. An advanced fast probability integration methods and standard/advanced sampling techniques were implemented to perform a probabilistic analysis of tooth dynamic force, dynamic factor, root bending stress, tooth surface compressive stress and fatigue life of gears. Probabilistic sensitivities of the performance functions to several random variables were also determined. In addition to revealing system reliability or under-performance through probability of failure (Pf), PMBDA approach also helps designers to consider certain variables critically through probabilistic sensitivity results.

Traditional multi-cell battery packs use a fixed configuration to connect multiple individual battery cells in fixed con-figurations to achieve pre-determined voltage and current. Even with modern advances in battery chemistry and greater power density, this fixed configuration results in low reliability, low fault tolerance, and non-optimal energy conversion efficiency. This system of manufacture is hindering advances in battery performance. This paper proposes a novel scheme to manufacture batteries by individualizing cells. By changing the packaging and adding low cost circuitry, a single cell in a battery pack will be able to control its orientation with other cells in a system. The idea has potential to revolutionize the way in which battery systems are developed and controlled. By using Texas Instruments value line MSP430 microcontrollers, the cost of the system can be minimized. The use of these low cost microcontrollers makes it possible to monitor voltage and temperature levels on individual cells. Also, by utilizing the same microcontroller, the individual cell is capable of shifting individual battery cells from off state, to a positive or negative polarity. The ability to switch single cells will make it possible to create a multi-level DC output. This independent switching scheme will also make it possible to create a modified sine wave AC output. The possibilities of switching to negative polarity will double the peak-to-peak voltage of the AC waveform. The battery will also be capable of identifying and implementing only the cells that are in optimal condition. Using cells at optimal temperature and state of charge will prolong the life of each cell. A battery system that individualizes each cell into a replaceable package makes replacement of “dead cells” possible. These are the cells that currently cause traditional battery packs to be replaced. With such systems available, not only will efficiency of large multi-cell battery systems increase, but with replaceable cells the cost of ownership of a complete battery pack will decrease over the lifetime of the system.

This thesis work focuses on the design of integrated voltage-mode controlled synchronous buck converter to achieve high efficiency. Concept of DC-DC converters are discussed first and synchronous rectification techniques are used for the design. This design work can be used for single lithium-ion battery operated portable electronic system. The input voltage range of the converter is 3.5V-5V and the maximum load current can be as high as 950mA. A high switching frequency of 1MHz is used for the design to achieve smaller inductor and capacitor value as well as lower voltage ripple. The functional blocks of this designed synchronous buck converter include power stage circuit, compensated error amplifier, PWM comparator, dead time generation circuit and gate driver. Based on AMI0.5 um process, the whole circuit system as well as each functional block are simulated and the simulation results show that the output voltage ripple of this synchronous buck converter is smaller than 10mV. At 6Ω load resistance, the synchronous buck converter has efficiency greater than 96% and at input voltage of 3.7V, the synchronous buck converter has efficiency greater than 90%.

Today, the limits of petroleum resources (and rising gasoline prices) have globally become a reason for concern, and it is commonly thought throughout the world that current automotive technology will need to be adapted or replaced for the future. Efforts are underway worldwide to improve current vehicle technologies to make automobiles more fuel efficient, environmentally friendly, powerful, etc. In this context, EcoCAR: The Next Challenge was an international, collegiate vehicle engineering competition for North American colleges and universities sponsored by the US Department of Energy and General Motors Corporation, and others. Texas Tech University was one of the sixteen universities that competed in this three year collegiate advanced vehicle technology competition where teams were challenged to re-engineer a GM donated vehicle to achieve improved fuel economy and reduced emissions while maintaining consumer acceptability in the areas of stock performance, utility and safety. This dissertation presents an overview of the development of the vehicle design with industry standard vehicle development process (VDP). A two-mode hybrid powertrain was proposed to keep the vehicle performance, improve fuel economy and reduce the impact to the environment. The powertrain utilizes a GM 1.6L family 1 engine, a GM 2-mode front-wheel drive (FWD) transaxle and a 12.9 kWh A123 Systems high voltage battery pack. The proposed 2-mode hybrid electric vehicle was built by integrating the proposed hybrid powertrain into a GM donated vehicle. The design process started from the architecture selection with the use of PSAT software. Modeling and simulation of two-mode hybrid using model based design (MBD) process was performed. The Mathworks Simulink, SimDriveline and Stateflow provided an environment for modeling selected architecture and powertrain components. A vehicle performance target was established through vehicle technical specifications (VTS). Once model was verified in Software-in-the-loop (SIL), hardware in-the-loop (HIL) testing was performed with the use of a National Instruments PXI and a dSPACE MicroAutoBox (MABX). For the hybrid control algorithm development, a rule-based control method is used to consider both the 2-mode transmission dynamic model and the powertrain component specifications and constraints. For rapid control system prototyping, MABX was added as a supervisory controller to interface with the stock electronic control units to accomplish the desired hybrid control functions. In this way going from mathematical models to lab-based tests with HIL, then by moving to in-vehicle testing of the vehicle’s on board software, a realistic vehicle propulsion controller was developed. The proposed hybrid vehicle is capable of EV drive, regenerative braking, two electric variable transmission modes, engine auto-stop, and engine optimal operation. The prototype vehicle was tested on road to verify the simulation model, vehicle performance and fuel economy, the 2-mode transmission dynamic model and the hybrid control algorithm.

As the integration density and power density of modern very-large-scale-integrated (VLSI) circuits keep increasing, on-chip overheating issue is causing performance degrading and even function failures. Thermal management system is therefore integrated on-chip, where a temperature sensor is the most important function block. As the process technologies keep shrinking down and the demands for battery operation increase, low voltage operation has been an important design criterion. Temperature sensors with low and process scalable supply voltages are proposed in this dissertation. Specifically, subthrehsold MOSFET diodes are used as sensing devices. Compared with traditional bipolar junction transistor (BJT) diodes, MOSFETs working in subthreshold region exhibit similar temperature characteristics but need lower and process scalable supply voltage. Other blocks in the sensor such as the error correction amplifier, ADC, etc, have been re-designed to support low voltage operation. Device mismatches in the sensing diodes, the current mirrors, the error correction amplifier, etc, result in large error in the measured temperature, which leads to worse accuracy performance than the BJT-based temperature sensor. Various error correction techniques have been studied and implemented in the dissertation in order to minimize the mismatch induced error and improve the sensing accuracy. Furthermore, scattered temperature sensors with multiple remote sensor nodes distributed across the chip are proposed for modern multi-core digital processer, where multiple hot spots need thermal monitoring simultaneously. Relative inaccuracy has been evaluated and optimized in the scattered temperature sensor which is necessary to improve the performance of the processer through load balancing. Several prototype designs have been taped out in different process technologies and the experimental results demonstrate the low voltage operation as well as the improved sensing accuracy.

This thesis discusses the design and implementation of several discrete and monolithic envelope modulator designs for use in high efficiency envelope tracking power amplifiers.

This thesis report summarizes the design and analysis of the power conditioning circuits of a piezoelectric energy harvesting system. Commercial piezoelectric generators with a frequency range of 26 – 205 Hz were used to convert kinetic energy to electric energy. A 6 stage AC/DC charge pump designed by a previous student was redesigned to multiply the output voltage of the piezoelectric generators. A Low Dropout Regulator (LDO) was designed to create a steady dc output voltage of 4.1 V. The ASIC for this system was designed using 0.6μm complementary metal-oxide-semiconductor (CMOS) technology.

The project aims at designing the receiver end of a wireless power transmission system which consists of an ac to dc rectification system and a voltage level shifting system. The ac to dc rectification system consists of a Full Bridge Rectifier and a Shunt Regulator. The Shunt Regulator makes the system insensitive to voltage fluctuations and thus helps to make it more stable. The dc to dc rectification system consists of a Multi Resonant Buck Converter used to step down the voltage to the desired level. The power semiconductor modules have shrunk its size but the passive components (inductors, capacitors) used for filtering still occupy a considerable area. This paper focuses on reducing the size of these components by increasing the frequency. However higher frequency also poses the problem of higher switching losses. The use of resonant components like Multi-Resonant Buck and Boost Converter help minimize the switching losses further increasing efficiency and ensuring maximum power delivery. Also conventional gate drivers used cause a lot of power dissipation due to conduction losses and also involve the problem of shoot through. This project also makes use of a Resonant Gate driver to drive the Buck Converter minimizing shoot through and conduction losses, thereby increasing efficiency.

With the interest in RF (radio frequency) and HPM (high power microwave) directed energy applications growing, rapid capacitor charger technology has advanced to meet the input power management parameters to these systems. Current mode control is seen as a desirable control method for the power inverter to quickly charge the capacitor bank. An analog current mode control platform has been demonstrated at the P3E (pulsed power and power electronics) Laboratory. Engineering design advancements have resulted in optimization for power density. Further developments in current mode control have yielded: 1) a current mode control approach that allows multiple inverters to be stacked for high power (100 kW capability) applications 2) a digital peak current mode control approach that allows for adaptive slope compensation with a reduction of analog peripheral circuitry. The method to handle slope compensation for the peak current mode control has also progressed along with the hardware developments. To artificially adjust the current upslope into the CS pin of the analog IC, the initial use of a BJT emitter follower matured into an op-amp circuit for a more eloquent solution. . The digital peak current mode control was then implemented with a dsPIC controller and demonstrated specifically with a pulse forming network charging application. The digital control method continuously monitors the peak output current and adjusts the current limit with relation to the PWM duty cycle. The continued development of these control methods has led to a digital control platform that shows improvements over the analog method while still providing peak current mode control with stable operation at duty cycles greater than 50%.

This dissertation presents the design insights towards the realization of a fully monolithic ratio frequency (RF) cascode silicon (Si) BiCMOS power amplifier (PA) using the integrated envelope tracking (ET) technique (i.e., an “ET-PA” system). The dissertation begins with the introduction of ET as an efficiency-linearity enhancement technique by demonstrate its operating principle with the RF/analog/digital system co-simulations in SPICE and analytic analysis. The bandwidth and timing mismatch sensitivities are compared between the ET and the envelope-elimination-and-restoration (EER) techniques. A discrete linear-assisted switching envelope modulator is designed to investigate the overall ET-PA system performances using a monolithic SiGe common-emitter PA for broadband 3G/4G cellular signals with high peak-to-average ratio (PAR). The design trade-off of the switching frequency and the bandwidth of the envelope modulator on the ET-PA will be studied carefully to improve the linearity without degrading the overall efficiency. After the design insights for the circuits and the ET-PA system are well-understood, a fully monolithic SiGe BiCMOS cascode ET-PA will be implemented and presented. The proper circuitry topology and envelope shaping method will be investigated to successfully apply the differential cascode SiGe/BiCMOS PA into the ET-PA system. The integrated CMOS envelope modulator is optimized specific to this cascode PA, where its finite bandwidth and switching frequency are considered for achieving a high efficiency with minimal distortion and low spurious noise. Such optimization of the monolithic envelope modulator design for a fully-integrated ET-PA system is novel and different from almost all the works previously published in the literature. Further improvements of the fully monolithic BiCMOS ET-PA will also be carried out by: (1) the combination of ET and transistor resizing techniques for additional efficiency enhancement at the low output power regions for power saving; (2) the integration of the ET technique with the power-combined SiGe PA with an on-chip transformer for higher linear output power; and (3) the design of the monolithic Bipolar-CMOS-DMOS (BCD) envelope modulator for higher voltage and higher power applications. Based on the literature surveys, all the above monolithic ET-PA designs achieved state-of-the-art world record efficiencies for Si-based RF PAs for broadband high PAR signals without needing any predisotortion technique. More work is underway to increase the maximum output linear power to enable this revolutionary silicon-based ET-PA technology into real products space for various handsets and wireless applications.

False data injection attacks have recently been introduced as an important class of cyber attacks against smart grid's wide area measurement and monitoring systems. These attacks aim to compromise the readings of multiple power grid sensors and phasor measurement units in order to mislead the operation of the control centers. Recent studies have shown that if an adversary has complete knowledge on the power grid topology and transmission-line admittance values, he can adjust the false data injection attack vector such that the attack remains undetected and it successfully passes the residue-based bad data detection tests that are commonly used in power system state estimation. However, in this thesis, we explain that a realistic false data injection attack is essentially an attack with incomplete information due to the attackers lack of real-time knowledge with respect to various grid parameters and attributes such as the position of circuit breaker switches and transformer tap changers and also because of the attacker's limited physical access to most grid facilities. In this thesis, we have shown the minimum required information for a perfect false data injection attack. Then, we mathematically characterize false data injection attacks with incomplete information from both the attacker's and grid operator's viewpoints. Furthermore, we introduce a novel vulnerability measure that can compare and rank different power grid topologies against such attacks. To the best of our knowledge, this work is the first study to investigate false data injection attacks with line admittance uncertainty.

The demand for Internet and Cloud Computing services has been constantly increasing in the United States and elsewhere over the past few years. In response to the users' growing needs for Internet and computational services, major companies such as Google, Microsoft and Amazon have built several data centers at a variety of geographical locations, each one including hundreds of thousands of computer servers. There is a huge amount of power consumption associated with each data center due to running several servers, plus the electricity needed for the cooling and lightening equipments. While a large body of work has recently focused on reducing data center's energy expenses, there exists no prior work on investigating the trade-off between minimizing data center's energy expenditure and maximizing their revenue for various Internet and cloud computing services that they may offer. In this study, we seek to tackle this shortcoming by proposing a systematic approach to maximize a green data center's profit, i.e., revenue minus cost. In this regard, we explicitly take into account practical service-level-agreements (SLAs) that currently exist between data centers and their customers. Our model also incorporates various other factors such as availability of local renewable power generation at data centers and the stochastic nature of data centers' workload. Furthermore, we propose a novel optimization-based profit maximization strategy for data centers for two different cases, without and with behind-the-meter renewable generators. We show that the formulated optimization problems in both cases are convex programs; therefore, they are tractable and appropriate for practical implementation. Finally, we propose a workload distribution algorithm to utilize locational diversity of data centers that are built at different regions and may face different prices of electricity and different renewable power availability at different times of day. Using various experimental data and via computer simulations, we assess the performance of the proposed optimization-based strategy and show that it significantly outperforms two comparable energy and performance management algorithms that have recently been proposed in the literature.

I am grateful to Dr.Stephen Bayne for taking me as a graduate student early in my Masters. He has been a guide in every sense. His thoughts and insights to Electrical Engineering have only broadened my horizon in Electrical Engineering. His ideas and guidance have been instrumental in publishing three IEEE conference papers during my time here. His belief in my abilities and constant encouragement has made me work harder to achieve my goals. I would like to thank Dr.Michael Giesselmann for accepting to be the co-chair on my committee for my thesis defense. I thank Mr. Jerry Lopez for being a great mentor. He has been an inspiration throughout my Masters. His work ethics and commitment has been a great influence on me. He has set a high benchmark which has left me chasing constantly. Interacting with him has only made me a better person. I thank my friends Chaitanya S.K, Purvi Patni and Sanjar Hussain for encouraging me throughout my Masters. I thank Mr. Sandeep Nimmagadda for helping me with my research and internship. I thank Srividya for being my pillar of strength throughout my Masters. Without her it wouldn’t have been possible to survive the day to day hardships of life in USA. Lastly I would like to thank my parents and Almighty from the bottom of my heart for giving me the opportunity to study in the United States. Without their blessings none of this would have been possible.

The cost of testing in semiconductor industry is always growing because of the ever increasing complexity of semiconductor devices. The time required to introduce a device in market is reducing because of the highly competitive semiconductor industry. This puts additional pressure to develop efficient testing strategies to enhance productivity. Keeping the test cost low is another challenge to have greater profit margin for a device. This report takes up the challenge of shortening development cycle time while simultaneously bringing down the cost of test. The approach is by an efficient design of RASP (Remote Access Spring Probe) to be as generic as possible. The RASP is the interface between the device under test (DUT) and Automated Test Equipment (ATE), which in this case is the VLCT (Very Low Cost Tester) of Texas Instruments. This report also addresses about various design restrictions accompanying the tester, and layout modifications which were handled during the development phase of the RASP. The Mentor Graphics Design Capture tool was used extensively to develop the board. Finally, testing of the MAX3221 transceiver device on the VLCT using this board has been taken up and the results compared against the existing solution to verify its accomplishments.

High power electronics are approaching their limit with Silicon (Si) semiconductor devices, and a new material will soon be needed to take over in high stress and high temperature environments. Silicon Carbide (SiC) is a newly introduced material that may be the next step for a high power semiconductor material. Testing of this material has been done previously and this is a slightly different approach/continuation of that work. The work done concluded that SiC is a durable material that will be a good solution for high power semiconductor devices. This testing has been done to help further characterize and determine the viability of SiC JFET devices at room temperature and 150°C. The series of tests included are designed to highly stress the device and try to find out if any other properties of SiC are different from Si. The tests performed on these devices are millions of high current discharges through the devices at room temperature and 150°C. These conditions push the material to its limit and are far beyond what Silicon devices could handle. The results from all the testing is documented and analyzed to better understand how this new material reacts under high stress. The tests concluded that SiC is a very durable material and should be tested further to continue the advancement of the understanding and use of this material.

Quad Data Rate SRAMS (QDR SRAM) with a maximum speed of 550MHz are the latest technology QDRs in the market. These devices use the traditional wire-bonding interconnects ball grid array package technology with about 165 signal pins. There are next generation QDR SRAMS that are being designed which operates at speeds much higher than 550MHz and signal pins twice as much as that of the present QDRs. These new products would require a new packaging interconnect technology called Flip Chip in order to accommodate higher speed and increased number of signal pins. The reason for this is that Flip Chip shows improved electrical properties over wire-bonding technologies. In this thesis, we deal with the qualification of Flip Chip interconnects technology for a higher pin count device.

This thesis illustrates the transient performance of Silicon carbide (4H-SiC) Power MOSFET. Transient analysis enables the designer to understand the thermal stress the semiconductor device undergoes while dissipating high power for short period of time. Silicon carbide has been a material of interest in the development of High Power Semiconductor device especially due to its wide band gap and high temperature operational stability. This research focuses on the transient performance of vertical D-MOSFET structure at room temperature and elevated ambient temperature conditions. The 2D device model was created and simulated using Silvaco© ATLAS Technology Computer-Aided Design (TCAD) physics based simulation software. Physics based models were included to accurately model electrical device parameters like mobility, impact ionization, Lattice heating etc.. Orcad PSPICE student version and B2 SPICE A/D V4 LITE simulation tools were also used to verify the circuits before simulating it via Silvaco. In order to aid the research on MOSFET, a parallel plane Silicon Carbide PIN diode was first designed and simulated for its DC characteristics.

In production testing of semiconductor devices contact resistance can be significant between the output of the tester and the device pin. At each insertion of the device, the contact resistance changes which causes failure at the production level. Thus the purpose of this project is to calculate the contact resistance at the output of the tester and compensate at the specified pin. This idea also leads to the elimination of Kelvin contactors for small packages such as micro-QFN or sub 1x1mm packages to reduce the crowding of contactor pins on the device pads. This project will describe the ways of calculating the contact resistance using the ESD structure and also how to compensate for some of the critical test using this IR drop.

This thesis focuses on test and characterization of the Direct Attach passive cables by 8 port s-parameter analysis. The setup comprises of the Network Analyzer, multi port test set and Electronic calibration module. The module compliance boards (MCB) and a host compliance board (HCB) is used as in integral part of the experiment test setup for measuring the Direct Attach passive cables. MATLAB code is developed to test the Direct Attach passive cables for the SFF-8431 cable assembly specifications. The 10 gigabit SFP+ copper cable assembly specification parameters tested by this code are Difference Waveform Distortion Penalty (dWDPc), VMA Loss (L), VMA Loss to Crosstalk Ratio (VCR), Differential Output/Input Reflection Coefficient (SDDxx) and Common Mode Output/Input Reflection Coefficient (SCCxx). Failure analysis is done for all the cables under test and cables within the specification are sorted out as reliable ones.

The development of mobile Pulsed Ring Down Source (PRDS) arrays requires the ability to accurately determine the relative positions of array elements at distances, and in situations, where discrete measurements are not practical. At the frequencies of interest, centimeter level accuracy is required for the array to localize radiated energy at a given target location. Global Positioning System (GPS) devices and techniques are evaluated for the purpose of position acquisition. A Monte Carlo simulation was developed that takes into account the position error, the GPS timing error, and the switch jitter of the element. The error sources are combined and used a metric to evaluate and predict the array performance. Results of the GPS device testing, as well as previous work, are used as the input parameters of the simulation to determine their viability for use in the implementation of PRDS arrays. An array of low power solid state pulsed ring down sources are used to verify the results of the Monte Carlo simulations.

A computer model is developed to predict the output of a NonLinear Transmission Line (NLTL) based upon an input pulse, material properties and physical dimensions. Additionally, a test bed is developed with the goal of validating the computer model with regards to its level of accuracy in comparison with a real world system. The test bed is also designed to provide the apparatus for evaluating ferrite materials for their performance characteristics as components for NLTL applications. The resulting model provides two computation algorithms that successfully simulate aspects of NLTL operation. They require further development to improve their computational algorithms and to take into account more material properties in order to serve as a better tool for design of NLTL systems. The NLTL testbed results in a working pulser and diagnostic system, however the NLTL suffers from high voltage breakdown that prevents it from functioning as designed.

There has been a keen interest on Distributed Generation (DG) due to their restricted goals of meeting local loads and improving reliability of the overall system. Microgrids (MGs) are connected to the main grid through a Point of Common Coupling which separates the former from the latter. At the time of an intentional islanding or fault at the grid level, a microgrid is able to disconnect itself from the rest of the grid and operate by itself. A microgrid may contain both directly connected and inverter interfaced sources with different control configurations. When disconnected or islanded from the main grid there are various approaches to share the load, one of them being master-slave control where a storage device may become the reference DG to set the nominal voltage and frequency. When the main grid is brought back to normal operation, the microgrid is able to resynchronize itself to the main grid only when it meets certain conditions so as to avoid transients. All the microsources, power electronics and their control with power management were developed in Matlab/Simulink.

Most integrated circuits are evolutionary. This is especially true in the realm of system-on-a-chip (SoC) devices that combine multiple functions monolithically. Electronic systems that begin life as an entire printed circuit board often see smaller and smaller chip counts as designs mature. In some cases, functions will be combined into multichip modules that co-locate separate integrated circuits in a single package to provide additional levels of signal integrity and achieve cost reductions. This process continues through stages that culminate in the monolithic integration of these separate chips. The requirement to differentiate similar functions for different customers and applications results in families of SoC’s with similar but not identical capabilities. As parametric and functional testing become larger and larger contributors to total cost, avoiding duplication of effort is a key factor in maintaining competitive position and market share. The strategies involved in achieving economies of scale that can be realized by recognizing the similarities between family members while still providing for differentiation where required is a subject of great interest currently. This work traces the development of test capability in such a family through several generations. An approach that utilizes a motherboard to take advantage of the similarities between family members and is combined with specialized hardware realized in a series of daughter boards, and differentiated software as well is described through several design iterations. Debugging both hardware and software while looking for ways to streamline testing and further reduce test time and cost is detailed. The result is a cost effective approach to advanced device testing that does not compromise performance and provides for acceptable levels of fault coverage.

This thesis presents the design, development, and testing MEMS based Atomic Force Microscope (AFM). The system is capable of measuring the pull-off force measurements on different surfaces. The design is capable of producing a verticalresolution of ~ 2nm. The MEMS AFM consists of a stand-alone optical head, stepper motor controlled Z stage assembly incorporated with a MEMS XY stage. The shaft end of the stepper motor has a worm gear attached, which takes care of the Z movement.A commercial piezo actuator from Noliacis used. A LabView-based system is used to control the entire assembly. Custom made piezo amplifiers and transimpedance amplifiers are developed. The MEMS-based AFM has significance in finding the adhesion forces of a surface estimating the surface energy present on the surface. Surface forces in the order of ~21Nn and ~ 11nN are measured for a bare silicon substrate and hydrophobic coated MEMS XY stage. In addition, the results obtained are compared with the results of the force measurements performed on a commercial AFM system (Park XE-100). The signal to noise ratio for the system is calculated and is found to be 40 dB.

Increasing interest in high action wide pulse width applications for SGTO’s has heightened the need to develop a comprehensive simulation model. The model simulation would be able to predict device operation, aiding in the further development of the SGTO in high action wide pulse width circuits. A means to predict failure and device degradation would lead to higher reliability. The Thesis explores the development of a model for simulation in a high action wide pulse width circuit.

The development process pertaining to the design, fabrication, coding, and testing of multi-stage distributed energy plasma arc railguns are presented. In collaboration on an Air Force Office of Scientific Research (AFOSR) funded Multidisciplinary University Research Initiative (MURI) project, the Center for Pulsed Power and Power Electronics (P3E) at Texas Tech University is responsible for developing and investigating a functional scale model of a multi-stage distributed energy store (DES) railgun to analyze its effectiveness to suppress a restrike phenomenon and increase plasma armature railgun performance [1]. The term “restrike” denotes the formation of an electrical breakdown in the railgun bore some distance behind a traveling plasma armature. The formation of this secondary arc reduces the driving force on the primary armature and has led to a velocity ceiling of approximately 6 km/s on all breech-fed plasma armature railguns. Numerous solutions have been theorized as viable methods of restrike prevention but lack experimental verification. The primary objective of our research team within the MURI effort is to experimentally test Dr. Jerry Parker’s theoretical restrike suppression technique [2] that was developed at Los Alamos National Laboratory in the 1980’s. The project tasks are organized to identify potential problematic issues and verify theoretical concepts before implementation of a full scale system.