1. An improved non-uniformity correction algorithm and its hardware implementation on FPGA
- Author
-
Hanlin Qin, Huixin Zhou, Wen Zhigang, Kuanhong Cheng, Kun Qian, and Shenghui Rong
- Subjects
010302 applied physics ,Artificial neural network ,Computer science ,business.industry ,Frame (networking) ,ComputingMethodologies_IMAGEPROCESSINGANDCOMPUTERVISION ,Motion detection ,Condensed Matter Physics ,01 natural sciences ,Composite image filter ,Atomic and Molecular Physics, and Optics ,Electronic, Optical and Magnetic Materials ,010309 optics ,Computer Science::Computer Vision and Pattern Recognition ,0103 physical sciences ,Noise (video) ,business ,Ghosting ,Field-programmable gate array ,Projection (set theory) ,Computer hardware - Abstract
The Non-uniformity of Infrared Focal Plane Arrays (IRFPA) severely degrades the infrared image quality. An effective non-uniformity correction (NUC) algorithm is necessary for an IRFPA imaging and application system. However traditional scene-based NUC algorithm suffers the image blurring and artificial ghosting. In addition, few effective hardware platforms have been proposed to implement corresponding NUC algorithms. Thus, this paper proposed an improved neural-network based NUC algorithm by the guided image filter and the projection-based motion detection algorithm. First, the guided image filter is utilized to achieve the accurate desired image to decrease the artificial ghosting. Then a projection-based moving detection algorithm is utilized to determine whether the correction coefficients should be updated or not. In this way the problem of image blurring can be overcome. At last, an FPGA-based hardware design is introduced to realize the proposed NUC algorithm. A real and a simulated infrared image sequences are utilized to verify the performance of the proposed algorithm. Experimental results indicated that the proposed NUC algorithm can effectively eliminate the fix pattern noise with less image blurring and artificial ghosting. The proposed hardware design takes less logic elements in FPGA and spends less clock cycles to process one frame of image.
- Published
- 2017