Search

This paper describes the use of model-based design flow in the development of self-configurable image processing blocks over FPGAs. For this, some generic hardware architectures has been created and modified using a novel software proceeding using the specific characteristics of the different processing algorithms. This aspect, in addition to others configuration options of the blocks, allows the adjustment the FPGA resources consumption for a specific application. Also the automatic reconfiguration process is analyzed for a generic convolution block making some architectural comparisons over a Spartan-6 LX45 FPGA. [ABSTRACT FROM AUTHOR]

In this paper hardware implementations of cryptographic algorithms are integrated to the OpenSSL library which is used by the Linux operating system applications to protect TCP/IP networks. The selected algorithms are AES and the hash functions SHA-1 and SHA-256. These algorithms are implemented in hardware as coprocessors of Xilinx MicroBlaze soft processor core using the FSL interface for data exchange. These coprocessors are integrated inside the OpenSSL library considering Linux operating system multitasking, so a synchronization technique is selected to control the access to the hardware coprocessors. The speed gain achieved is measured using the OpenSSL's speed utility. Finally a virtual private network is configured using OpenVPN in order to compare the transmission rate using the coprocessors and without them. [ABSTRACT FROM AUTHOR]