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Since first proposed in JSSC [1], phase-switching modulation has been proved to be a viable transmission scheme. In this paper, we explored the maximum data-rate of phase-switching modulation and proposed a modified quadrature oscillator with a self-bias circuit to isolate the disturbance in power supply and ground. Dividers and filter are also optimized to minimize parasitic resistor and capacitor. The prototype is fabricated in a 0.18 μm CMOS process, with an active chip area of about 0.13 mm × 0.35 mm. The total power consumption of the modulator is only 2 mW with an energy efficiency of 80 pJ/Bit. This modulator has been successfully embedded in a direct-up conversion transmitter for medical application. • We present the system design of a phase-switching modulator with maximized data rate. • We proposed a modified quadrature oscillator with a self-bias circuit to isolate the disturbance in power supply and ground. • We investigated the designs for divider and filter to explore its design space and achieve optimal performance. [ABSTRACT FROM AUTHOR]

In this paper, we present a double-operating-mode adder which may be employed either in low-power (LP) or high-performance (HP) operating mode. The adder has a hybrid structure based on a c arry- l ookahead and c arry- p ropagate structures and hence is called CL-CPA. The selection between the two operating modes is performed through a mode selection bit during the operational period. The hybrid structure of the adder provides the feature of selecting the operating mode depending on the application deadlines and system available energy resources. The adder structure is realized by modifying the carry look-ahead tree (CLT) structure and then combining it with a carry propagate adder (CPA). During the LP mode, only the CPA structure is utilized while the CLT is deactivated through the power gating scheme. On the other hand, during the HP mode, the CLT structure is activated and the adder performs with its highest speed and power consumption using both CLT and CPA structures. The efficacy of the proposed hybrid adder is assessed by comparing its speed, power, energy, and area parameters with those of the other conventional adders obtained using HSPICE simulations for a 45-nm CMOS technology in a wide range of supply voltages. The results revel switching from the LP to HP operating mode leads to about 5.4X decrease, 2.5X increase, and 2.1X decrease in the delay, power, and energy of the 64-bit CL-CPA, respectively, averaged over the supply voltages. Also, the proposed hybrid adder provides flexibility on speed and power with an acceptable area usage for applications where both high speed and low power adders are required. [ABSTRACT FROM AUTHOR]