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Transistor threshold voltage (V t) scaling causes higher power consumption by increasing the subthreshold leakage and short-circuit currents in CMOS circuits. Leakage currents are significant contributors to the overall power consumption of digital systems-on-chip as threshold voltage, channel length, and gate oxide thickness are reduced with CMOS technology scaling. A new dual-pullup/dual-pulldown (DPU/DPD) repeater is proposed in this paper for higher energy efficiency in low-voltage and low-frequency applications. The standby mode leakage power consumption is reduced by 59.11% with the proposed clock tree as compared to the conventional 3 level H-tree operating with a power supply voltage of 1.0V in a 45 nm CMOS technology. The short-circuit currents are suppressed by selectively employing high-V t transistors in the repeaters. The clock network with the proposed buffer lowers the active mode energy consumption by up to 24.91% as compared to a conventional clock tree under equal silicon area constraint. Post layout results reveal that the statistical spread of clock skew in the DPU/DPD H-tree is also 20.60% lower than the conventional H-tree network. • A novel dual-pullup/dual-pulldown (DPU/DPD) repeater is presented for low leakage and high frequency clock distribution. • The minimum operating voltage of a clock tree is determined for achieving the lowest total energy consumption while satisfying the clock frequency and signal transition time (10% of clock cycle time) requirements at the leaves. • The influences of leakage currents on the total energy consumption of the clock trees designed with three different repeaters (conventional CMOS inverter, previously published SPLIT-IO, and the new DPU/DPD) are benchmarked at various supply voltages and frequencies. • The leakage power reduction provided with the DPU/DPD buffers is evaluated. • The impact of process parameter fluctuations on the clock skew of the novel clock distribution network is also characterized in this paper. [ABSTRACT FROM AUTHOR]

As the number of transistors on a chip surface increases, power consumption becomes more and more a serious concern. A promising solution to bridge the gap between resource-constrained gadgets and computation-intensive applications could be the approximate computing paradigm. This paper presents four efficient approximate full adder cells based on dynamic logic and carbon nanotube field-effect transistors (CNFETs). To the best of our knowledge, dynamic logic has never been deployed in the design of approximate full adders before. Comprehensive simulations and analyses are conducted to study the efficacy of the new circuits. Simulation results indicate remarkable improvements compared to state-of-the-art circuits. For instance, at 0.9 V power supply, our final proposed design improves the power-delay-area product (PDAP) metric by at least 63% compared to its peers. Moreover, the applicability of the proposed adders in the image sharpening application is examined by measuring peak signal-to-noise ratio (PSNR) and structural similarity index measure (SSIM) using the MATLAB tool. The proposed designs have also a reasonable performance in this regard. • Deploying dynamic logic (DL) in the design of approximate full adders for the first time. • Designing ultra-low area and energy consumption full adder structures. • Applying the proposed adders in the image processing application. [ABSTRACT FROM AUTHOR]

Since first proposed in JSSC [1], phase-switching modulation has been proved to be a viable transmission scheme. In this paper, we explored the maximum data-rate of phase-switching modulation and proposed a modified quadrature oscillator with a self-bias circuit to isolate the disturbance in power supply and ground. Dividers and filter are also optimized to minimize parasitic resistor and capacitor. The prototype is fabricated in a 0.18 μm CMOS process, with an active chip area of about 0.13 mm × 0.35 mm. The total power consumption of the modulator is only 2 mW with an energy efficiency of 80 pJ/Bit. This modulator has been successfully embedded in a direct-up conversion transmitter for medical application. • We present the system design of a phase-switching modulator with maximized data rate. • We proposed a modified quadrature oscillator with a self-bias circuit to isolate the disturbance in power supply and ground. • We investigated the designs for divider and filter to explore its design space and achieve optimal performance. [ABSTRACT FROM AUTHOR]

Medical implant devices have found widespread application in recent years. The Super-Regenerative Receiver has been one preferred architecture due to its power advantage over other architectures. We present a detailed analysis of the circuits and their equivalent models to be used in system level design of a Super-Regenerative Receiver in this paper. The design procedure is also demonstrated with a receiver design example. Designs were carried out in UMC 180 nm process with a center frequency of 416 MHz for MedRadio band. Errors between the simulation results of the proposed model and actual circuits are less than 1.6% for LNA characteristics and 7% for receiver output amplitude. 10 Mbps data rate was achieved with 432 pJ/bit energy consumption over 1.8 V power supply. The study is concluded with the simulation results of the circuits and the equivalent models. • Analysis of blocks of super-regenerative receiver is carried out. • Lumped element models of super-regenerative receiver blocks are proposed. • Results of analytic solutions as well as simulation results of models and circuits were presented. • As a benchmarking case, a super-regenerative receiver is designed and the design procedure is explained in detail. [ABSTRACT FROM AUTHOR]

In this paper, we present a double-operating-mode adder which may be employed either in low-power (LP) or high-performance (HP) operating mode. The adder has a hybrid structure based on a c arry- l ookahead and c arry- p ropagate structures and hence is called CL-CPA. The selection between the two operating modes is performed through a mode selection bit during the operational period. The hybrid structure of the adder provides the feature of selecting the operating mode depending on the application deadlines and system available energy resources. The adder structure is realized by modifying the carry look-ahead tree (CLT) structure and then combining it with a carry propagate adder (CPA). During the LP mode, only the CPA structure is utilized while the CLT is deactivated through the power gating scheme. On the other hand, during the HP mode, the CLT structure is activated and the adder performs with its highest speed and power consumption using both CLT and CPA structures. The efficacy of the proposed hybrid adder is assessed by comparing its speed, power, energy, and area parameters with those of the other conventional adders obtained using HSPICE simulations for a 45-nm CMOS technology in a wide range of supply voltages. The results revel switching from the LP to HP operating mode leads to about 5.4X decrease, 2.5X increase, and 2.1X decrease in the delay, power, and energy of the 64-bit CL-CPA, respectively, averaged over the supply voltages. Also, the proposed hybrid adder provides flexibility on speed and power with an acceptable area usage for applications where both high speed and low power adders are required. [ABSTRACT FROM AUTHOR]