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In this research, a new architecture of dynamic latch comparator is presented, which is able to provide high-speed, consumes low-power and low offset voltage. The proposed comparator has been verified in a design, a 12-Bit SAR ADC(Successive Approximation Register Charge-Redistribution Analog-To-Digital Converter). The comparator consists of two stage pre-amplifier and a StrongLatch. The pre-amplifier adopts an inverter-based input pair and a pair of capacitances in output stage to reduce noise. It is shown by simulation and analysis that the offset voltage is significantly reduced compared to a conventional dynamic latched comparator. The proposed circuit is designed and simulated in 28 nm CMOS technology. The results show that, for the proposed comparator, the speed is 2.37 ns and consumes only 426.6 μ W power, at 1.8 V supply voltage and 330 MHz clock frequency. This article presents two kinds of FoM(Figure of Merit) to prove that the comparator has excellent performance. • Analysis of offset source of differential pairs. • Optimize comparator design. • Validate the comparator design. [ABSTRACT FROM AUTHOR]

This paper presents a 16-bit 1-Msps successive-approximation-register analog-to-digital converter (ADC) with a split-ADC digital calibration scheme based on dynamic element matching. A multi-segment capacitor array with redundant bits is utilised for ensuring that missing-level errors are calibrated in the digital domain, reducing the area and power consumption. The key circuit modules are optimised, such as the low-power dual-mode cascade comparator and dynamic element matching control logic. The prototype is fabricated by a 0.18-μm CMOS technology, and it exhibits 170.47 dB figure of merit Schreier (FoMs), 15.04 bits effective number of bits (ENOB) and 119.50 dB spurs free dynamic range (SFDR). The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.422/0.536 LSB and −0.721/0.758 LSB, respectively. • A 16-bit 1 Msps SAR ADC is manufactured in 0.18 μm CMOS process with 170.47 dB FoMs. • A split-ADC digital calibration scheme based on dynamic element matching can improve the SFDR effectively. • A segmented capacitor array of 4 sub-capacitor arrays decreases the total capacitance of the high-resolution SAR ADC. • A dual-mode automatic zero comparator is utilised to reduce power consumption. [ABSTRACT FROM AUTHOR]