Search

Content addressable memory (CAM) is a hardware search engine (HSE) used for accelerating lookup functions in tagged cache, translation lookaside buffers (TLBs) and network routers. Despite its speedy search feature, augmentation of compare-evaluate blocks to storage units costs additional area. Activation of cells and matchlines (MLs) during search operations is responsible for huge dynamic-power dissipation. This paper proposes a shared ML scheme (SMS) based on a two-step evaluation CAM cell, in order to reduce ML transitions per word besides improving density in the comparison units. A 64 × 32-bit proposed SMS-CAM, using 45-nm CMOS technology, dissipates 1.06 fJ/bit/search and achieves 100.77-ps search time. At the cost of 6.55% sacrificial delay over a conventional CAM, the proposed CAM reduces 12.38% – 30.48% energy over a self-power off gating, the conventional and an early terminate ML precharge designs. Low energy-delay results better trade-off budget besides decreasing macro area in the SMS-CAM, which could be useful in search applications of network devices. • A 2-bit storage with common evaluation (2B-CE) involving two-step comparison • Two side-by-side CAM cells (one 2B-CE based cell) share one matchline (ML) node • Shared matchline scheme limits ML discharge to only 1 path per 2-bit mismatches • Lesser ML discharge paths with shared matchline scheme (SMS) saves dynamic power • N/2 proposed 2B-CE cells are designed in NOR-type ML to form an N-bit CAM word • SMS-CAM sustains high-speed searches owing to the parallel cells in NOR-type ML • Comparison of SMS-CAM with referred CAMs verifies performance and reliability [ABSTRACT FROM AUTHOR]

Single clock cycle access feature of content-addressable memory (CAM) suits well for high-speed parallel content search operation in data-intensive hardware search engines. The diverse applications span from accelerating databases and routing networks to processing images, implementing machine learning, processing biomedical data, and compressing data. Nevertheless, the CAM macro consumes significant energy due to the high switching of most match-lines (MLs), which comprise CAM words, during parallel access. Segmented ML schemes reduced power yet the cell and ML delay, and the extra sequential cycles affect search-speed. A novel selective-charging and adaptive-discharging (SCAD) scheme in the form of dynamic ML architecture is proposed to reduce CAM power consumption at no extra cycle cost. Additionally, a full-swing CAM cell forms the basis of storage and comparison-evaluation to lessen ML delay. Based on 45-nm technology under 1-V supply, the proposed 64 × 32-bit and 256 × 144-bit SCAD-CAM arrays dissipate only 0.45–0.46 fJ/bit/search energy and achieve high-speed. Compared to CAMs based on low-power ML schemes, viz., low-swing precharge, division and control, and master–slave, and the conventional CAM as baseline design, the SCAD-CAM reduces 13.49%–89.35% energy-delay. The average-power reduction of 1.8 × –2.4 × establishes the SCAD-CAM as a promising memory architecture for emerging search-intensive applications involving large-scale data workloads. • A CAM cell with strong comparison & sufficient evaluate-voltage to increase search-speed. • Selective-charging and adaptive-discharging (SCAD) scheme to reduce power consumption. • Search operation using SCAD match-line costs no additional clock cycle. • CAM design with SCAD-ML and full-swing CAM cell proves energy efficiency and error reliability. • High-speed operation besides low-power suits SCAD-CAM well in hardware search engines. [ABSTRACT FROM AUTHOR]

Content addressable memory (CAM) is a specialized search engine mostly used for speeding memory lookup in network devices. Despite fast searching, activation of all comparison circuits in every clock cycle costs huge power. Power dissipation is more severe in high capacitive NOR match-line (ML) because of higher precharge activity and multiple transitions in ML. This paper proposes a two-layer ML scheme to reduce power due to frequent ML switching between precharge and evaluation phases. The complementary charging property of P and N matching circuits of NOR cells are utilized with the help of a ML precharge and sensing (MLPS) block to charge up only the matched entry while the mismatched entries are held at pre-discharged levels. Also, charging up the first layer due to mismatch limits the discharge levels of the mismatched second layer. These techniques reduce precharge activity besides lessening evaluate-power. Based on a 45-nm CMOS technology, post-layout analysis of the 64 × 32-bit proposed CAM at 1-V supply shows 56% and 24% reductions in precharge-power over a conventional CAM and a gated-power ML sensing CAM, respectively. In addition, the total ML power saving of approximately 2× is achieved when compared to a high-performance master-slave ML and a local-NOR global-NAND ML based CAMs besides decreased macro area. With the help of a charge-hold and charge-up sensing scheme, the proposed design achieves a match function in only 223.52 ps and dissipates 1.42 fJ/bit/search favouring it to be an efficient energy-delay design among the compared designs. • A novel two-layer CAM architecture using complementary charging properties of P and N match-lines. • Mismatched MLs of longer layer are discharged to low-swing to reduce precharge levels. • Matched ML of final output changes its state while mismatched MLs do not change, lessens precharge-power and evaluate-power. • A sense amplifier senses the ML states quickly based on charge-hold/up scheme. • Comprehensive analysis and comparison with referred CAM designs to demonstrate power and delay improvements. [ABSTRACT FROM AUTHOR]

Design of associative memories such as content addressable memories (CAMs) is a challenging task as the demand of high search speed and low power are given the utmost importance. CAMs are wide spread in computing devices those require a precharge phase prior to every search. It lessens the frequency of search and consumes more power. Precharge free CAM (PF-CAM) is an alternative solution in reducing the power associated with matchline due to the void of additional precharge cycle. In this paper, an energy efficient precharge free CAM (EEPF-CAM) structure is proposed to reduce the power dissipation along with extra cycle time. The proposed structure of 32 × 16-bit size has been designed using predictive 45-nm CMOS technology and post layout simulations performed in SPECTRE at the supply voltage of 1 V. The architecture consuming 4.31 μW power dissipation, resulted in an energy competence of 0.66 fJ/bit/search. The requirement of energy of the proposed EEPF-CAM architecture is reduced by 23.43% and 85.71% compared to the existed low power precharge free (LPPF) and self-controlled precharge free (SCPF) CAMs respectively in single search. For 25 repetitive searches, an improvement of 72.73% and 92.72% in energy has been obtained compared to LPPF and SCPF CAMs. Evaluation time requirement in the proposed scheme is same as that of SCPF-CAM and is enhanced compared to LPPF-CAM. • A novel precharge free ML structure for low-power applications. • False match issue is eliminated with the absence of additional cycle time. It reduces short circuit power significantly. • Multi-search analysis and MC method are carried out to prove robustness of proposed design in practical applications. • Comprehensive performance comparison with existing precharge free ML structures that proved superiority of proposed design. [ABSTRACT FROM AUTHOR]