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A semi-foreground offset cancellation strategy is proposed for inter-stage residue amplifiers, RAs, in high-speed analog-to-digital converters. Conversion flow continuously proceeds and the main drawback of the regular foreground methods is removed. Based on a novel digitally-assisted technique the analog voltage which is resulted from the calibration loop can be reliably frozen for long time duration. Hence, Frequency of the correction loop can be considerably reduced and smaller power consumption is obtained, consequently. Another benefit is sensing and correcting the low-frequency components of the dynamic offset, thanks to the periodic correction of the tired RA. Monte-Carlo analysis with 100 iterations shows that the input-referred offset achieves to around 53 µV at one sigma while was 4.8 mV before correction. The proposed strategy can be utilized in a 13-bit ADC with peak-to-peak reference range of 1600 mV, where the input-referred offset is required to be less than half of one LSB amplitude. Total power consumption is 0.75 mW at 1.8 V supply voltage, including power of all components when the multiplexing and operating frequencies of the calibration loop are reduced to 100 Hz and 200 kHz, respectively. More than 22.5 dB and 11 dB improvement in SNDR and SFDR of a 13-bit pipeline ADC is achieved when the calibration loop is activated. Post-Layout simulations are performed at all process corners using the BSIM3v3 model of a 0.18 µm CMOS technology. [ABSTRACT FROM AUTHOR]