Search

Silicon Physical unclonable functions (PUFs) are regarded as emerging hardware security primitives that can be used for generating secret keys for cryptographic algorithms. Unfortunately, the reliability issues greatly limit the applications of most PUFs since ambient noises and aging issues may alter the output responses of the PUFs. In this paper, a novel error calibration technique (ECT) based on average sampling circuit (ASC) and self-checking circuit (SCC) is proposed for significantly boosting the reliability of PUFs. The primary role of ASC is filtering the ambient noises that may affect the output responses of the PUFs. In contrast, SCC rehabilitates the PUFs once aging issues damage the process mismatches within the PUFs. As shown in the result, a PUF with the proposed ECT is able to achieve a 99% reliability with a 50 Mbps throughput. • Regular PUFs have poor reliability issues due to the effects of ambient noises and aging issues. • Error calibration technique (ECT) is able to the improve the corresponding reliability significantly by filtering critical noises. • An ECT-based PUF offers a high throughput without causing much area overhead. [ABSTRACT FROM AUTHOR]

On-chip voltage converters such as low drop-out (LDO) regulators are capable of generating fast and scaled voltage levels against power analysis attacks (PAAs) due to the high bandwidths of feedback loops. Unfortunately, LDO regulators suffer from much power loss when they are utilized for outputting scaled voltage levels. In contrast, buck converters may achieve high power conversion efficiencies but are unable to generate output voltage with fast scaling patterns. In this paper, a novel hybrid voltage regulator that is consist of an LDO regulator and a buck converter connected in parallel is proposed to address the issues related with security against PAAs and power loss. The LDO regulator offers fast scaled voltage levels while the buck converter provides major load current. The result shows that the measurement-to-disclosure (MTD) value of a cryptographic circuit (CC) with the proposed hybrid voltage regulator maintains over 2 million with a 4.3% power loss. • An LDO regulator suffers from a high power loss with a high security. • A buck converter achieves a high power conversion efficiency with a low security. • A hybrid voltage regulator achieves both high efficiency and high security. [ABSTRACT FROM AUTHOR]

Modeling attacks such as machine learning attacks are pretty efficient in breaking hardware security primitives like silicon strong physical unclonable functions (PUFs). As compared to regular strong PUFs such as arbiter PUFs and lightweight (LW)-PUFs, subthreshold current array (SCA)-PUFs exhibit a better resilience against modeling attacks since they utilize the non-linear relationship between the subthreshold current and gate voltage of transistors to obfuscate the corresponding relationship between input challenge and output response. Unfortunately, the degree of non-linearity (DoNL) within SCA-PUFs is still not sufficiently high to resist against state-of-the-art modeling attacks. Therefore, to further enhance DoNL for resisting against modeling attacks, a new strong PUF architecture is proposed in this paper by embedding reconfigurable neural networks (RNNs) into SCA-PUFs. Mathematical foundations are established for finding appropriate RNNs that are able to maximize the DoNL of an SCA-PUF. As shown in the result, when state-of-the-art modeling attacks like Lagrange multiplier attacks (LMAs) are selected, the robustness of the proposed RNN-embedded SCA-PUF is enhanced over 20 times with less than 18.5% power and area overhead as compared to a regular SCA-PUF. • SCA-PUF utilizes the non-linear sunthreshold current of transistors. • SCA-PUF is quite vulnerable to advanced modeling attacks such as LMAs. • RNN-embedded SCA PUF resists LMAs by masking power side-channel information. [ABSTRACT FROM AUTHOR]