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This paper presents the use of a new structure of active inductor named cascoded flipped-active inductor (CASFAI) in a T -type high-pass tunable output matching network of a class-E RF power amplifier (RFPA) to control the output power and enhance the efficiency. The designed CASFAI behaves as an inductor in the frequency range of 0–6.9 GHz, and has reached to a maximum quality factor of 4406, inductance value of 7.56 nH, 3rd order harmonic distortion better than −30 dB for 0 dBm input power, while consumes only 2 mW power. In order to consider the performance of the proposed active inductor-based tunable output matching network on the output power level and power added efficiency (PAE) of RFPA, the CASFAI is applied as a variable inductor to the output matching network of RFPA. The overall circuit is designed and validated in ADS in a 0.18 µm CMOS process and 1.5 V supply voltage. The results indicate that by increasing the inductance value of the matching network in constant operating frequency, the PAE peak moves from high power to low power levels without any degradation. Therefore, it is possible to maintain the power efficiency at the same maximum level for lower input drive levels. [ABSTRACT FROM AUTHOR]

This paper presents a CMOS low quiescent current output-capacitorless low-dropout regulator (LDO) based on a high slew rate current mode transconductance amplifier (CTA) as error amplifier. Using local common-mode feedback (LCMFB) in the proposed CTA, the order of transfer characteristic of the circuit is increased. Therefore, the slew rate at the gate of pass transistor is enhanced. This improves the LDO load transient characteristic even at low quiescent current. The proposed LDO topology has been designed and post simulated in HSPICE in a 0.18µm CMOS process to supply the load current between 0 and 100mA. The dropout voltage of the LDO is set to 200mV for 1.2–2V input voltage. Post-layout simulation results reveal that the proposed LDO is stable without any internal compensation strategy and with on-chip output capacitor or lumped parasitic capacitances at the output node between 10 and 100pF. The total quiescent current of the LDO including the current consumed by the reference buffer circuit is only 3.7µA. A final benchmark comparison considering all relevant performance metrics is presented. [ABSTRACT FROM AUTHOR]

Abstract: This paper presents a current-steering approach to implement a fast transient response low-dropout regulator (LDO) based on a current feedback amplifier (CFA) topology. The circuit does not require any internal compensation capacitor, being stable for a wide range of output load currents [0–100mA] and a 1μF output capacitor. The CFA consists of an open-loop voltage follower with output local current–current feedback based on a level-shifted flipped voltage follower (LSFVF) which is instrumental to achieve high regulation and fast transient response. The inverting output buffer stage of the CFA together with current-mirror-based driving of the power pass transistor results in high PSRR. Post-layout simulation results for a 0.35μm CMOS process design reveal that the proposed LDO requires 59μA quiescent current at no-load condition and at full-load condition has a current efficiency of 99.8%. For a 1μF output capacitor, the maximum output voltage variation to a 0–100mA load transient with rise and fall times of 10 and 100ns is only 3mV, and the PSRR is smaller than −56dB over the entire load current range. [Copyright &y& Elsevier]