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The six‐switch inverter has gained significant attention due to its ability to achieve dual AC voltage outputs with fewer semiconductor power devices. However, with existing pulse width modulation (PWM) algorithms, the switching frequency of the two middle‐position power devices is twice that of the other four power devices at the upper and lower ends. Therefore, this paper proposes an improved PWM algorithm for the six‐switch converter based on the unipolar modulation principle. The proposed algorithm can significantly reduce the switching frequency of the two middle‐position power devices. Research results indicate that, under optimal conditions, the switching frequency of the two middle‐position power devices is as low as the frequency of the AC output voltages, and in the worst‐case scenario, it is only half the carrier frequency. Consequently, the efficiency of the inverter is effectively improved. Additionally, analysis results suggest that, given the same switching frequencies of power devices, the modulation algorithm proposed in this paper for controlling the converter also results in lower Total Harmonic Distortion (THD) for the output voltages compared to traditional modulation algorithms. [ABSTRACT FROM AUTHOR]

Summary: This paper proposes leaky least mean fourth (LLMF) algorithm for the control of five‐level series connected H‐bridge multilevel inverter (5L SCHB‐MLI). The SCHB multilevel inverter is a popular configuration due to its wide application for high‐power and medium‐voltage applications. The complete system comprising the grid, load, and compensator is modeled in MATLAB/SIMULINK. Prototype hardware is also developed in the laboratory for experimental validation. The 5L SCHB inverter is connected in a single‐phase power distribution system and controlled as a compensator. The voltage across both DC links of the H‐bridges is regulated to almost equal value by the proposed control algorithm. The closed loop system is designed to mitigate total harmonic distortion (THD) in the source current and improve the power quality of the proposed system. The system is analyzed under the steady state and dynamic state, and the results are also verified on the hardware prototype developed in the laboratory. The proposed algorithm is also compared with conventional least means square (LMS) algorithm and notch filter algorithm on several parameters. The paper discusses a detailed simulation and hardware analysis on the control of five‐level MLI topology. [ABSTRACT FROM AUTHOR]

Lossless image compression techniques shrink the image size to improve the transmission efficiency and reduce the occupied storage space while ensuring the quality of the image is lossless. Among them, the LOCO‐I/JPEG‐LS algorithm benefits high lossless compression ratio and low computational complexity and thus is widely used for various real‐time applications. However, due to the problems of the context dependency in the LOCO‐I, the parallelism in the algorithm is greatly constrained, which significantly limits the throughput and the real‐time performance of hardware implementations. Existing designs achieve more parallelism by using a lot of hardware costs or straightforward chunking with losing compression ratio. In order to trade off the parallelism and the compression ratio, this paper proposes a chunk‐oriented error modeling scheme for LOCO‐I, which enables parallelism in both compression and decompression and achieves a better compression ratio in chunks. Based on the optimized algorithm, a high‐throughput flexible lossless compression and decompression architecture (HFCD) is proposed, which achieves higher pixel per clock (PPC) with less hardware cost. Additionally, HFCD introduces a parameter sharing mechanism to enable random access of image chunks to improve the flexibility for decompression. Experimental results show that, compared with state‐of‐the‐art works, HFCD achieves 3.02–13.50 times improvement for the PPC of compression. For decompression, benefiting from our optimizations, HFCD achieves 22.4 times speedup compared to the software solution. [ABSTRACT FROM AUTHOR]

This paper proposes a novel generic modulo‐2 graph that can be converted to parallel prefix adders (PPA). Also, a conversion algorithm for converting the proposed graph to PPAs is proposed in this paper. The conversation algorithm can be applied on N‐bit Generic modulo‐2 graph, and this graph is converted to N‐bit PPAs. When the proposed conversion algorithm is applied to generic modulo‐2 graph, this graph is converted to Brent‐Kung, Sklansky, Kogge‐Stone, Harris, Ladner‐Fischer, Han‐Carlson, and Knowles adders. Moreover, PPAs are shown in trilinear coordinates to represent the final PPAs, which generic graph converted to them. Furthermore, the add operation is done by generic graph and also the correctness of add function of this graph is investigated by "Boolean decision diagram." [ABSTRACT FROM AUTHOR]

Summary: In order to achieve efficiency extremum of power conversion independent of parameter values and operational mode, an adaptive dual‐controller on‐line efficiency optimization method is presented in this paper. Firstly, based on tri‐modal analysis for four‐switch buck‐boost (FSBB) converter, efficiency extremum analysis is given and existed for such this converter. Then, adaptive dual controller on‐line efficiency seeking algorithm is shown to adaptive two variables for efficiency optimization and output voltage regulation. Furthermore, perturb and observe detector is described to realize control variables decoupling of dual‐controller and to prevent the instability of the whole system during the algorithm tuning process and to improve the algorithm speed of the dual controller. The proposed method is model independent and does not depend on the circuit parameter values. The detail implement of algorithm and performance analysis is given, and the experimental platform and experimental results are put forward to verify the effectiveness of the algorithm. [ABSTRACT FROM AUTHOR]

Wider linear modulation range, less switching loss, and simplicity are the goals pursued by various modulation methods of multilevel inverters. This paper proposes a new hybrid discontinuous pulsewidth modulation (HDPWM) strategy for three‐level neutral‐point‐clamped (3L‐NPC) inverter that can achieve the above goals to a certain extent. According to the position of the reference voltage vector and the actual situation of the neutral point voltage, different control modes and clamping types are selected. The neutral point voltage is controlled by DPWM strategy, which can not only greatly reduce the switch loss but also maintain the balance of the neutral point voltage and expand the linear modulation range. The implementation of the algorithm combines the advantages of carrier‐based PWM (CBPWM) and space vector PWM (SVPWM). There is no need to select the nearest three vectors (NTVs) and calculate their dwell time. Only the reference voltage needs to be modified according to the control requirements, and then by comparing the modified reference voltage with the carrier, the driver pulse required by the switching devices can be generated. Compared with the existing PWM methods, it is more simple and easy to implement. Experimental results verify the validity of the method. [ABSTRACT FROM AUTHOR]

Summary: This paper presents the extension of generalized parameter extraction method for direct circuit function generation in a fully symbolic form of rational expressions or a nested s‐expanded polynomial. The new formula for implicit extraction of parameters that allows effective factoring by grouping of determinants of circuits containing any linear models of active elements, such as controlled sources, nullors, and pathological mirrors, is proposed. The concept of nullor with parameter is used for implicit extraction. The rules of optimal selection of parameters for extraction are presented. The proposed algorithm of symbolic analysis is implemented in the CirSym program, which is available online. The paper discusses the results of automatic analysis of several large active circuits, as well as determinants of matrixes and passive topologies, in terms of compact size and minimization of the number of arithmetic operations. Experimental results demonstrate that the expressions of determinants derived by CirSym are more compact than the results of the factorization algorithms of commercial computer algebra systems. The comparison with several other symbolic analysis algorithms shows that CirSym is the only available program that provides the exact calculation of the symbolic function of large circuits in the s‐expanded form with every coefficient being a compact‐nested expression. [ABSTRACT FROM AUTHOR]

Summary: This paper proposes a power factor correction (PFC) method in a single‐phase AC/DC converter using a predictive control algorithm (PCA) through a boost DC/DC converter. The minimum value of the DC‐link capacitor has been evaluated on the DC distribution side for stable operation of the converter. The proposed technique can be applied to the cascade connection of the converters, that is, the uncontrolled rectifier with boost converter and load. The value of the minimum capacitance is obtained as a function of the reference voltage of the DC‐link capacitor, the frequency of the supply, the input power, and the maximum DC‐link voltage. The proposed design is applied to control the boost converter for PFC applications using PCA at the minimum DC‐link capacitor value. The calculated value of DC‐link capacitance has been reduced to a greater extent as compared to the conventional calculation of DC‐link capacitance. The converter operation with the designed value of DC‐link capacitance has been verified through the MATLAB and Typhoon Simulink environment, and an experimental prototype model is used for the validation by using the FPGA based Typhoon HIL‐402 kit. [ABSTRACT FROM AUTHOR]

Summary: This paper describes a fast and efficient hardware‐accelerated pseudoinverse computation through algorithm restructuring and leveraging FPGA synthesis directives for parallelism prior to high‐level synthesis (HLS). The algorithm, which is composed of modified Gram–Schmidt QR decomposition (MGS‐QRD), triangular matrix inversion (TMI), and matrix multiplication (MM), is synthesized and implemented on a field‐programmable gate array (FPGA). MGS‐QRD is restructured and augmented with parallelism directives prior to synthesizing the algorithm, which yielded an MGS‐QRD hardware accelerator with high throughput. Modifications to the current TMI algorithm were also proposed, in which the removal of redundant computational tasks was done in order to speed up overall operation. Data dependencies in the MM algorithm were carefully considered such that appropriate parallelism directives were inserted, and matching the data flow of MM with MGS‐QRD and TMI modules was also performed to accelerate the pseudoinverse computation. The results showed that the proposed pseudoinverse module is better than the naïve implementation which is composed of existing MGS‐QRD, TMI and a standard MM in terms of maximum frequency (1.24× speedup), hardware resources(48% of reduction of DSP usage), latency (23% reduction), and throughput (62% increase). [ABSTRACT FROM AUTHOR]

The main objective of this paper is to develop a hybrid predictor based on intelligence techniques for dynamic voltage restorer (DVR) to estimate the reference load voltage and self‐tuned voltage regulation to enhance voltage power quality issues. The best fitted predictor model is obtained by using the potential merits of metaheuristic algorithms coupled with Antlion Optimization (ALO) and Genetic Algorithm (GA). This article proposes ALO optimized multilayer perceptron (MLP) neural network (NN) control algorithm for appropriate selection of weights and biases to generate the subsequent switching signal with lower error rates for load voltage estimation. The ANFIS‐GA control algorithm is implemented for automatic tuning of fuzzy rules with fewer membership functions (MFs) to obtain the perfect ANFIS (Takagi–Sugeno) predictive models for effective DC and AC link voltage regulation. The proposed hybrid controller counteracts the drawbacks of traditional ANN such as early convergence, slow learning mechanism, less probability of local entrapment, and difficulties to achieve the estimated target under parametric uncertainties, namely, sag, swell, unbalance, and distortion. The accuracy of the prediction model is computed by considering the error indices for the training and testing data set. The result confirms that the hybrid system ALO‐MLP NN establishes satisfactory performance in extracting the reference with the least error values. [ABSTRACT FROM AUTHOR]

Summary: In this paper, we propose the use of the simplicial algorithm, originally proposed to implement piecewise‐linear functions, to compute a digital vector–vector multiplication (VVM) without multiplications. The main contributions of the proposed methodology are (a) an improved error propagation with respect to parameter quantization; (b) a more efficient digital implementation with respect to area, energy, and speed in the case of large number of inputs; and (c) an intrinsic capability to produce multivariable nonlinear processing. We show that when quantization of inputs and parameters are considered, the simplicial method achieves the same accuracy with fewer representation bits for the parameters, assuming the same quantization for the inputs. Actually, in the particular case of a large number of inputs, the simplicial method needs half the number of parameter bits of a linear combination plus one. [ABSTRACT FROM AUTHOR]

Summary: This paper presents the design and control of single‐phase five‐level cascaded H‐bridge multilevel inverter (CHB‐MLI) as a shunt active power filter (SAPF) unit to mitigate the various power quality (PQ) problems such as reactive power burden, injection of harmonics in the supply, poor power factor, and so on. The control of CHB‐MLI has been done using the normalized least mean absolute third (NLMAT) algorithm, which overcomes the shortcoming of conventional least mean square (LMS), normalized LMS (NLMS), and least mean absolute third (LMAT) algorithm. The control algorithm is designed in MATLAB Simulink, and its scaled down prototype model is developed in the laboratory to find the fundamental active component of load current and to mitigate the aforementioned PQ problems. The proposed system is tested for single‐phase grid‐connection, and it works satisfactorily under steady state and dynamic load conditions. A dSpace1104 microcontroller is used to test the proposed algorithm and to generate firing pulses. Besides, the detailed comparison in the context of mean square error (MSE), weights convergence and intermediate error with conventional LMS, NLMS, and LMAT algorithm have also been discussed. Moreover, the harmonic distortion observed in the source current is within stipulated IEEE‐519 limits. [ABSTRACT FROM AUTHOR]

Summary: A single‐input bipolar converter has been proposed along with a fast MPPT tracking algorithm. The proposed converter is used as an interface for PV panel to perform twofold task of effectively extracting the maximum power from the PV side and efficiently delivering the extracted power to the load. For effectively tracking the MPP (maximum power point) of PV panel, a modified perturb and observe (MP&O) algorithm has been proposed in the paper. Proposed algorithm works effectively even under fast variations of irradiation and ambient temperature. The proposed converter has been developed with a target application in DC nanogrid by providing two loading points with amplitude balanced bipolar outputs. Moreover, least input current ripple (compared with other conventional DC‐DC converters) aids the MPP algorithm in improving the tracking efficacy. As the proposed converter has synchronous switching operation at both output terminals referred to input side, the power conversion efficiency of the converter is very high. Two out of three switches used are ground referenced; thus, design complexity of the converter is greatly reduced. Proposed converter with the MP&O algorithm has been analyzed, and the simulation results are obtained using MATLAB/Simulink. A laboratory developed prototype is used to experimentally validate the proposed converter. [ABSTRACT FROM AUTHOR]

Conventional modular multilevel converters (MMCs) are widely used in high power applications due to their various astonishing advantages; however, they fail to achieve balanced capacitor voltage in DC operation. In this paper, a hybrid two‐stage modular DC–DC converter is proposed to solve the issue of unbalanced capacitor voltages. The proposed converter consists of a single‐phase half‐bridge MMC with half‐bridge submodules followed by a medium voltage valves‐based H‐bridge rectifier. The proposed converter is used in medium‐voltage applications such as feeding a DC‐load or interconnection between two DC grids of different voltage levels. The proposed configuration achieves successful DC–DC conversion with a low number of switches, a high conversion ratio with bidirectional power flow, low current stresses, soft switching across the second stage, and low switching losses. The operational concept and the control algorithm have been illustrated in detail. Finally, the effectiveness of the proposed DC–DC converter is evaluated based on simulation studies of MATLAB SIMULINK and a scaled‐down laboratory experimental test rig. [ABSTRACT FROM AUTHOR]

To provide multiple options for specific application in biosignal processing, the programmable Gaussian‐derived Gm‐C wavelet filter has been proposed. To realize the programmable characteristic, the analog wavelet base with one numerator term is constructed by using hybrid artificial fish swarm algorithm. Also, the inverse follow‐the‐leader feedback Gm‐C filter structure with a switch array is employed. By programming switches only, Gaussian and Marr wavelet transforms can be realized flexibly with all component parameters unchanged. The seventh‐order programmable wavelet filter is designed as an example. Simulation results show that power consumption is only 141.68 pW at scale a = 0.1, with dynamic range of 42.6 dB and figure‐of‐merit of 2.05 × 10−13. Due to the programmability, the proposed design method can implement two wavelet filters with very low circuit complexity. [ABSTRACT FROM AUTHOR]

Summary: In this paper we describe an FPGA implementation of the Scale Invariant Feature Transform (SIFT) algorithm. The FPGA is required as its a lightweight device which makes it ideal for vision‐guided hybrid neuro‐prostheses utilised for upper limbs replacement. SIFT point detection is needed for computation of coordinates of the object‐to‐grasp in a wearable multi‐camera system. A modified SIFT algorithm is proposed and an implementation of it into C/C++ language on Xilinx ZCU102 FPGA board. The proposed hybrid hardware/software solution is compared to other hardware or hybrid implementations of the SIFT algorithm and with the baseline software detector OpenSIFT. The algorithm optimised for FPGA gives an average precision of 0.84 and the average recall of 0.94 in SIFT‐point detection compared to the baseline. The proposed solution has lower dissipated power than other solutions like CPU or GPU, and it has better computational speed. This solution allows for processing medium‐sized images in real‐time with low power consumption. [ABSTRACT FROM AUTHOR]

Summary: Stable image matching is still a pursuit goal in the communities of computer vision and graphics because of many potential applications such as 3D reconstruction, object recognition, and visual tracking. In the case of 3D reconstruction, modern structure‐from‐motion methods depend heavily on image‐matching methods for recovering geometric models. Existing methods have tried to exploit various strategies to generate correct feature correspondences for 3D reconstruction. However, there are no efficient methods that can work well in the wild. To defend this drawback, in this paper, we design a stable image‐matching method for 3D reconstruction. The method consists of feature point detection, descriptor extraction, feature matching, and matching verification. Besides, we try to choose a stable algorithm for each module of the proposed method, in which the adopted algorithms are implemented in an optimized approach for acceleration. Finally, we conduct a systematic experiment on several benchmarking datasets to assess the performance of the proposed method. Experimental results show that the proposed method has both high matching precision and fast speed. [ABSTRACT FROM AUTHOR]

In this paper, we suggest basing the development of classification methods on traditional techniques but approximating them in whole or in part with artificial neural networks (ANNs). Compared to a direct ANN approach, the underlying traditional method is often easier to analyse. Classification failures can be better understood and corrected for, while at the same time faster execution can be obtained due to the parallel ANN structure. Furthermore, such a two‐step design philosophy partly eliminates the 'guesswork' associated with the design of ANNs. The expected gain is thus that the benefits from the traditional field, and the ANN field can be obtained by combining the best features from both fields. We illustrate our approach by working through an explicit example, namely, a Nearest Neighbour classifier applied to a subset of the MNIST database of handwritten digits. Two different approaches are discussed for how to translate the traditional method into an ANN. The first approach is based on a constructive implementation which directly reflects the original algorithm. The second approach uses ANNs to approximate the whole, or part of, the original method. An important part of the approach is to show how improvements can be introduced. In line with the presented philosophy, this is done by extending the traditional method in several ways followed by ANN approximation of the modified algorithms. The extensions are based on a windowed version of the nearest neighbour algorithm. We show that the improvements carry over to the ANN implementations. We further investigate the stability of the solutions by modifying the training set. It is shown that the errors do not change significantly. This also holds true for the ANN approximations providing confidence that the two‐step strategy is robust. [ABSTRACT FROM AUTHOR]

Summary: A fractional delay filter is used to increase the accuracy, preciseness, time synchronization, and stability of signal processing system. However, designing a fractional delay filter for a specified delay, without affecting spectral characteristics of the signal is challenging because of nondifferentiability and multimodal nature of its objective function. In this paper, a more accurate design technique has been proposed for designing fractional delay filters, based on a recently developed firefly algorithm and its improved version. The designed filters offer variable fractional delay. A novel symmetric structure of implementation has been used to design filters. The efficacy of the proposed technique is evaluated by considering a filter design example. The performance of the proposed technique is compared with the other exiting algorithm. The comparative analysis of finite impulse response (FIR) fractional delay filter design proves that the proposed algorithm has a smaller design error and an implementation complexity than the other reported existing algorithms. In addition to this, the designed FIR fractional delay filter is implemented on Xilinx Virtex‐7 for experimental validation. [ABSTRACT FROM AUTHOR]

Summary: This paper introduces a new hybrid control strategy to control the bifurcation of the delayed congestion model. The delay or gain is taken as the bifurcation parameter to analyze the characteristic root distribution of the linearized system. The stability and existence conditions of Hopf bifurcation are obtained. The results show that by selecting the appropriate method, the dynamics of the controlled system can be changed, and the nonzero equilibrium constant control parameters are maintained. It reveals that when such bifurcation is undesirable or desirable, the hybrid controller can delay or advance the onset of the intrinsic bifurcation. Finally, the case study illustrates and visualizes the effectiveness of the new control strategy in controlling Hopf bifurcation. [ABSTRACT FROM AUTHOR]

Summary: Many of the modern deep learning, machine learning, and artificial intelligence algorithms use adders, multipliers, and multiply‐accumulators (MACs) with mixed precisions. In general, fixed‐point and floating‐point adders, multipliers, and MACs are used in mixed‐precision hardware, such that the above algorithm can choose appropriate hardware for its processing. This paper proposes an efficient mixed‐precision MAC circuit that can perform fixed‐point and floating‐point operations. The proposed design uses Han‐Carlson adder with late carry or end‐around carry in its accumulator design; as a result, delay and energy of the circuit reduce by 21.46% and 22.54% respectively, when compared with the existing designs from the literature. [ABSTRACT FROM AUTHOR]

SUMMARY Real equilibrium solutions of electronic circuits are affected by deviation of real characteristics of devices from their nominal values, producing the displacement of solution points from their nominal position. In this paper, a method to determine all the equilibrium regions in which real equilibrium points may fall is presented. The analysis is based on the introduction of the so-called strip characteristics that represent the characteristics of devices affected by tolerances. They are modeled by polyhedral characteristics. Different situations may occur as tolerances grow. A nominal solution point may disappear, or on the other end, some solution point not present with nominal characteristics may appear. These possible events call for a classification of the equilibrium regions in either certain or uncertain, depending on the existence or not of an equilibrium point for any choice of real characteristics. The algorithm adopts linear programming techniques and a clustering algorithm. Copyright © 2015 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

SUMMARY The paper offers an algorithm for local and global parametric diagnosis in nonlinear analog circuits, including both identification of the faulty parameters and determination their values. The algorithm exploits a nonlinear algebraic type test equations which may possess multiple solutions, corresponding to different sets of the parameters values which meet the test. To find the solutions, the homotopy concept is applied. Since the test equation is not given in explicit analytical form, the simplicial method is used to trace the homotopy path. The proposed approach can be applied to a broad class of analog circuits, including the complementary metal-oxide-semiconductor circuits fabricated in nanometer technology. The developed diagnostic procedure has been implemented in DELPHI, whereas the required by the algorithm repeated circuit analyses are carried out using IsSPICE 4 and both environments have been joined together. For illustration, two numerical examples are given. Copyright © 2013 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

ABSTRACT Time-delay systems (TDSs) frequently arise in circuit simulation especially in high-frequency applications. Model order reduction (MOR) techniques can be used to facilitate the simulation of TDSs. On the other hand, many kinds of variations, such as temperature and geometric uncertainties, can have significant impact on the transient responses of TDSs. Therefore, it is important to preserve parametric dependence during the MOR procedure. This paper presents a new parameterized MOR scheme for TDSs with parameter variations. We derive parameterized reduced-order models (ROMs) for TDSs using balanced truncation by approximating the Gramians in the multi-dimensional space of parameters. The resulting ROMs can preserve the parametric dependence, making it efficient for repeated simulations under different parameter settings. Numerical examples are presented to verify the accuracy and efficiency of our proposed algorithm. Copyright © 2012 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

Summary: This paper presents an algorithm with low computational complexity for classifying and recognizing characters based on a random sampling and high‐dimensional binary spaces for the development of real‐time applications. Character classification is performed using uniform random sampling as the feature selection process, subsequently performing encoding as binary strings. Associative memories are commonly used as general classifiers with linear criteria to discriminate between data points. In most classifiers, the ability to efficiently detect class membership depends entirely on the expressiveness of the attributes used to encode the data. Each binary pattern encodes the distinct characteristics of several glyphs. Character features are represented as elements of a high‐dimensional binary space, where a criterion of the cluster is defined under the L1 metric. The reduction in computational complexity is analyzed. The reduction in the number of character features through random sampling techniques makes it feasible to manage all the character information in physical architectures; therefore, this approach might use resources on a hardware platform with integer operators typically implemented at the hardware‐register level. Finally, this approach is implemented in a parallel architecture Field‐Programmable Gate Array (FPGA) and tested using a Database (DB) of different fonts, including distortions, therein showing that the efficiency is comparable to the other well‐known approaches. [ABSTRACT FROM AUTHOR]

Summary: This paper proposes an all‐hardware architecture to perform the subpixel refinement operation in the scale invariant transform algorithm. Although the literature describes several hardware implementations of this algorithm, due to its complexity, most of them are based on simplifications of it. These implementations normally exclude the subpixel refinement stage, which, however, is an essential process to obtain accurate results in image matching applications.The architecture has been described in very high–speed integrated circuit hardware description language at register transfer level and synthesized on a Xilinx Zynq 7020 device. The latency of the proposed architecture to generate a refinement operation is 211 clock cycles, and the throughput achieved exploiting pipeline techniques is 64 cycles. The architecture uses fixed‐point data representation and has been tested with images from known databases, yielding very good performance compared with the floating‐point software implementation of the algorithm. [ABSTRACT FROM AUTHOR]

Summary: This paper addresses the most suitable in‐pixel analog memory bank for running a hardware‐oriented approach of the well‐known Pixel‐Based Adaptive Segmenter algorithm on CMOS vision sensors. The high number of memory accesses, typically up to 200 times, along with the long time elapsed before an analog memory in a pixel is updated, around 5 seconds at 30 fps, constrains the memory topology. This work assesses the impact of nominal and process nonidealities of the 3 main analog memory topologies, namely, open‐loop, closed‐loop, and integrator architectures for background subtraction over the CDNET14 database. This is the first step towards the implementation of a CMOS vision chip with per‐pixel processing to run the Pixel‐Based Adaptive Segmenter. [ABSTRACT FROM AUTHOR]

Summary: Greedy algorithms in the compressive sensing theory have been formed the essential method for pruning power amplifier (PA) behavioral models and digital predistorters (DPDs). However, the inherent batch mode of these algorithms limits their application in adaptive digital predistortion framework. In this paper, a powerful subspace pursuit greedy scheme combined with stochastic gradient descent adaptive algorithm is proposed to design a class of adaptive sparse DPDs. According to the given sparsity level, the proposed approach can obtain the sparse terms of DPDs and extract the corresponding coefficients adaptively. Performance improvement of the proposed method is validated by simulation results on the adaptive DPD excited by 15‐MHz 3‐carrier Long‐Term Evolution signals and 50‐MHz 16 amplitude/phase‐shift keying signals. Meanwhile, measurement results on a Doherty PA excited by 30‐MHz 3‐carrier Long‐Term Evolution signals are also performed to verify the advantage of the proposed approach. Simulation and experimental results show that proposed algorithm can efficiently construct the adaptive sparse DPD models with only a small number of parameters; both nonlinear distortions and memory effects in the PA can be almost completely removed. A comparison with the nonsparsity aware DPD techniques and batch mode compressive sensing pruning techniques has been demonstrated that the proposed method exhibit faster convergence, improving tracking capabilities and reduced computational complexity. [ABSTRACT FROM AUTHOR]

In this paper, an efficient and highly accurate algorithm for yield-aware design of pipeline analog to digital converters (ADCs) based on a four-step approach is presented. First, a general netlist is generated for the data converter building blocks. Then, using an evolutionary method, its best performance sizing is estimated. Finally, the yield gets enhanced to reach a desired value. With the same accuracy, the presented algorithm can achieve yield optimization by approximately five times less computational cost compared with a state-of-the-art MC-based method. The framework is applied to demonstrate a reliable converter with optimum performance, power consumption, speed and area overhead during a single running process. A prototype 10-bit resolution, 10-MS/s pipeline analog to digital converter has been simulated in a 0.18-µm 1.8-V CMOS process. Presented results, applying the proposed method, show important advantages in terms of accuracy and efficiency. Copyright © 2016 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

This paper presents new ideas and insights towards a novel optimal control approach for power electronic converters. The so-called stabilizing or Lyapunov-based control paradigm is adopted, which is well known in the area of energy-based control of power electronic converters, in which the control law takes a nonlinear state-feedback form parameterized by a positive scalar λ. The first contribution is the extension to an optimal Lyapunov-based control paradigm involving the specification of the optimal value for the parameter λ in a typical optimal control setting. The second contribution is the extension to more flexible optimal switchinggain control laws, where the optimal switching surfaces are parameterized by a number of positive scalars λj. Systematic derivation of gradient information to apply gradient-descent algorithms is provided. The proposed techniques are numerically evaluated using the exact switched model of a DC-DC boost converter. [ABSTRACT FROM AUTHOR]

The issue of testability, intended as a measure of solvability of the parametric fault diagnosis problem in analog linear time-invariant electrical networks, is addressed in this paper. Independently of the considered fault location method, such important metric provides information as to how many and which components can be diagnosed. For the reader's convenience and to set up an appropriate framework for our main achievements, our first concern is to rederive fundamental results concerning analog linear time-invariant electrical network testability hinging on multifrequency measurements. Then a novel algorithm for testability analysis is proposed, which is straightforward and able to circumvent the main drawbacks of formerly proposed methods, such as computational and conceptual complexities, proneness to roundoff errors, and vulnerability to particular cases. A computer program that implements such algorithm is also described. Moreover, the possibility of employing further simplified versions of the latter and their links with a previously proposed approach are discussed on rigorous bases. Finally, examples are provided, which show the effectiveness and robustness of the new algorithms, also by means of a comparison with the old ones. Copyright © 2015 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

New coding schemes are increasingly being developed to adapt multisensor and communication systems to the requirements of the current technological environment. In some cases, the practical implementation of these schemes involves a great amount of signal processing operations. In order to achieve and make suitable their use in different platforms, efficient algorithms are required to process coding. In the last years, a new kind of complementary sequences, known as Generalized Pairwise Complementary sequences, has been proposed. These sequences provide high noise immunity when they are applied to multiuser systems, as well as a low cross-correlation, which is convenient in those applications. The aim of this paper is to propose optimized generation and correlation architectures for Generalized Pairwise Complementary sequences that would allow to process a complete set using a reduced amount of operations. An analytical demonstration is provided, with a final comparison to evaluate the reduction with regard to other algorithms. Copyright © 2015 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

Knowing the Network Function (NF) pertaining to a certain input-output couple individuated inside a linear electrical network (LEN) is crucial, as it provides a synthetic and effective description of the input-output relationship and allows one to derive several key features of the subject system as well as to devise proper strategies to modify them. From a mathematical point of view, an NF may be expressed as the product of a real number, called the gain constant (GC), by a real rational function of the complex variables, whose numerator and denominator are called the zero polynomial (ZP) and the characteristic polynomial (CP), respectively, and may be obtained by calculating the determinants of proper matrices. However, when a design-oriented symbolic hand analysis is needed, calculating the said polynomials in this manner may turn out to be tediously cumbersome; and above all, such a route may fail to illuminate the way that their coefficients depend on the circuit elements. The same may be said of numerical computer methods, which are suited to providing a global description of the NF in the frequency domain rather than analytical expressions of its coefficients. In this paper, a method is proposed that permits one to obtain the ZP without calculating any determinants. With respect to other methods that achieve the same goal, the present one does not require prior calculation of the CP or a nullator-norator pair (NNP) to be compulsorily inserted in the subject circuit. Instead, it is based on applying the Andreani-Mattisson extension (AME) of the Cochrun-Grabel algorithm (CGA) for the calculation of the CP to a circuit obtained from the assigned one by inserting in the latter a proper dependent source. The nature of such new circuit allows the worker to employ the classical tools of LEN theory so as to make the analysis as simple as possible and often performable by straightforward inspection, without the need for possibly involved equilibrium equations. Moreover, it is shown how the same technique can be applied to a properly modified version of the original network in order to calculate the CP as well. In this case (not compulsorily but if judged convenient for simplifying the calculations), a NNP may be employed in conjunction with the dependent source. The proposed method once again allows one to exploit the classic tools of LEN theory so as to considerably, if not drastically, simplify the analysis associated with the direct application of the AME to the original network. Finally, the calculation of the GC (that completes the knowledge of the whole NF under study) as well as circuit degeneracy are discussed and practical examples of application of the proposed techniques are given. Copyright © 2013 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

ABSTRACT This paper presents a novel structure for constructing two-channel quincunx quadrature mirror filter (QQMF) banks. The analysis and synthesis filters of the QQMF bank are composed of two-dimensional (2-D) recursive digital allpass filters with symmetric half-plane support regions. Using the 2-D doubly complementary half-band property possessed by the analysis and synthesis filters, we facilitate the design of the digital allpass-based two-channel QQMF banks. For finding the coefficients of the 2-D recursive symmetric half-plane digital allpass filters, the design problem is appropriately formulated to result in an optimization problem that can be solved by using a weighted least-squares algorithm in the minimax ( L∞) optimal sense. The novelty of the proposed design method is that the designed 2-D QQMF bank achieves perfect magnitude response and possesses satisfactory phase response without requiring extra phase equalizer. Simulation results are also provided for illustration and comparison. Copyright © 2012 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

Aiming at the problem that it is difficult to accurately estimate the state of charge (SOC) of lithium‐ion batteries in the strongly nonlinear interval, a novel algorithm based on a fuzzy control strategy is proposed. It integrates extended Kalman filter (EKF) and ampere‐hour (Ah) integration accurately estimate the SOC of lithium‐ion batteries. First, the algorithm uses the advantage that the EKF algorithm has high estimation accuracy in the nonlinear interval and can solve the problem of the large error caused by the inaccurate initial value of the Ah integral algorithm. Then the fuzzy‐EKF‐Ah (F‐EKF‐Ah) is used to fuse the two algorithms of EKF and Ah integral. The fused algorithm can effectively solve the problems of the cumulative error caused by the sampling accuracy of the Ah integral algorithm and the large estimation error of the EKF algorithm in the strong nonlinear interval. Finally, the equivalent circuit model is used for analysis. The experimental results show that the improved algorithm can achieve high estimation accuracy under three experimental conditions. [ABSTRACT FROM AUTHOR]

Proper range and precision analysis play an important role in the development of fixed-point algorithms for embedded system applications. Numerical linear algebra algorithms used to find singular value decomposition of symmetric matrices are suitable for signal and image-processing applications. These algorithms have not been attempted much in fixed-point arithmetic. The reason is wide dynamic range of data and vulnerability of the algorithms to round-off errors. For any real-time application, the range of the input matrix may change frequently. This poses difficulty for constant and variable fixed-point formats to decide on integer wordlengths during float-to-fixed conversion process because these formats involve determination of integer wordlengths before the compilation of the program. Thus, these formats may not guarantee to avoid overflow for all ranges of input matrices. To circumvent this problem, a novel dynamic fixed-point format has been proposed to compute integer wordlengths adaptively during runtime. Lanczos algorithm with partial orthogonalization, which is a tridiagonalization step in computation of singular value decomposition of symmetric matrices, has been taken up as a case study. The fixed-point Lanczos algorithm is tested for matrices with different dimensions and condition numbers along with image covariance matrix. The accuracy of fixed-point Lanczos algorithm in three different formats has been compared on the basis of signal-to-quantization-noise-ratio, number of accurate fractional bits, orthogonality and factorization errors. Results show that dynamic fixed-point format either outperforms or performs on par with constant and variable formats. Determination of fractional wordlengths requires minimization of hardware cost subject to accuracy constraint. In this context, we propose an analytical framework for deriving mean-square-error or quantization noise power among Lanczos vectors, which can serve as an accuracy constraint for wordlength optimization. Error is found to propagate through different arithmetic operations and finally accumulate in the last Lanczos vector. It is observed that variable and dynamic fixed-point formats produce vectors with lesser round-off error than constant format. All the three fixed-point formats of Lanczos algorithm have been synthesized on Virtex 7 field-programmable gate array using Vivado high-level synthesis design tool. A comparative study of resource usage and power consumption is carried out. Copyright © 2015 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

For the lithium battery management system and real‐time safety monitoring, two issues are of great significance, namely, the ability to accurately update the model parameters in real time and to accurately estimate the state of charge and health. In this context, this thesis adopts the second‐order RC equivalent circuit model and the forgetting factor recursive least squares ‐ double extended Kalman filtering (FFRLS‐DEKF) algorithm with multi‐time scales and low‐pass filter. Forgetting factor recursive least squares is applied to conduct online parameter identification, and the traditional double extended Kalman filtering algorithm is optimized to evaluate the state of charge and model parameters in the micro‐scale and macro‐scale. In this way, the error caused by two different characteristics is reduced, and a low‐pass filter is added to optimize the fluctuation problem of the estimated value of the model parameters. According to the experiment results, the maximum error between the model simulation value and the actual value of the terminal voltage is 0.0459 V. If the initial value of the state of charge deviates from the actual value, the maximum errors under BBDST and HPPC conditions record 0.0235 and 0.0048, respectively, the forgetting factor recursive least squares ‐ double extended Kalman filtering algorithm with multi‐time scales and low‐pass filter is able to track the true value within 40 s. Furthermore, the lithium‐ion battery state of health both reaches 98% under the two conditions. In summary, the experimental analysis shows that the algorithm helps reduce the influence of initial values on the results, thereby reducing error accumulation and improving the robustness. [ABSTRACT FROM AUTHOR]

Summary: Multilevel inverter (MLI) provides a high power density, though the number of devices increases the chances of failures increases, reducing the reliability of power converter. It is essential to detect, isolate, and reconfigure the faults which arises in MLI. The research proposed here is capable of accomplishing the complete fault tolerance against single and multiple devices for both open circuit and short circuit faults. The control algorithm for operation of single‐pole‐double‐throw (SPDT) relays. This methodology is capable of completely preserving the normal operating condition in post‐fault condition also. The output voltage waveform matches by voltage sensors connected across load, and the controllers sense the faults originated from the variation in the look‐up‐table (LUT) and also categorize the nature of the faults. Field‐programmable gate array (FPGA)‐based controller sends a command signal through SPDT to isolate the faulty switches by redundant switches. In this way, the output power across the load is preserved. This research article also covers the comparative study that is made with the existing fault‐tolerant structures. The reliability comparison shows the better performance indices over conventional cascaded H‐bridge (CHB) inverter. The simulation and experimental results validate the effectiveness of control methodology to achieve complete fault tolerance. [ABSTRACT FROM AUTHOR]

Summary: Hardware Trojans (HTs) are malicious and intentional modification of the hardware design, embedded by an adversary to leak sensitive data, modify functionality, or cause malfunction. Lightweight ciphers are designed for resource‐constrained devices (RCDs) to balance resources and security, but often targeted by HTs. This work aims to create a trusted lightweight cipher design and detect complex sequential HTs using a runtime monitoring method with minimal resource overhead. The novelty of the approach is that it combines full or partial temporal redundancy, resource minimization, and runtime monitoring. The algorithm employs temporal redundancy, by executing a first run of the cipher, and then replays the cipher fully (ReplayN method) or partially (ReplayN/2 method). A mismatch indicates HT activity, and a third replay is executed to determine the correct results. The ReplayN/2 algorithm further optimizes time and energy by limiting replay to the second half of the cipher rounds. The proposed method is compared with other existing methods including triple modular redundancy (TMR), adapted triple modular redundancy (ATMR), and reverse‐function redundancy (RFR). All methods were implemented in field‐programmable gate array (FPGA) technology. Implementation performance metrics were measured and compared, including resource utilization (i.e., logical elements [LEs]), power, energy (E), and speed (i.e., Fmax). The results show that the proposed algorithm outperforms existing methods in most of the metrics. In terms of speed and area, the replay algorithm is faster by 24% and reduces total LEs by 42% when compared with existing methods. Regarding power, replay algorithm reduces power by 45% when compared with TMR and ATMR. With respect to energy, replay methods reduce energy by an average of 6% when compared with TMR and ATMR. The ReplayN/2 reduces energy by an average 15% when compared with TMR and ATMR. Based on the E×LE (i.e., energy × area) metric, ReplayN/2 is the top performing method as it balances area and energy metrics. Using E×LEFmax metric, the replay methods are the best performing methods as they best balance area, energy, and speed. Also, based on ThroughputLE2 metric, the replay methods are the top performing methods. [ABSTRACT FROM AUTHOR]

The utilization of an impedance network in power electronic applications overcame traditional two‐stage converters' drawbacks, including a dc‐dc and dc‐ac stage. A well‐designed impedance‐based converter shuns the necessity of multiple network stages that, in turn, enhance operational performance and reliability. The split source inverter (SSI) belongs to such a single‐stage system that consists of an impedance network with a voltage source inverter. The work's primary purpose is to explore the performance of grid‐connected SSI in the application of wind energy systems. A novel peak power tracking controller is proposed for the SSI‐based wind energy systems for tracking the maximum power available in the wind. The grid‐side controller's current regulator is modified to sense the intermittent wind's perturbation and to regulate the SSI output current. The theoretical analysis is validated by simulation, and different case studies are analyzed by considering the mutual effects of SSI and variable wind speed. A laboratory prototype is designed for the experimental investigation of the SSI that consists of a 5‐kVA three‐phase grid‐tied SSI and wind emulator prototype. A field‐programmable gate array (Xilinx) is used to program the control algorithm. Different test cases are analyzed experimentally to prove the robustness of the proposed controller. [ABSTRACT FROM AUTHOR]

Summary: A vast community of developing countries, like India, is still deprived of a proper water supply system. Such communities often depend on hand‐pumps, ponds, and ravines for their daily water needs. Government‐subsidized PV‐based water pumps have emerged as a boon for such communities. But intermittent nature of solar irradiation and unavailability at night time poses a big challenge. To mitigate this challenge, the present article proposes a stand‐alone PV‐based induction motor‐driven water pumping system serving a dual‐head, that is, an overhead storage tank and ground level supply. A single‐stage three‐phase high‐gain resonant inverter (HGRI) is proposed for driving the induction motor. A back‐ended wide bandgap (WBG) device‐based boost converter is used to extract maximum power from PV by employing the MPPT algorithm. HGRI injects sinusoidal current to the induction motor while operating it through PV power matched modified V/f control algorithm, thus minimizing the torque ripple. HGRI coupled with boost converter provides a high‐gain voltage boost at the output; enabling wide input voltage operation, which increases the operability of the system in high as well as low irradiation level. The practicality of the system is validated on a laboratory‐developed hardware test bed with a 1.5HP induction motor. [ABSTRACT FROM AUTHOR]

Summary: In this brief, an X‐band quasi circulator (QC)‐integrated low‐noise amplifier (LNA) implemented in 65‐nm Complementary Metal Oxide Semiconductor (CMOS) technology is presented. This work is the first QC‐LNA for the X‐band to the author's best knowledge, which achieves 30‐dB flat gain in 8–12 GHz with only 0.5‐dB variation across the band. This QC‐LNA uses two‐stage current reused techniques with variable impedance load. QC provides the minimum insertion loss of 0.9 dB with good return and isolation losses. Statistical analysis is presented for QC‐LNA to predict the percentage error tolerance. Quasi‐Newton (QN) control algorithm is used to optimize the parameter of the whole design. The design of experiment (DoE) is performed to claim the contribution towards gain, return loss, and noise figure. The proposed LNA measurement provides a minimum NF of 1 dB at 9.5 GHz, which remains less than 1.4 dB across 8–12 GHz. The fabricated LNA works with a supply voltage of 1.2 V and is unconditionally stable across the frequency. The calculated chip area is 0.84 × 0.52 mm2. This QC‐LNA exhibits an input and output 1‐dB compression point (IP1dB and OP1dB) of −15 and +13.8 dBm, respectively. It also exhibits third‐order input and output intercept point (IIP3 and OIP3) of +10 dBm and of +40 dBm, respectively. The proposed QC‐LNA draws only 8.7 mA from 1.2 V. [ABSTRACT FROM AUTHOR]

Summary: Four calibration algorithms based on the order statistics about capacitive mismatch are proposed for successive approximation register (SAR) analog‐to‐digital converter (ADC). An 18‐bit split capacitive SAR ADC architecture with redundant bits was used to verify the four calibration algorithms proposed. The main dynamic parameters of the SAR ADC were simulated in MATLAB by 500 Monte‐Carlo runs with a standard deviation of 0.1% (σ0/C0 = 0.001). And the simulation results of sorting and regrouping method II (SRGII) show that a 21.64‐dB enhancement of spurious‐free dynamic range (SFDR) and a 3.33‐bit improvement of effective number of bits (ENOB) have achieved respectively, whereas the simulation results of sorting and re‐exchanging method I (SREI) show that a 21.64‐dB enhancement of SFDR and a 3.34‐bit improvement of ENOB have achieved, respectively [ABSTRACT FROM AUTHOR]

Summary: This workpresents a novel high‐speed redundant‐signed‐digit (RSD)‐based elliptic curve cryptographic (ECC) processor for arbitrary curves over a general prime field. The proposed ECC processor works for any value of the prime number and curve parameters. It is based on a new high speed Montgomery multiplier architecture which uses different parallel computation techniques at both circuit level and architectural level. At the circuit level, RSD and carry save techniques are adopted while pre‐computation logic is incorporated at the architectural level. As a result of these optimization strategies, the proposed Montgomery multiplier offers a significant reduction in computation time over the state‐of‐the‐art. At the system level, to further enhance the overall performance of the proposed ECC processor, Montgomery ladder algorithm with (X,Y)‐only common Z coordinate (co‐Z) arithmetic is adopted. The proposed ECC processor is synthesized and implemented on different Xilinx Virtex (V) FPGA families for field sizes of 256 to 521 bits. On V‐6 platform, it computes a single 256 to 521 bits scalar point multiplication operation in 0.65 to 2.6 ms which is up to 9 times speed‐up over the state‐of‐the‐art. [ABSTRACT FROM AUTHOR]

Summary: Memristors are emerging devices that promise the efficient implementation of synapses in artificial neural networks. Memristors have permitted the processing and analysis of a large amount of data in evolutionary learning artificial systems through signals that can be assimilated to human brain‐like neurotransmitters and synapses. In this manuscript, we present a memristor‐based neural network implementing the Stochastic Belief‐Propagation‐Inspired algorithm, an efficient supervised learning algorithm (which infers a classification rule from a set of labelled examples) suited for devices with very‐low‐precision synaptic weights. Synapses are represented by memristor devices described by the Generalized Boundary Condition Memristor model. We will thus demonstrate how to implement the key features of a machine learning algorithm in real‐world circuitry. Copyright © 2017 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

Over the past 10 years, the multitude of highly constrained applications such as radio-frequency identification and sensor networks has led to a new trend in the development of cryptographic primitives. Many algorithms categorized as lightweight cryptographic algorithms have been developed specifically for these new applications. Comparing them is very important but also very challenging because every application has its own constraints. This fact leads to a different choice of design strategies, and the best algorithm for one application is not necessarily the best for all applications. Moreover, the definition of what is lightweight is not always the same because lightweight covers a reduction in power and energy consumption just as well as a reduction in area for hardware. This article proposes and compares lightweight hardware implementations of four recent block ciphers (Klein, Led, Lilliput, and Ktantan). This work is included in a large project that aims to protect the hardware against cloning and counterfeiting. The main constraint in this field is the area required by the protection scheme. As a result, we chose to target only the smallest possible area for each selected algorithm. Consequently, two strategies are presented: full width and serial hardware implementations. All results were generated and verified for Xilinx Spartan-6 and Spartan-3 field-programmable gate arrays and also for application-specific integrated circuit. Additionally, all the design files are available online. Copyright © 2016 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

SUMMARY Some of the advantages of very high speed integrated circuits hardware description language for analog and mixed signal (VHDL-AMS) when used to describe analog circuits are its modeling capability and the speed of simulations, in comparison with device level simulators. However, VHDL-AMS does not allow one to complete in a systematic way the synthesis of an analog circuit from higher description levels of the design hierarchy to lower ones. This is due to the lack of CAD tools and methods for analog circuits, contrary to the situation of pure digital circuits. This is a serious drawback because it is an obstacle to its success in analog CAD tools. The proposal described in this article, on the basis of the use of parameterizable macromodels, allows a systematic and rapid translation from a VHDL-AMS description of analog circuits to schematic level-sized descriptions. Copyright © 2011 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]