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Summary: This work presents the design of an asynchronous digital finite impulse response (FIR) filter suitable for high‐performance partial response maximum likelihood (PRML) read channel ICs. A high throughput, low latency FIR filter is the basic requirement for the equalization process in read channels. To achieve the enhancement in speed and reduction in latency of the FIR filter, its computational units are deeply pipelined using high‐capacity hybrid (HC‐hybrid) logic pipeline method. The designed FIR filter has been simulated using UMC‐180 nm and UMC‐65 nm technologies. Simulation results show that the asynchronous digital FIR filter can operate up to a throughput of 1.17 Giga items/s in 180 nm and 2.3 Giga items/s in 65 nm technology yet with the latency in the order of ns. [ABSTRACT FROM AUTHOR]

Summary: Load transient and dynamic voltage scaling (DVS) are commonly seen in the operation of the system processor. These two functions usually encounter large output voltage transient, which is hard to be quickly settled. Charge balance control is one of the prior choices that enables the converter to operate at its optimal charge/discharge slew rate so as to achieve fast transient response. The effectiveness of the optimal performance generally requires precise knowledge of the circuit parameters for charge balance computation. However, parameter drifting due to the manufacturing process may affect the performance, which is hard to implement a power integrated circuit (IC) for wide range applications. Different from the original approaches, this paper proposes an auto‐tuning charge balance control (AT‐CBC) to optimize load transient response and DVS of the buck converter. The auto‐tuning mechanism can save the preknowledge of the output filter and avoid complex calculation in digital control. The function of AT‐CBC is validated by a field‐programmable gate array (FPGA) controlled buck converter. Experimental result shows that the output voltage can be settled within 3 μs for the 750‐mA load step transient. For the 0.3‐V DVS transient, the output voltage can be settled within 4 μs. [ABSTRACT FROM AUTHOR]

Summary: A low power and high‐performance digital electrocardiogram (ECG) detector has become a basic requirement in modern implantable cardiac pacemakers. A fractional operator‐based digital ECG detector for modern pacemaker systems is proposed in this work. Instead of conventional thresholding, an adaptive slope prediction threshold is utilized for the detection of ECG peaks. A stochastic search‐based algorithm, namely, cuckoo search algorithm, is used to design an optimal fractional operator that is used for ECG denoising. It has been found that the proposed adaptive slope prediction threshold increases the QRS complex detection performance. A low detection error rate (DER) ranges from 0.01% to 0.56%, positive predictivity (P+) ranges from 99.32% to 99.98%, sensitivity (Se) ranges from 99.45% to 99.98%, and a detection accuracy (Acc) ranges from 99.43% to 99.96% for different databases are achieved for the proposed ECG detector, which is better compared with the existing ECG detectors. The proposed design of fractional order operator based on the lattice wave digital filter (LWDF) requires a minimum number of the multipliers for its structural realization. [ABSTRACT FROM AUTHOR]

Summary: A noniterative method for the all‐pass–based design of infinite impulse response multiple‐notch filters is proposed. This method ensures that specifications regarding positions of notch, left‐ and right‐hand cutoff frequencies, are exactly met, leading to a symmetric magnitude response about notch frequencies. Passband magnitude response can be improved by increasing the order of the corresponding all‐pass filter. A noniterative method for the all‐pass–based design of infinite impulse response (IIR) multiple‐notch filters is proposed. This method ensures that specifications regarding positions of notch, left‐ and right‐hand cutoff frequencies, are exactly met, leading to a symmetric magnitude response about notch frequencies. Passband magnitude response can be improved by increasing the order of the corresponding all‐pass filter. [ABSTRACT FROM AUTHOR]

Recently, we discussed the concept of direct synthesis technique (DST), in which real-coefficient filtering polynomials containing all information of the filters to be synthesized are derived directly for realization, and they could find applications in the design of lumped-element LC filters, active RC filters, and infinite impulse response digital filters. In this paper, another DST for complex general Chebyshev bandpass filters is discussed, which is based on a complex mapping relation and featured by complex-coefficient filtering polynomials. It is called as complex DST in this paper. Compared with real-coefficient filtering polynomials whose polarities are determined by the number of their zeros at zero frequency, the polarities of complex-coefficient filtering polynomials can be easily changed by multiplying imaginary unit j. Such advantage might make their realization more flexible. The analysis shows that conventional coupling matrix could be considered as narrow-band approximation of network matrix derived by complex DST in the normalized frequency domain. In order to demonstrate the validity of complex DST in this paper, it is applied in the design of classic parallel-coupled microstrip bandpass filters. Compared with conventional synthesis techniques, complex DST could find out better dimensions and provide more choices for realization and synthesize both even-order and odd-order parallel-coupled microstrip bandpass filters. Copyright © 2017 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

The main objective of this paper is to design and implement minimum multiplier, low latency structures of a comb filter. Multipliers are the most area and power consuming elements; therefore, it is desirable to realize a filter with minimum number of multipliers. In this paper, design of comb filters based on lattice wave digital filters (LWDF) structure is proposed to minimize the number of multipliers. The fundamental processing unit employed in LWDF requires only one multiplier. These lattice wave digital comb filters (LWDCFs) are realized using Richards' and transformed first-order and second-order all-pass sections. The resulting structural realizations of LWDCFs exhibit properties such as low coefficient sensitivity, high dynamic range, high overflow level, and low round-off noise. Multiplier coefficients of the proposed structures are implemented with canonic signed digit code (CSDC) technique using shift and add operations leading to multiplierless implementation. This contributes in reduction of number of addition levels which reduces the latency of the critical loop. A field programmable gate array (FPGA) platform is used for evaluation and testing of the proposed LWDCFs to acquire advantages of the parallelism, low cost, and low power consumption. The implementation of the proposed LWDCFs is accomplished on Xilinx Spartan-6 and Virtex-6 FPGA devices. By means of examples, it is shown that the implementations of the proposed LWDCFs attain high maximum sampling frequency, reduced hardware, and low power dissipation compared with the existing comb filter structures. Copyright © 2017 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

Recently, direct synthesis techniques (DSTs) have been presented for filter synthesis. Unlike conventional synthesis techniques, DSTs derive the filtering polynomials of the filters to be synthesized directly in their own frequency domain. These filtering polynomials are real coefficient so that they might find applications in various fields. Furthermore, DSTs might be used to customize filters with a more complex frequency response, such as asymmetric frequency response or multi-band frequency response. In this paper, DSTs are compared with some well-known filter synthesis techniques. Then, the application of DSTs in the design of lumped-element LC filters, distributed-element filters, active RC filters, and infinite impulse response digital filters with complex frequency response is discussed. Some examples are presented for demonstration. Copyright © 2015 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

SUMMARY In this paper, a digital filter for the generation/correlation of binary Golay pairs of sequences of length 2 N · 10 M · 26 P ( N, M and P are non-negative integers) is proposed. It is carried out by means of a novel Golay kernel 26 decomposition, also introduced in this paper, combined with building blocks of Golay kernels 2 and 10, presented in previous works. The proposed filter has a similar architecture to the digital filter for the generation/correlation of Golay multilevel pairs of sequences, where the parameters at intermediate stages have to be adjusted to obtain Golay binary pairs of sequences in the final stage. Copyright © 2013 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

ABSTRACT This paper deals with the similitude between the behaviours of linear filter gain and negative group delay (NGD) function. The transposition method of low-pass/high-pass, low-pass/band-pass and low-pass/band-stop NGD circuits is established. To the best of the author knowledge, it acts as the first paper devoted on the NGD function generalized theory. The introduced transform relationships simplify the synthesis of any NGD circuits from simple elementary low-pass NGD topologies. Families of innovative NGD topologies are identified. To verify the relevance of the concept proposed, frequency- and time-domain analysis results from realistic proofs of concept demonstrating the feasibility of developed NGD transforms were performed. Thanks to the NGD phenomenon, the possibility of the ultra-wideband pulse signals propagating in time-advance is verified. Finally, potential applications of NGD circuits are discussed. Copyright © 2013 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]