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Summary: This paper presents an energy‐efficient fully differential switching scheme for successive approximation register (SAR) analog‐to‐digital converters (ADCs). During the sampling phase, the top and bottom plates of all capacitors except most significant bit (MSB) capacitors are grounded in digital‐to‐analog converter (DAC) arrays. The input signals are bottom plate sampled on MSB capacitors. This technique can reduce the settling time by more than 87.5% in comparison with the conventional switching scheme. Furthermore, a novel reset‐free regenerative comparator is unveiled in this paper. The proposed comparator is armed to amplify its inputs both during the reset and evaluation phases. In comparison with a conventional single‐ended comparator, the proposed comparator can reduce power consumption above 90% for the almost same input‐referred offset voltage. The proposed scheme is designed with a resolution of 8‐bit and a sampling rate of 90 MS/s in a standard 65‐nm CMOS technology. The simulation results certify that the ADC dissipates 363‐μW power with a 1.2‐V supply voltage and achieves a 7.13 effective number of bits (ENOBs), yielding a 28.8 fJ/conversion step Nyquist rate Walden FOM. [ABSTRACT FROM AUTHOR]

Summary: This work presents a macro modeling approach for the time‐mode cyclic ADC. The proposed ADC macro model is realized using the time‐to‐voltage converter (TVC) and the voltage‐to‐time converter (VTC) that are the key building blocks of time‐mode ADCs. In addition, the effect of circuit nonidealities and error sources of the time‐mode ADC including parasitic capacitance, current source output resistance, switch on‐resistance, capacitor mismatch, and comparator offset are incorporated in the macro model. The simulation time of the proposed ADC macro model showed 87.1% reduction compared to the all transistor level ADC circuit. As a result, the proposed ADC macro model can facilitate the ADC design and leverage the ADC nonideality analysis. Furthermore, the proposed macro model can be used for ADC calibration scheme development. As a practical design example, the macro model for an 8‐bit time‐mode cyclic ADC has been realized, where the nonideality analysis, design optimization, and calibration scheme development based on the proposed macro model have been demonstrated. [ABSTRACT FROM AUTHOR]