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Summary: This paper presents an energy‐efficient fully differential switching scheme for successive approximation register (SAR) analog‐to‐digital converters (ADCs). During the sampling phase, the top and bottom plates of all capacitors except most significant bit (MSB) capacitors are grounded in digital‐to‐analog converter (DAC) arrays. The input signals are bottom plate sampled on MSB capacitors. This technique can reduce the settling time by more than 87.5% in comparison with the conventional switching scheme. Furthermore, a novel reset‐free regenerative comparator is unveiled in this paper. The proposed comparator is armed to amplify its inputs both during the reset and evaluation phases. In comparison with a conventional single‐ended comparator, the proposed comparator can reduce power consumption above 90% for the almost same input‐referred offset voltage. The proposed scheme is designed with a resolution of 8‐bit and a sampling rate of 90 MS/s in a standard 65‐nm CMOS technology. The simulation results certify that the ADC dissipates 363‐μW power with a 1.2‐V supply voltage and achieves a 7.13 effective number of bits (ENOBs), yielding a 28.8 fJ/conversion step Nyquist rate Walden FOM. [ABSTRACT FROM AUTHOR]

The highlight of in vivo or ex vivo measurement to monitor the pH value from blood or saliva is emerging in these years since changes in pH suggest that hidden diseases are about to occur. In this paper, we design and implement a SoC for pH measurement, and a dual offset cancelation technique in comparator featured with 150‐uV input referred voltage and 1‐GHz comparison bandwidth is verified. The SoC by utilizing proposed dual offset cancelation technique can sense 8 femto farad capacitance change in the deionized water, 12 femto farad change in the glucose liquid, and 14 femto farad in the 0.5% hydrochloric acid. The SoC for pH measurement is not only used to detect pH change in blood or saliva, but can also extend to wearable device to monitor human's biomarkers such as pH and Na+ in sweat to prevent the disease in advance. [ABSTRACT FROM AUTHOR]

Summary: This work presents a macro modeling approach for the time‐mode cyclic ADC. The proposed ADC macro model is realized using the time‐to‐voltage converter (TVC) and the voltage‐to‐time converter (VTC) that are the key building blocks of time‐mode ADCs. In addition, the effect of circuit nonidealities and error sources of the time‐mode ADC including parasitic capacitance, current source output resistance, switch on‐resistance, capacitor mismatch, and comparator offset are incorporated in the macro model. The simulation time of the proposed ADC macro model showed 87.1% reduction compared to the all transistor level ADC circuit. As a result, the proposed ADC macro model can facilitate the ADC design and leverage the ADC nonideality analysis. Furthermore, the proposed macro model can be used for ADC calibration scheme development. As a practical design example, the macro model for an 8‐bit time‐mode cyclic ADC has been realized, where the nonideality analysis, design optimization, and calibration scheme development based on the proposed macro model have been demonstrated. [ABSTRACT FROM AUTHOR]

Summary: Inductorless circuits are gaining advantage in radio frequency (RF) and high‐speed serial link circuits due to the reduced silicon area. This paper presents an inductorless adaptive analog equalizer using an adaptive hybrid filter comprising integrated low pass and high pass filter. The equalizer, designed and fabricated in 180‐nm CMOS technology, is able to adjust the high‐frequency boost (HFB) and cutoff frequency of the internal filters depending on the data rate and the channel loss. The presented equalizer operates at data rates more than 4 Gbps in post‐layout simulation without electrostatic discharge (ESD) and package parasitics. For the test purposes, the equalizer has been packaged in QFN 64 pin package and hence the measurement results are up to 3.125 Gbps. The measurement results show that the equalizer is able to adapt the HFB for the channel losses as high as 5 dB. Average dissipated power of the equalizer at 3.125 Gbps is 18 mW with 1.8‐V supply. After reading this chapter you should be able to understand the merits of the proposed hybrid filter compared with the conventional RC filters in the adaptive equalizer using spectrum balancing technique; theoretical analysis and the impact of short channel effects on the performance of the power comparator; and test results of the adaptive equalizer using the proposed hybrid filter in the spectrum balancing technique. [ABSTRACT FROM AUTHOR]

Successive approximation register (SAR) analog-to-digital converters (ADCs) are widely used due to their low power consumption and area cost. However, testing SAR ADCs on an embedded chip is costly. This paper proposes a capacitance-ratio quantification design for the linearity test of differential top-plate sampling SAR ADCs. First, the pattern generator controls the switches connected to the bottom plate of capacitors to create a voltage difference proportional to a certain capacitance ratio on the top plates to be quantified. Then, the proposed mechanism quantifies the capacitance ratio via the auxiliary transistors connected to the input pair of the comparator in the SAR ADC. The capacitance ratios are recorded to construct the differential nonlinearity (DNL) and integral nonlinearity (INL) using the derived construction principles, which simplifies the implementation of the output response analyzer. Thus, the test time and area cost can be reduced with these two proposed mechanisms. For characterizing the DNL, the error between the results obtained using the proposed method and those obtained using conventional linear ramp histogram method is from −0.10 to 0.11 least significant bits (LSBs). For the INL, the estimation error is from −0.19 to 0.11 LSBs. Moreover, a test time reduction of about 76% is achieved at the expense of an 18.54% area overhead for the capacitance-ratio quantification mechanism. Copyright © 2014 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

SUMMARY This paper describes circuit design considerations for realization of low power dissipation successive approximation register (SAR) analog-to-digital converter (ADC) with a time-mode comparator. A number of design issues related to time-mode SAR ADC are discussed. Also, noise and offset models describing the impact of the noise and offset on the timing error of time-domain comparator are presented. The results are verified by comparison to simulations. The design considerations mentioned in this paper are useful for the initial design and the improvements of time-mode SAR ADC. Then, a number of practical design aspects are illustrated with discussion of an experimental 12-bit SAR ADC that incorporates a highly dynamic voltage-to-time converter and a symmetrical input time-to-digital converter. Prototyped in a 0.18-µm six-metal one-polysilicon Complementary Metal-Oxide-Semiconductor (CMOS) process, the ADC, at 12 bit, 500 kS/s, achieves a Nyquist signal-to-noise-and-distortion ratio of 53.24 dB (8.55 effective number of bits) and a spurious-free dynamic range of 70.73 dB, while dissipating 27.17 μW from a 1.3-V supply, giving a figure of merit of 145 fJ/conversion-step. Copyright © 2013 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]