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A memory Alias Table holds a major role in Register Renaming Unit (RRU), which is responsible for maintaining the translation between logical registers to physical registers under the given instruction(s). This work presents the design of the memory Alias Table based on the SRAM‐based 8T‐Cell with multiport write, read, and content‐address operations for two‐way three operands machine cycle. The design of the memory Alias Table of size 32‐row × 6‐bit has SRAM‐based CAM cell of type 21T‐Cell that comprises four‐read ports, two‐write ports, and two‐content‐address ports. The content‐address examines the register under‐test against all contents of the memory Alias Table in parallel and releases the associated match index address. Results show that the four read ports operate simultaneously within the half‐cycle, while the two write ports operate simultaneously within the other half‐cycle. The operation of the two content‐address ports is managed during the half‐cycle of the read phase. Thus, the three operations occur within a single cycle without latency. HSPICE simulations using 90 nm/1 V CMOS process reveal that the memory Alias Table provides the three operations within a one‐cycle of 1 GHz consuming an average power of 0.13 mW. [ABSTRACT FROM AUTHOR]

We present a new FIFO (first‐in first‐out) architecture for both synchronous and asynchronous communication for high‐speed and low‐power operation. Our FIFO design is reconfigurable and scalable using a separate datapath with an 8T‐Cell SRAM and control circuits, which enables specialization for different application requirements. The datapath uses a two‐phase clock system of nonoverlapping signals such that one signal increments the address pointer, while the other signal activates the memory decoder for data reading and writing. This structure halves the critical path delay and simplifies the timing operations between the memory decoder and address pointer while maintaining robustness against process‐voltage‐temperature (PVT) variations. Our design uses two alternative control circuits to manage separate synchronous and asynchronous operations by generating nonoverlapping control signals that drive the datapath circuit. The empty‐full flag circuitry records only the state of the address pointers' rollover independent of the memory size, and, thus, improves scalability and reconfigurability. Compared to prior works, our design is 5X faster with a 2.3X lower power consumption and has a throughput of 1 Giga‐Word/s. For a 64‐bit word size with a free latency cycle. Additionally, our design functions clocklessly with the synthesizable structure for asynchronous communication that leverages Internet of Things (IoT) and Networks on Chip (NoCs) applications. The presented FIFO design is reconfigurable and scalable using separate datapath and synchronous/asynchronous control circuits, which enables specialization for different application requirements. The datapath uses a two‐phase clock system of nonoverlapping signals with 8T‐Cell memory. Our design operates 5X faster with a 2.3X lower total power consumption with a throughput of 1 Giga‐Word/s. For a 64‐bit word size with a free latency cycle for the synchronous communication, and it serves for asynchronous Internet of Things (IoT) and Networks on Chip (NoCs) applications. [ABSTRACT FROM AUTHOR]