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In this letter, a novel secret merchant‐4 (SM4) cryptographic circuit implementation is proposed against higher order power analysis attacks (PAAs). Four different random number generators (RNGs) are embedded into the SM4 architecture for breaking the correlation between the processed data and monitored power dissipation against PAAs. Firstly, fake keys are created by the first RNG to scramble the critical information related with the actual secret key. Furthermore, the second RNG controls the implementations of substitution boxes (Sboxes) with composite fields or look‐up tables randomly while the third RNG randomizes the substitution locations with respect to these Sboxes. Ultimately, the fourth RNG randomly swaps the behaviors of the fake SM4 and true SM4 to further break the critical correlation. Under the assistance of the four embedded RNGs, the proposed SM4 cryptographic architecture is capable of resisting against fourth‐order PAAs effectively with a 300 Mbps throughput and 165,354 μm2 area after synthesizing in the TSMC 90 nm process design kits (PDK). [ABSTRACT FROM AUTHOR]

In this letter, a high‐speed and low‐latency Ron Rivest‐4 (RC4) encryption algorithm is designed based on SMIC 14 nm process. Since the key issue of limiting the throughput of RC4 encryption algorithm is the swapping operation of S‐box, this proposed design is capable of achieving four swapping operations of S‐box within a clock cycle by utilizing fully combinational logic designs and advanced computations. All 256 swapping operations of key scheduling algorithm (KSA) can be done in 64 clock cycles. Moreover, the novel design greatly improves the encryption efficiency of RC4 since each clock cycle offers 4 bytes of key stream. The whole area can be further optimized by reusing the existing modules, and a lightweight countermeasure is embedded into the RC4 design to break the correlation between the processed data and power dissipation against differential power analysis (DPA) attacks. Finally, the whole design is assessed by the SMIC 14 nm process design kits (PDK). The corresponding clock frequency, throughput, area, and latency, respectively, are achieved as 1 GHz, 32 Gbps, 51,596 μm2, and 74 clock cycles. [ABSTRACT FROM AUTHOR]

Summary: False key‐controlled aggressive voltage scaling (FKCAVS) technique is a lightweight and effective leakage power analysis (LPA) attack countermeasure. However, the regular FKCAVS technique may not be utilized as a countermeasure against differential power analysis (DPA) attacks unconditionally. The primary reason is that the working frequency of DPA attacks is significantly higher than the corresponding frequency of LPA attacks. Thus, it is difficult to make the speed of voltage scaling keep pace with the speed of DPA attacks by employing the regular FKCAVS technique. In this paper, a fast FKCAVS technique is proposed to maximize the security of a cryptographic circuit (CC) against DPA attacks while minimizing the corresponding overhead by embedding a machine learning low‐dropout (LDO) regulator (MLLR). As shown in the result, by deploying the proposed FKCAVS technique, the measurement‐to‐disclose (MTD) value against DPA attacks is maintained over 1 million with less than 17.4% power/area overhead. [ABSTRACT FROM AUTHOR]

Summary: In modern integrated circuits (ICs), integrating workload‐agnostic multiphase switched‐capacitor (SC) voltage converters on‐chip is an effective way to reduce the transient response time, improve the security, and boost the power efficiency. However, a stochastic and unbalanced active sequence within the multiphase SC converter may undermine the corresponding output voltage ripple significantly. In this paper, a novel algorithm that is based on Fourier transform is capable of efficiently mitigating the amplitude of output ripple without compromising its security drastically. To achieve this objective, firstly, the output ripple of a single‐phase SC converter needs to be approximated with a Fourier expansion. Then the relationship between the output ripple and active phase sequence of a multiphase SC converter can be modeled precisely under the assistance of Fourier transform. After maximizing the randomness of the active sequences of the multiphase SC converter under different workload conditions and filtering a certain number of phase sequences with unsatisfied output ripples, the optimum control algorithm is generated. As shown in the result, the amplitude of output ripple of a multiphase SC converter can be reduced by 69.5% with negligible security loss and less than 29% power and area overhead under the 55 nm process design kits (PDK). [ABSTRACT FROM AUTHOR]

Summary: Traditional hardware security primitives such as physical unclonable functions (PUFs) are quite vulnerable to machine learning (ML) attacks. The primary reason is that PUFs rely on process mismatches between two identically designed circuit blocks to generate deterministic math functions as the secret information sources. Unfortunately, ML algorithms are pretty efficient in modeling deterministic math functions. In order to resist against ML attacks, in this letter, a novel hardware security primitive named neural network (NN) chain is proposed by utilizing noise data to generate chaotic NNs for achieving authentication. In a NN chain, two independent batches of noise data are utilized as the input and output training data of NNs, respectively, to maximize the uncertainty within the NN chain. In contrast to a regular PUF, the proposed NN chain is capable of achieving over 20 times ML attack‐resistance and 100% reliability with less than 39% power and area overhead. [ABSTRACT FROM AUTHOR]