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Summary: The present study is devoted to articulating a modified folded‐cascode circuit, to make folded‐cascode structures an attractive configuration as a transimpedance amplifier (TIA) for being employed in Giga‐bit per second optical communication receiver systems. Giga‐bps communication receivers are highly necessitating circuits to isolate the input parasitic capacitance of the photodiode. The present modification makes folded cascodes comparable to the famous regulated cascode (RGC) structures by isolating this parasitic capacitor almost by the same quantity. The system is shown to be capable of operating at 2.5 Gbps up to 8 Gbps data rate with a fixed bandwidth. The paper analyzes and evaluates the designed circuit mathematically, and the obtained simulated results from Cadence using TSMC 65 nm CMOS validate the suitability of the modified circuit as a TIA. [ABSTRACT FROM AUTHOR]

Summary: In this paper, a modified Regulated Cascode (RGC)‐based, low‐power, transimpedance amplifier (TIA) is proposed followed by a closed‐loop gain stage beside an added level shifter circuit to the booster of a conventional RGC circuit to set the proper biasing conditions for the transistors in the proposed TIA structure in 90‐nm CMOS technology. Moreover, the added gain stage benefits from an active inductor which resonates with the output capacitance of the TIA circuit to extend the bandwidth while saves the occupied chip area in comparison with passive inductor schemes. In addition, the performance of the proposed TIA circuit is simulated in HSPICE using 90‐nm CMOS technology parameters which show a transimpedance gain of 41 dBΩ, −3‐dB frequency bandwidth of 3.7 GHz, input referred noise value of 834nArms, and the power consumption value of only 1.4 mW at 1‐V supply. In this paper, a modified Regulated Cascode (RGC)‐based, low‐power, transimpedance amplifier (TIA) is proposed followed by a closed‐loop gain stage beside an added level shifter circuit to the booster of a conventional RGC circuit to set the proper biasing conditions for the transistors in the proposed TIA structure in 90‐nm CMOS technology. The simulation results show the proper performance of the proposed modified TIA as a low‐power block. [ABSTRACT FROM AUTHOR]