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This paper proposes the use of double-frequency (DF) buck converter architecture consisting of a merged structure of high and low frequency buck cells as a candidate topology for envelope elimination and restoration (EER) applications and integrated power supply of RF power amplifiers (RFPA) to obtain favorable tradeoffs in terms of efficiency, switching ripple, bandwidth, and tracking capability. It is shown that having two degrees of freedom in designing the DF buck helps to achieve high efficiency, low output ripples, and tracking capability with low ripples, simultaneously. A comparison analysis is done with regards to the mentioned performance indexes with the standard and three-level buck converters; in addition, the results are validated in HSPICE in BSIM3V3 0.35-µm CMOS process.

This article presents a low quiescent current output-capacitorless quasi-digital complementary metal-oxide-semiconductor CMOS low-dropout LDO voltage regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is segmented into two smaller sizes based on a proposed segmentation criterion, which considers the maximum output voltage transient variations due to the load transient to different load current steps to find the suitable current boundary for segmentation. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Furthermore, this situation is the worst case for stability requirements of the LDO. Therefore, using one smaller transistor for low load currents and another one larger for higher currents, a proper trade-off between output variations, complexity, and power dissipation is achieved. The proposed LDO regulator has been designed and post-simulated in HSPICE in a 0.18µm CMOS process to supply a stable load current between 0 and 100mA with a 40pF on-chip output capacitor, while consuming 4.8µA quiescent current. The dropout voltage of the LDO is set to 200mV for 1.8V input voltage. The results reveal an improvement of approximately 53% and 25% on the output voltage variations and settling time, respectively. Copyright © 2015 John Wiley & Sons, Ltd.

Digital control in switching power converters has been proposed and researched in recent years. However, one of the problems which arise in these circuits is that of quantization-induced limit cycle oscillations, which are generally considered to be undesirable. In this work, we investigate the addition of new control terms in the feedback loop of the system, in order to actively prevent these limit cycles from occurring. Firstly, the addition of a sinusoidal signal is considered, and then a more complicated signal which focuses on interrupting how the system switches between duty cycle levels is presented. The methods are effective in removing the limit cycle oscillations which arise in the system. Copyright © 2013 John Wiley & Sons, Ltd.