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In the paper, the novel topology of the resonant DC link three-level soft-switching inverter is proposed to reduce switching losses and improve the efficiency of three-level inverter at high switching frequency. Symmetrical auxiliary resonant circuits are set in the DC link of three-level hard-switching inverter. Moreover, the terminal voltage of the resonant capacitors between the DC buses periodically drops to zero via the resonance of auxiliary circuits. Furthermore, under such condition, the main switches of the three-level inverter would be operated, in order to achieve zero-voltage switching. Based on the equivalent circuits in different operating modes, the paper analyses the working process of the soft-switching inverter in detail. In addition, a 3 kW laboratory prototype of resonant DC link three-phase three-level soft-switching inverter is built. The experimental results show that the main switches and auxiliary switches of the inverter are operated under soft-switching conditions, and the efficiency is significantly improved compared with the three-level hard-switching inverter. Therefore, the proposed topology can effectively reduce switching losses and prove to be more practical in engineering. [ABSTRACT FROM AUTHOR]

This article is an interesting substrate material for environmental-friendly printable electronics. In this study, screen-printed RFID tags on paper substrate are examined. Their reliability was tested with low temperature, high temperature, slow temperature cycling, high temperature and high humidity and water dipping test. Environmental stresses affect the tag antenna impedance, losses and radiation characteristics due to their impact on the ink film and paper substrate. Low temperature, temperature cycling and high humidity did not have a radical effect on the measured parameters: threshold power, backscattered signal power or read range of the tags. However, the frequency response and the losses of the tags were slightly affected. Exposure to high temperature was found to even improve the tag performance due to the positive effect of high temperature on the ink film. The combined high humidity and high temperature had the most severe effect on the tag performance. The threshold power increased, backscattered power decreased and the read range was shortened. On the whole, the results showed that field use of these tags in high, low and changing temperature conditions and high humidity conditions is possible. Use of these tags in combined high-humidity and high-temperature conditions should be carefully considered. [ABSTRACT FROM PUBLISHER]

An auxiliary switching device is usually set on the DC bus of the resonant DC link inverter, which restricts the efficiency of the inverter and is also one of the reasons for its not extensive application and promotion in the high-power field. To solve the problem, auxiliary circuits and DC bus of the resonant DC link soft-switching inverter designed in this paper are connected in parallel, and auxiliary switching devices and resonant elements are not connected in series on the DC bus, which help to improve the efficiency and reduce the power losses of the auxiliary resonant circuits. Based on the equivalent circuits in different operating modes, the paper analyzes the working process of the soft-switching inverter, soft-switching realization conditions and design rules. A 10 kW laboratory prototype is built, and through the comparison of the experimental results from it and the hard-switching inverter, it is shown that the efficiency improvement value of the designed inverter at full load is higher than that at light load. Therefore, the soft-switching inverter designed in this paper is conductive to reducing the power losses of the auxiliary resonant circuits and ensuring the efficient use of the electric energy. [ABSTRACT FROM AUTHOR]

This paper describes a printed Thai character recognition method which uses topological properties. The recognition system is divided into two stages. In the rough classification stage, a thinning technique is applied to eliminate noise and fine features. The thinned characters are separated into cluster domains by using a linear decision function based on the height and width of each character. In the fine classification stage, the ‘connected numbers’ of points in the character pattern are computed. Topological properties are then used to distinguish between the characters. [ABSTRACT FROM AUTHOR]

This paper presents simulation analysis of an inverter made from non-aligned double gate field effect transistors (NADGFETs) in Sub-100 nm regime. The inverter consists of n-channel NADGFET and p-channel NADGFET device with a channel length of 40 nm and 50% non-alignment between gate and source/drain. The response of the inverter was tested by a combination of gate dielectric constant (k) and metal work function (ϕ). Three gate dielectrics namely, SiO2 (k = 3.9), Si3N4 (k = 7.2), HfO2 (k = 24), and three metal work function namely tungsten (ϕ = 4.5 eV), molybdenum (ϕ = 4.75 eV), gold (ϕ = 5 eV), were considered in the NADGFET inverter. This paper defines a kϕ index as characterising parameter to explore the best response from inverter configuration with minimum propagation delay, and minimum power consumption at super-high frequency. The paper proposes to analyse the NADGNFET device, in term of ION current, ION/IOFF ratio, cut-off frequency, and gate delay. And observes that low k material with moderate metal work function gives best response. The work then simulates the inverter and group the results into voltage transfer curve (VTC), transient response, and power dissipation category. The result shows that when inverter was subjected to high frequency, all the kϕ combination responds good, however when the inverter was subjected to super-high frequency, the low value of kϕ combination performs well. Thus, the result concludes that SiO2-M2 combination will be best selection to get minimum propagation delay and dynamic power dissipation by the inverter. The test strategy presented in this paper on the basis of kϕ index can serve as benchmark to test inverter device at super-high frequency. [ABSTRACT FROM AUTHOR]

Examines the characteristics of travelling waves along the non-linear transmission lines for monolithic integrated circuits. Analysis of slow-wave structures like MIS and Schottky-barrier strip lines; Examination of suitable equivalent circuits leading to characteristic wave equations; Parameters of the non-linearity, dispersion and dissipation and the boundary conditions of practical devices.

Examines the use of distributed, monolithic travelling-wave amplifiers. Guidance on reducing amplifier noise by rendering dipole-domain-generated noise contributed by the individual field effect transistor (FET); Use of insulated gate FET to permit higher gate breakdown voltage operation in the accumulation mode; Reduction of even harmonics and the improvement of efficiency.

Discusses the statistical properties of randomly generated boolean functions. Effect of prime implicant errors in the minimization algorithms; Relationship between the number of variables in the boolean expression on the k-subcube probability to be a prime implicant.

Approximate computing is an emerging paradigm that can tolerate some loss of accuracy to improve the energy consumption and design complexity. Multiplication is one of the important computational components in various digital signal processing (DSP) applications. Improvement of multipliers, as the building blocks of an approximate computing systems, has received significant attention. Compressors are key elements in an approximate multiplier to have an optimal design with high performance. This paper proposes an approximate/exact 4–2 compressor and an exact 5–2 compressor in carbon nanotube field-effect transistors (CNTFET) technology for utilisation in an approximate multiplier. Four efficient designs for utilising the proposed compressors are introduced and analysed for a Wallace multiplier. All of the proposed circuits are analysed in 32 nm CNTFET Stanford technology and are simulated by HSPICE. In addition, as an image processing application of approximate multipliers, this paper compares the quality metrics of the image multiplication for the proposed designs and previously presented approximated multipliers. For example, the proposed schemes provide excellent results in structural similarity index up to 99%, and peak signal-to-noise ratio more than 45 dB. Also, it uses figure of metric (FOM) that includes the accuracy and quality metrics of the approximate multipliers. The simulation results demonstrate the efficiency of proposed designs. [ABSTRACT FROM AUTHOR]

In this paper, the radial basis function neural network based on the orthogonal least squares (OLS-RBFNN) method is proposed for the first time for the calibration of the six-port receiver, which realises six-port accurate reception in the true sense. This algorithm overcomes the problems of an ageing circuit, narrow working frequency band and nonlinearity of the six-port receiver hardware. The RBFNN is a three-layer forward network, including an input layer, a hidden layer and an output layer. The transformation function of the hidden layer is the radial basis function. A six-port receiver test platform with an operating frequency band of 2.0–8.0 GHz is built to verify the performance of the six-port receiver based on OLS-RBFNN. The test signal is a 16-QAM signal with different bandwidths and different frequency bands. The test indicator uses error vector magnitude (EVM)， which represents the error between the received signal and the ideal signal sent. At last, the EVM of all tested data is less than 1.07%, and the best EVM is 0.57%. Therefore, the calibration accuracy of the OLS-RBFNN proposed in this paper is very high. [ABSTRACT FROM AUTHOR]

Power converters enhance the DC-AC power supply by using multi-level inverters based on switched capacitor technology. The voltage stress on the switches in switched capacitor-based multi-level inverters decreases as the number of switches rises, and vice versa when the number of switches falls. This paper suggests a quadruple boost nine-level inverter based on a switched capacitor with a single voltage source to address this issue. Only nine switches are used in the suggested architecture to implement the inverter with two diodes and two capacitors. Since the diodes and capacitors are linked to the low voltage input side, the total voltage stress of the inverter is kept low even at the elevated for quadruple boost output voltage. The theoretical study, computations, and design parameters of the nine-level inverter are presented in this paper. The switching specifics of the seven-level boost extension topology are also reported in this work. Simulations and laboratory tests on a 120 W inverter prototype have confirmed the viability of the suggested topology. [ABSTRACT FROM AUTHOR]

Due to the intermittent and unstable nature of PV systems, maximum power point tracking (MPPT) of PV systems is necessary in practice. At the same time, PV cells are also shaded by objects such as trees and houses in the environment causing local shadows, so the Lévy flight particle swarm optimisation (LFPSO) is proposed in this paper. The random walk process of Lévy flight is added to the particle swarm optimisation (PSO) to increase the diversity of the search, which can avoid falling into local optimal solutions. The experimental simulation results show that the algorithm proposed in this paper can still accurately track the global maximum power in the case of partial shading, which well avoids falling into the local maximum power. The performance is much higher than the traditional maximum power point tracking algorithm, which improves the efficiency of the PV system. [ABSTRACT FROM AUTHOR]

This paper proposes an efficient design of Hamming (11, 7) encoder utilising Full Swing-Gate Diffusion Input (FS-GDI) approach in 65 nm technology nano-size node. The proposed design of Hamming codes aims to improve the power and area efficiency through reducing of transistors count by employing power-efficient logic style. Encoding circuits of Hamming code (11, 7) and (7, 4) are designed using the various traditional and proposed approaches. The amount of consumed power, delay time, Power Delay Product (PDP) and hardware simplicity are employed as a metrics for evaluating the efficiency of the proposed designs of encoding circuits. The simulation experiments are executed utilising Cadence Virtuoso simulator package. These experiments revealed that the proposed designs of Hamming encoding circuits achieve delay time reduction by 50.91% and 20% for Hamming codes (7, 4) and (11, 7), respectively. Also, hardware (H/W) simplicity and area efficiency of the circuits are improved by 50% compared to CMOS-based circuits. From the results analysis, the proposed FS-GDI based Hamming encoding circuits achieve efficient power and delay optimising. Hence, the power consumption, delay and area in communications systems and DSP circuits due to encoding process are reduced. The whole performance of DSP circuits can be more power/area efficient. [ABSTRACT FROM AUTHOR]

In this paper, a Dickson-based RF-DC (Radio frequency power to direct current power) rectifier for energy harvesting system is designed. Dickson double-voltage structure, voltage-dividing structure and switching transistors are integrated in the system to fulfil the synchronous rectifying function, which can upgrade PCE (Power Conversion Efficiency) value, reduce the threshold voltage and decrease the leakage current, etc.. The simulation is conducted on the designed synchronous rectifier for energy harvesting of 900 MHz signal. It shows that when the input voltage $${V_{IN}} = 1V$$ V IN = 1 V , the peak output DC voltage can be stabilised at 1.8 V with the assistance of LDO (Low dropout) regulator, while the reverse leakage current is below 20 µA and the PCE value reaches 58%. The designed rectifier is assembled and tested in the paper. Both the simulation and testing results demonstrate the feasibility of the proposed synchronous rectifier. [ABSTRACT FROM AUTHOR]

In this paper, we present a design method for a highly efficient retrodirective array (RDA)-based microwave power transfer (MPT) system for the mMTC scenario, and evaluate its characteristics through experiments. Long-range wireless power transfer is required to effectively support the mMTC situation. RDA-based MPT controls and tracks the power beam towards the device within a certain range and it enables efficient power transfer. The overall link budget analysis is examined first and the required antenna gain is calculated. The required antenna gain can be secured using multiple-antenna modules. So, it is possible to design an RDA-based MPT system. In this paper, we implement a reduced RDA-based MPT system and evaluate its characteristics to confirm the feasibility of this design method. Through experiments, it has been confirmed that additional gain can be secured by using multiple antenna modules, and the RDA function can be effectively operated to effectively make a power beam in the direction of the power receiver. Conclusively, the gain of about 2.2dB increased whenever the number of antennas is doubled. The experimental results also show that the RDA-based MPT system designed in this paper is capable of adaptive power beamforming from −30 degrees to 30 degrees. [ABSTRACT FROM AUTHOR]

Non-cooperative scenarios in cognitive wireless sensor network (CWSN) are often encountered with shadowing and hidden terminal issues. Cooperative spectrum sensing (CSS) can solve these issues but at the expense of large overhead. It is necessary to optimise the energy of battery-operated unlicensed users, also known as secondary users (SUs). The effect of fading and noise uncertainty is often overlooked when determining CSS performance. Energy efficiency (EE) is a comprehensive parameter that gives a complete picture of the overall performance of the CSS. There are several parameters that affect the EE of CSS. In this paper, the detector threshold is optimised to maximise the EE of the system. A system model is proposed to determine the EE of centralised CSS over different fading channels in noisy reporting conditions. An iterative algorithm is presented which determines the optimum detector threshold for which the EE is maximum. Results show that the optimum value of the detector threshold from the analytical model matches with simulation data. [ABSTRACT FROM AUTHOR]

This paper introduces a non-isolated high voltage gain DC-DC converter for electric vehicles (EVs). The proposed converter schematic is modelled to be operated on reasonable duty cycle by employing passive switched inductor (PSL) cell and voltage multipliers. Moreover, this structure is functioning on continuous conduction mode (CCM) with a wide range of operations. This structure offers high voltage gain, lower voltage stress across all the devices, low switching losses and high efficiency. Thus, simple proportional integral (PI) controller is adopted to regulate the output to the desired voltage of 200 V. The proposed converter is designed and simulated using MATLAB/Simulink platform and hardware prototype of 100 W/200 V is developed to examine the performance of the proposed circuit. Besides, the experimental results are recorded to prove its robustness over both source voltage and load power discrepancies. The efficiency of the presented configuration is around 91% and it acts as a good choice for EV applications. [ABSTRACT FROM AUTHOR]

This paper presents a gradient-based optimisation method of antenna array for null controlling in specific regions and sidelobe suppression. The optimisation problem is formulated as optimising the electronic control parameters (excitation amplitude and phase) of the array to achieve that the maximum value of the peak sidelobe levels (PSLLs) is minimised and the depths of the nulls in specific regions are not greater than a threshold. The Kreisselmeier – Steinhauser (KS) function is used to describe the maximum value of the PSLLs, in this way, the optimisation problem becomes differentiable and can be solved efficiently by gradient-based algorithm. The sensitivities of the objective with respect to the design variables are analytically derived. Typical numerical examples and detailed evaluations are provided to validate the effectiveness of the proposed method. The results show that the null controlling in the predefined specific single, single-wide, dual, multiple, and annular regions is realised, and the PSLL suppression is performed comparing to the uniform planar arrays. In the 28 GHz base station transmitting antenna-array example, the proposed method effectively suppresses the PSLL and greatly saves the calculation time while maintaining the various specific null regions controlling. [ABSTRACT FROM AUTHOR]

Purpose: This paper presents a novel low-power, low input offset rail-to-rail comparator that is suitable for a digital dominant successive approximation resistor analog-to-digital converter. The proposed comparator is based on traditional inverters cascaded to amplify analog signals and digital logic level conversion. The absence of a direct path between the high-swing output node and the input node restricts kickback noise. Design/methodology/approach: The proposed circuit is designed and simulated using UMC 28 nm and 40 nm CMOS technology. The simulated power consumption using UMC 40 nm CMOS technology is 6.2084 μW at 1.1 V (330.8nW at 700 mV) supply voltage at the 2.5 MHz clock frequency. Similarly, simulated power consumption using UMC 28 nm technology is 0.04104μW at 900 mV (0.0097μW at 600 mV) and supply voltage operating at 66.66 MHz clock frequency with a resolution of a maximum of 12 bits, therefore, a reduction of more than 90% in power consumption observed by scaling technology node. Findings: The conventional power-efficient clock-controlled latched comparator does not have a static current during the entire operation. The main drawbacks are the limited input range and the the kickback noise. However, a large voltage swing on the drain of a differential pair, due to this current feeding through a parasitic drain gate capacitor to the input node and the presence of source impedance, results in kickback noise. The performance of the ADC can be hampered by excessive kickback noise, which can eventually cause an incorrect comparator output. An inverter-based comparator is reported, where the input range is rail-to-rail and operates at moderate speed. Modern scaled technologies have better matching among transistors, i.e. matching of switching threshold voltage achieved by selecting suitable aspect ratios of transistors (cascaded inverters). Inverter-based dynamic comparators are inherently power-scalable and switching threshold voltage scales with supply voltage variation. Therefore, the amplification operation is not hampered by the reduction of the supply voltage. Originality/value: The proposed architecture is compared with a set of existing hardware architectures to analyse various design metrics, such as low input offset, power scalability to maintain the resolution of the comparator, and low kickback noise. [ABSTRACT FROM AUTHOR]

This article covers the potential of Filter Bank Multicarrier (FBMC) modulation as an alternative to be used in the future 5 G wireless networks in which Massive Multiple-Input Multiple-Output (MIMO) is implemented. The 'energy efficient Massive Multiple Input Multiple Output (M-MIMO) Filter bank Multi-carrier Modulation (FBMC)' is necessary and beneficial for the upcoming wireless communiqué system. This is because there is an ever-increasing demand for higher data rates with higher Spectral Efficiency (SE). This paper compares orthogonal frequency division multiplexing (OFDM) with FBMC. This helps to evaluate the Spectral Efficiency (SE) of a Massive MIMO system that performs transmission under a unicellular environment. The variation in Massive MIMO allows equilibrium of the channel because FBMC has extra benefits due to the confinement of the subcarrier in an assigned range. However, the high Peak to Average Power Ratio (PAPR) in an M-MIMO-FBMC system is recognised as a serious problem that causes nonlinear signal deformation and restricts the effectiveness of the Power Amplifier (PA). In this work, to increase the SE in the system, the antenna count is optimised, such that the SNR or SNDR is maximum. For this, the antenna counts are optimised via Self Improved SSO with a Chaotic Map (SISSO-CM). [ABSTRACT FROM AUTHOR]

Antenna selection serves as an effective way of reducing complexity when dealing with multiple antennas, allowing for better signal transmission from a reduced number of antennas and thus increased system performance. In this paper, we derive a closed-form expression for the ergodic capacity (EC) of a multi-input multi-output non-orthogonal multiple access (MIMO-NOMA) network utilising joint transmit and receive antenna selection (JTRAS). We analyse the two-user and multi-user scenarios over Rayleigh fading channels with both imperfections: successful interference cancellation (SIC) and channel state information (CSI). To illustrate the gains of our proposed system, we compare its performance to that of its perfect counterpart. We observe that SIC and CSI imperfections have a significant impact on the performance of MIMO-NOMA networks. Furthermore, applying JTRAS to MIMO-NOMA also yields a higher sum EC than MIMO orthogonal multiple access (MIMO-OMA) with JTRAS. Finally, the close agreement between the analytical, asymptotic and simulation results validates the presented analysis. [ABSTRACT FROM AUTHOR]

A novel low-profile beam-switchable antenna operating in the Extended Global System for Mobile Communications band of 5G sub-6 GHz for vehicular communication is proposed in this paper. The proposed work has a centre patch that connects with four parasitic radiators and encompasses a tapered patch to R1, R2, R3 and R4 which are slotted loop rectangular patches. The main lobe switching is achieved for Extended GSM by switching between the states of PIN diode circuits, which affects the overall performance of the antenna. With the dimensions of 0.346 λe × 0.346 λe, the presented work exhibits a very-low-profile antenna, having an impedance bandwidth of 14.7% and a peak gain of 1.27 dBi. The proposed beam-switchable antenna incorporates four similar radiators facing different directions affixed to the central square patch director. Each PIN diode is incited eventually to obtain the same resonant frequency at each radiator. The pattern of the proposed antenna can be switched using different states of PIN diodes in the angles of 81°, 171°, 261° and 351°. The prototype is fabricated, and the measured results are in agreement with the simulated results. For the validation of the practicability of the proposed antenna, the far-field analysis is done on the vehicle. [ABSTRACT FROM AUTHOR]

Wearable device applications such as smartwatches, fitness trackers, and health monitors rely on batteries for power and require static random-access memory (SRAM) with low power consumption and high stability to ensure accurate sensor readings during prolonged operation. In this regard, this paper proposes a novel low-power single-ended 10-transistor (SE10T) SRAM cell with high stabilities. It utilises a stacked pull-down structure for hold/read stability improvement and leakage power reduction, a feedback-cutting mechanism for writability enhancement, and single-ended read/write structures for dynamic power reduction. Also, using a single-transistor reading path with eliminated read bitline leakage enhances ON-to-OFF currents (ION/IOFF) ratio. The proposed design is compared with the conventional 6T, Schmitt-trigger 10T (ST10T), differential writing 10T (DW10T), data-independent read port 10T (DIRP10T), transmission gate read-decoupled 9T (TGRD9T), and feedback-cutting 11T (FC11T) SRAM cells based on 7-nm Fin-shaped Field-Effect Transistor (FinFET) technology at VDD = 0.4 V. The proposed design shows at least 1.04×/1.01×/1.12×/1.25×/1.15× improvement in read stability/writability/read delay/leakage power/dynamic power. Moreover, it shows at least 1.22× improvement in ION/IOFF ratio and offers the lowest minimum operating voltage (0.292 V). However, it offers a 1.02× lower hold stability than that of ST10T, a 1.18×/1.14×/1.13× higher write delay compared to 6T/ST10T/DW10T, and a 1.56×/1.07×/1.05× higher layout area occupation in comparison with 6T/TGRD9T/DIRP10T. Therefore, the proposed SRAM cell can be an optimum candidate for usage in smartwatches. [ABSTRACT FROM AUTHOR]

The Discrete Cosine Transform (DCT) can be used instead of the conventional Discrete Fourier Transform (DFT) for the Orthogonal Frequency Division Multiplexing (OFDM) construction, which offers many advantages. In this paper, the Multiple-Input-Multiple-Output (MIMO) DCT-OFDM is enhanced using a proposed Cosine Domain Equaliser (CDE) instead of a Frequency Domain Equaliser (FDE). The results are evaluated through the Rayleigh fading channel with Co-Carrier Frequency Offset (Co-CFO) of different MIMO configurations. The average bit error probability and the simulated time of the proposed scheme and the conventional one are compared, which indicates the importance of the proposed scheme. Also, a closed formula for the number of arithmetic operations of the proposed equaliser is developed. The proposed equaliser gives a simulation time reduction of about 81.21%, 83.74% compared to that of the conventional Linear Zero Forcing (LZF)-FDE and Linear Minimum Mean Square Error (LMMSE)-FDE, respectively, for the case of a 4 × 4 configuration. [ABSTRACT FROM AUTHOR]

The discontinuous PWM technique, with its advantage over the continuous PWM technique in reducing switching losses in power converters, is gaining popularity. However, its deterministic nature results in discrete harmonics with significant amplitudes, which leads to electromagnetic interference (EMI) emissions. The randomised PWM technique is gaining more interest because of its effectiveness in spreading the harmonic spectrum and thus reducing EMI problems in power converters. This paper presents a carrier-based dual randomised discontinuous PWM (DRDPWM) method for a three-phase voltage inverter. The DRDPWM method combines the random carrier frequency (RCF-DPWM) and random pulse position (RPP-DPWM) schemes. In addition to reducing switching losses, DRDPWM can achieve a broad spread of the voltage spectrum with significantly smaller amplitudes. Furthermore, it produces less inverter output current distortion when compared to traditional DPWM and simple random (RCF-DPWM and RPP-DPWM) schemes. Simulations and experimental results confirm the effectiveness of the suggested method for spreading the voltage spectrum compared to simple random schemes. Additionally, an evaluation of the performance of all randomised discontinuous schemes is conducted based on a number of assessment metrics, including the switching loss factor (SLF), the power spectral density (PSD), the harmonic spread factor (HSF), and the quality factor (QF). [ABSTRACT FROM AUTHOR]

The instantaneous power of 1- $\phi $ ϕ solar photovoltaic system comprising of high-gain DC-DC converter and 1- $\phi $ ϕ photovoltaic inverter has a twice line frequency that creates the undesirable second order harmonic current. This paper provides topological changes in both DC-DC converter and DC-AC inverter to mitigate the undesirable second-order harmonic current. Re-boost converter is used instead of boost converter, and power decoupling-based 1- $\phi $ ϕ inverter is used for the inverter purpose. To provide adequate DC-link voltage, standard maximum power point tracking scheme is used. To control the output of inverter, fixed-frequency sliding mode controller is used that provides better response in steady state as well as transient state conditions. [ABSTRACT FROM AUTHOR]

Inevitability to reduce the size, cost and complexity of multilevel inverter (MLI) to evolve simplified RSC (Reduced switch count) MLIs has created diversified effects such as limited switching redundancies which further restricted modularity and flexibility of implementing PWM schemes. Among the PWM schemes of RSC-MLIs, modified reduced carrier (MRC) PWM with unified switching logic (USL) is the simplest and claims to be superior with the state of art in terms of implementation, line harmonic performance, imposing least controller computational burden (of 6.5 µS to realise a three-phase seven-level RSC-MLI) by adapting minimal carrier constraints. However, this is valid for sophisticated digital controllers such as dSPACE MicroLabBox, but not for low-end cost-effective controllers such as dSPACE1104 (imposing a computational burden of nearly 25 µS to control a single-phase RSC-MLI). Thus, this paper proposes an improved USL which adopts no carrier constraints and operates with less computational burden over the conventional USL. The proposed USL gives flexibility to the user to implement a part of the switching logic with analogue circuits and thereby avoid the requirement of high-end digital controller. The scalability and superiority of the proposed USL is demonstrated for symmetrical and asymmetrical configurations of popular cascaded T-type RSC-MLI. Efficacy of the proposed USL is demonstrated with dSPACE 1104 controller and dSPACE FPGA R&D Micro-lab Box. [ABSTRACT FROM AUTHOR]

This paper implements the stochastic filters for state and parameter estimation of nonuniform transmission lines (NTL). In general, transmission line (TL) problem is a continuous time and space problem. By taking the line loading noise into account, the TL equations become a stochastic partial differential equation (PDE) rather than a simple set of coupled finite stochastic differential equations (SDE). By transforming the spatial variables into the Fourier domain, the stochastic PDE can be transformed into an infinite sequence of SDE. After truncation to a finite set of Fourier series coefficients, it becomes a finite set of coupled linear SDE, which is the required domain in which extended Kalman filter (EKF) and unscented Kalman filter (UKF) can be applied. For state space equation of EKF and UKF, the voltage and current of periodic NTL are expanded into an infinite set of spatial harmonics. In this way, the voltage and current measurement of NTL become an eigenvalue problem. The NTL is considered as cascade of small infinite NTL and the four distributed primary parameters of the periodic NTL are expressed using Fourier series expansion. Finally, the Kalman filter (KF)-based state estimation and the EKF- and UKF-based parameter estimation have been compared with recursive least squares (RLS) method. The simulation results present the superiority of the method. [ABSTRACT FROM AUTHOR]

A modular multilevel converter (MMC) is reflected to be an emerging multilevel topology for medium- to high-power induction motor drives due to its highly reliable structure, modularity and scalability. However, large circulating current produced in the phase arm of MMC during low-speed operation of induction motor drive is a major drawback of MMC, which leads to affect the size of a sub-module capacitor, inductor and switch rating. To mitigate the circulating current and improve the performance of MMC-fed induction motor drive, this paper proposed a new circulating current error compensator (CCEC) technique with reduced arm current peak. By proper control of instantaneous voltage between arms and DC link current, second-order fundamental frequency current harmonic from circulating current is eliminated which leads to a significant reduction in circulating current. A comparative evaluation between conventional control scheme and the proposed CCEC control scheme is presented. The performance and effectiveness of the proposed CCEC technique are validated using a MATLAB-based simulation. Scale-down laboratory experimental setup is also developed to check the effectiveness of the proposed CCEC control technique. Reduction in circulating current for entire speed range with improved DC link current profile is observed as compared to conventional circulating current suppression control. [ABSTRACT FROM AUTHOR]

This paper presents the performance analysis of a five-level T-type multilevel inverter (MLI) based six-phase induction motor drive (SPIMD) for high-power industrial applications. In the adopted T-type MLI, the sensorless self-capacitor voltage balancing control is designed, which controls the voltage across the capacitor at half the magnitude of the direct current (DC) source value, creating a symmetrical five-level output voltage waveform. Moreover, self-capacitor voltage balancing control reduces complexity and improves system performance. The SPIMD with distributed neutral is taken as the load, and the whole system is simulated using MATLAB/Simulink software. The system's performance is determined by considering the power loss and efficiency. This paper also presents a comparative performance analysis of the adopted T-type, cascaded h-bridge (CHB) and Flying Capacitor (FC) MLI-based SPIMD. Finally, a prototype is developed as a proof of concept and tested experimentally to validate the analytical development of the adopted system. [ABSTRACT FROM AUTHOR]

Electronic devices are persisting as the integral part in various medical devices. These devices require SRAMs (Static Random Access Memory) with power efficient capability to handle the data, as they occupy most of the die area. Especially, wearable devices are bringing new challenges in the design of an IC, where high stability and low static power dissipation are very much required. In this paper, two new Carbon Nanotube Field Effect Transistor (CNTFET) based 9T SRAM cell topologies are presented to improve the leakage power dissipation at standby mode while maintaining the stability of the cell. Differential bitlines with decoupled read port are used to assist the read disturbance and the subthreshold lowering as well as stack of transistors are employed to curtail the leakage power. The circuits are implemented at 900 mv in Cadence using CNTFET technology. The Architecture with a 4 × 4 array matrix of the proposed 9T cells is designed. These are found to be the better ones yielding good results compared to the existing designs. [ABSTRACT FROM AUTHOR]

All-pass transformation (APT)-based variable digital filters (VDFs) can be used in different biomedical signal-processing applications, particularly in electrocardiograph denoising. In this paper, arithmetic optimised APT-VDF is proposed by modifying the hardware structure of APT-VDF based on arithmetic perception to enhance the performance in terms of area, speed and power consumption. The core blocks of the suggested Arithmetic Optimised APT-VDF (AOAPT-VDF)are adders and multipliers. This paper introduces a new reusable Vedic multiplier with redundant detection unit to identify redundant computations while generating the partial products. Also, a new Carry select adder (CSLA) with simplified combinational logics is proposed to improve the performance of the CSLA by simplifying the partial sum and carry generation logics without requiring Ripple Carry Adders. The proposed Reusable Vedic Multiplier with Redundant Detection Logic (RVM-RDL) also reuses the same vertical and cross-product generation units repetitively to reduce the area while increasing the bit length. The effectiveness of the suggested AOAPT is analysed utilising the MIT-BIH Arrhythmia Database. The proposed AOAPT-VDF consumes only 0.21 $$W$$ W power and achieves a 235.50 MHz operating frequency. [ABSTRACT FROM AUTHOR]

This paper presents a highly efficient dual-mode HV (high voltage) buck converter which operates at both light and heavy load currents. To improve the conversion efficiency at two different load conditions, a dual-mode design composed of pulse width modulation (PWM) and pulse frequency modulation (PFM) were implemented using TSMC 0.5- $\mu $ μ m HV CMOS process. The chip area is 2038.05 $ \times $ × 1689.85 $\mu $ μ m2, while the input voltage ranges from 12 V to 15 V. A 92.95% peak efficiency at a load current of 10 mA was achieved based on on-silicon measurement results. [ABSTRACT FROM AUTHOR]

This paper presents a new behavioural mixer model in a multi-box structure. In the proposed model, as well as amplitude and phase nonlinearity, the memory effect is also modelled. The multi-box structure is constructed in line with the Hammerstein model to characterise both fundamental signals, intermodulation distortion (IMD) and harmonic distortion (HD) for mixers in particular and all frequency translating devices in general. A testbed is constructed to measure both amplitude and phase characteristics. A good match between the measured and the calculated results is obtained using curve fitting and optimisation algorithms. In order to model the memory effect, a finite impulse response (FIR) filter is used. The measured IM3 imbalance is successfully modelled with this filter. For fundamental components, amplitude and phase errors are less than 0.1 dB and 1 degree, respectively. For IM3 components, amplitude and phase errors are less than 4 dB and 10 degrees, respectively. For the overall accuracy of the model, measurements are conducted with two-tone and modulated signals, and normalised mean square error (NMSE) values are calculated as −31.5 dB and −29.3 dB, respectively. The results are obtained for a wide range of input power span, including the compression region where nonlinearity is strongly pronounced. The proposed model is capable of accurately representing nonlinearity and memory effect for mixers and frequency translating devices in general and thus may be used for system-level modelling and linearisation applications. [ABSTRACT FROM AUTHOR]

The paper addresses the investigations of four elements MIMO antenna with reconfigurable grounds for 5 G NR n3/n1/n40/n41/n77/n79 to X-bands using PIN diodes. Initially, a single unit ultra wideband antenna is implemented, and then it is extended to 2 × 2 MIMO with reconfigurable grounds using one PIN diode. Later, the 4 × 4 MIMO antenna with reconfigurable grounds using six PIN diodes is developed. This study has the novelty that it gives the analysis and design of MIMO antennas switching between unconnected and connected grounds by the method of reconfiguration. The proposed 4 × 4 MIMO is fabricated on FR4 substrate with a volume of 0.485λ0 × 0.326λ0 × 0.0075λ0 mm3, where λ0 is calculated at a lowest resonating frequency. It has operating frequency bands of 1.4–1.6 GHz, 1.75–2.5 GHz and 2.7–13 GHz with connected grounds. The port isolation in the majority of the band is ≤ −15 dB. The inference is included on all the performance metrics. The fabricated MIMO performance is in line with simulated results and hence validates the observations of this research work. So, the proposed MIMO designs are compatible with 5 G wireless applications. [ABSTRACT FROM AUTHOR]

Machine learning-based prediction of the output characteristics of a negative capacitance (NC) double gate (DG) Tunnel FET (TFET) (NC DG TFET) has been demonstrated in this paper. On current (ION), OFF current (IOFF) and sub-threshold slope (SS) have been predicted for different values of the body thickness (TSi), oxide thickness (TOX) and channel length (LCh) and the work function (WF). Random Forest Regression (RFR) model is used in the ML framework to explore the device characteristics. A total of 5444 simulated data has been generated by using the SILVACO ATLAS tool. After pre-processing the data, RFR-ML has been applied to obtain maximum accuracy. Root means square error (RMSE) (~0.34), R2 score (~0.965) and accuracy (~98.51%) parameter have been used as the figures of merit (FOM) to judge the efficiency of the proposed model with respect to the state-of-the-art literature. Besides, with higher accuracy, the model is capable of predicting the data within a few seconds compared to the few hundred hours using TCAD tools. This fast and accurate design strategy will surely be efficacious for the present VLSI industries. [ABSTRACT FROM AUTHOR]

This paper discusses in detail a new 17-level inverter that employs a switched-capacitor (SC)-based configuration. The proposed SC-based inverters require just a single DC power supply, three capacitors, four diodes and 13 switches. The peak inverse voltage of the proposed 17-level SC-based inverter half-bridge is cut in half when compared to the prior arrangement, which was published not long ago. The blocking voltage is reduced by an order of magnitude as well. Many of the features of the proposed SC-based inverter, such as a high boosting gain factor (G) of eight times, self-balanced capacitor voltage and decreased voltage ripples in capacitors, have been carried over to other SC-based MLIs. The circuit description, working theory, PWM modulation techniques and capacitor voltage ripples are all examined. Finally, the results of the experiments show without a doubt that the proposed SC-based inverter can be made. [ABSTRACT FROM AUTHOR]

In this paper, the path loss performance of an eight-port Multiple-In-Multiple-Out (MIMO) antenna consisting of four circular slots radiator-based antenna elements is investigated in 3.5–3.75 GHz range for utilisation as an RFID tag and reader antenna. First, the S-parameters between the ports of two proposed MIMO antennas are measured in four channels of spatial diversity; one direct line-of-sight (LOS) and three indirect LOS in an anechoic chamber, each for the horizontal and vertical polarisation schemes at two distances, 5 and 25 cm, and the path losses between the ports of MIMO antennas are evaluated. Then, the path losses between the same MIMO antennas are obtained in a laboratory environment, which are higher by about 5–10 dB than those in the anechoic chamber and so, these losses are more dependent on the antenna position and nearby objects. The tag power sensitivity and the tag (read) range for the presented MIMO antenna are found to be more power level dependent than frequency dependent. The reported results confirm the performance of proposed MIMO antennas for RFID applications in addition to 5 G communications. [ABSTRACT FROM AUTHOR]

In two-stage electric vehicle (EV) battery chargers, ac-dc conversion stage contributes significantly in determining the power quality. At this stage, multilevel rectifiers (MLRs) featuring switches with lower voltage rating and better input voltage waveform quality can be adopted. However, balancing capacitor voltage in MLR is an important challenge. In this paper, a single-phase five-level power factor correction (PFC) rectifier with self-balancing capacitor is implemented for EV battery charging. The complimentary switching scheme adopted for rectifier reduces number of gate driver circuits and ensures capacitor voltage balancing. The rectifier shows added benefit of reduced voltage stress across switches and not requiring an external filter at the dc side as the load is parallelly connected with one of the capacitors. The operating principle, control strategy, modulation technique and design features of the implemented five-level rectifier is discussed in detail. The implemented control scheme enhances rectifier performance by establishing precise output voltage regulation during load fluctuations while maintaining unity power factor at input side. The five-level rectifier is validated experimentally and compared with other existing multilevel and non-multilevel rectifier topologies. The peak efficiency of 93.8% is achieved at 2 kW of output power. [ABSTRACT FROM AUTHOR]

In this paper, a radar cross-section (RCS) reduction of a microstrip antenna is investigated both experimentally and numerically. A traditional metal ground plane antenna and a bandstop frequency selective surface (FSS) filter are designed at 5.4 GHz. In order to reduce RCS and reflectivity of the reference antenna, the bandstop filter structure is set up instead of the full metal ground plane. The study observed a wide frequency range between 3 GHz and 14 GHz. The maximum RCS reductions between the reference antenna and the low RCS antenna in-band and out of band are obtained at 9.2 dBsm and 28 dBsm, respectively. The antennas are analysed under different θ – and φ – polarised incidence conditions. Low RCS antenna shows satisfactory results especially at X band in terms of reflectivity and RCS under these angular conditions. [ABSTRACT FROM AUTHOR]

This paper describes a high-frequency shunt feedback amplifier. A new design procedure is presented based on practical design steps as well as theoretical aspects, such as sizing the transistor, stabilisation, and selecting the values of feedback elements. The amplifier is designed and fabricated using 0.15 μm GaAs technology. It operates in the 7–10 GHz frequency range, with a small signal gain of 11.5 $ \pm $ ± 0.5 dB and input and output return losses of less than 6 dB and 7 dB, respectively. Furthermore, for 1 dB and 3 dB output compression points, the maximum measured values are 23.1 dBm and 23.9 dBm, respectively. Besides, the maximum measured value for Power Added Efficiency (PAE) for 1 dB output compression is 27.13% and 48.6% for 3 dB output compression. In addition, the measured Noise Figure (NF) in the frequency band of interest ranges from 3.7 to 4.1 dB. The chip area of the fabricated amplifier is 1.01 mm2. [ABSTRACT FROM AUTHOR]

This paper presents novel power-efficient designs of quaternary logic gates like Quaternary Minimum (QMIN) and Quaternary Maximum (QMAX), Standard Quaternary Inverter (SQI), Standard Quaternary NAND (SQNAND), Standard Quaternary NOR (SQNOR) and Standard Quaternary XOR (SQXOR) using Carbon Nanotube Field Effect Transistor (CNTFET). The designs are based on Pass Transistor Logic (PTL) and use only three types of Carbon Nanotube (CNT) diameters 0.626 nm, 1.018 nm, and 2.27 nm, which lead to lower fabrication costs and enhanced manufacturability when compared to the state-of-the-art designs. The designs are simulated in HSPICE with a 32 nm CNTFET model provided by Stanford University, and the average power and maximum propagation delay obtained from the simulation results are compared with other existing designs. It shows that the proposed designs require 75% to 90% less power and they achieve 73% to 91% less Power Delay Product (PDP) than the latest designs. [ABSTRACT FROM AUTHOR]

The two-stage power converter is currently the most widespread topology for three-phase grid-connected photovoltaic (PV) systems. The PV power is injected to the grid through the regulation of the dc-link voltage. This method is commonly called the voltage control method, whereby the current is controlled indirectly. This paper focuses on the modelling of power converters and the parameter design of proportional-integral (PI) controllers, based on the bandwidth of the inner current loop and the outer voltage loop. It is assumed that the inner loop has a bandwidth that is ten-fold bigger than that of the outer loop, in order to fully decouple the dual loops. The PI parameters are thus determined through this relationship, and two sets of simulations are run to validate the methodology used. Results show that the controllers give highly satisfactory performance even in the presence of transients introduced by rapidly varying irradiance model. [ABSTRACT FROM AUTHOR]

An improved combined-mode power converter (CMPC) for a solar photovoltaic (SPV) system is presented in this paper. Ten-power electronic switches are utilised for the functioning of the converter. The proposed converter has four modes of operation: buck, boost, inverter, and mixed mode. The new CMPC topology provides a unique and complex switching sequence for implementing the mixed-mode operation. This work uses a field-programmable gate array (FPGA) for mode selection and to create PWM (MS-PWM) signals. A digital MS-PWM controller is configured to switch between improved stepped perturb and observe (ISPO) maximum-power point tracking (MPPT) and sine wave PWM (SPWM). The ISPO provides the appropriate duty cycle for buck/boost operation, while the SPWM controls the inverter operation. This work's new digital PWM control algorithm supports mode selection, PWM generation, and reconfiguring PWM generation timings. The whole framework for constructing the MS-PWM controller employs a very high-speed integrated circuit hardware description language (VHDL). Simulation and experimental results are presented, proving that the digital MS-PWM controller uses fewer resources with improved accuracy. [ABSTRACT FROM AUTHOR]

In the multi-target scenarios, we consider the problem of constant false alarm rate (CFAR) target detection. For the conventional CFAR algorithms, the multi-target detection performance is mainly limited by the interference target tolerance within the reference window. In this paper, we propose a local ordered statistic CFAR (OS-CFAR) target detector based on compressed sensing (CS) radar system to address the degradation of detection performance in multi-target scenarios. With the analog-information-converter (AIC), the radar intermediate frequency (IF) signal is compressively sampled into discrete linear measurements. At each detection stage, multiple signal components are generated by correlation tests between the sensing matrix and linear measurements. By support set merge and proxy pruning, the signal components with the largest energy are retained. These components are the echoes reflected from the targets. Since target components are output in decreasing order of correlation, the proposed detector only requires a local OS-CFAR decision in the interval where the least correlated target is located, rather than traversing the entire interval. By continuously updating the detection stage, all targets that satisfy the false alarm rate requirement can be screened out. Finally, the performance of the proposed detector in the multi-target scenarios is confirmed by simulation results. [ABSTRACT FROM AUTHOR]

The first part of the paper discusses designing of the lowpass filter that gives both a constant group delay over the passband and a sharp cut-off slope, which is one of the most difficult challenges in continuous-time signal processing. Furthermore, equalisation of the group delay distortion of the Chebyshev filter has been performed through a cascade connection of the allpass filters. The Newton–Raphson method is applied for solving the system of nonlinear equations that calculate the allpass filter parameters for equalising the constant group delay in an equiripple sense. This procedure gives nearly symmetric impulse response of the resulting filtering system, as well as a longer duration. In the second part of the paper, two solutions for synthesising polynomial filter transfer functions are discussed: filter with monotonic amplitude characteristic (LSM) and filter using Chebyshev polynomial. For the purpose of comparison, the passband ripple factor of the Chebyshev filter is necessary to be adjusted so that both filters have the same stopband insertion loss, group delay and transient response. It is shown that Chebyshev filter is preferable since the passband magnitude distortions and sensitivity to the element deviation tolerance are significantly superior. [ABSTRACT FROM AUTHOR]

The grid-forming inverter (GFI) plays an indispensable role in the microgrid (MG). Thus, it is critical for a microgrid to control the GFI flexibly and accurately, because of its voltage-forming and frequency regulation capabilities. The conventional proportional integral (PI) control strategy is usually used to control the GFI. However, the conventional PI control strategy has a high output voltage total harmonic distortion (THD) and deteriorative performance under external disturbances, which results in several problems in system flexibility, reliability and stability. This paper proposed a novel adaptive sliding mode control (ASMC) based cascaded control of the GFI system, which involves an ASMC-based inner current loop and outer voltage loop, and shows some superior performances of low THD, fast dynamic tracking performance and good robustness. Both the MATLAB/SIMULINK-based simulation and StarSim Modelling Tech-based semi-physical experimental results were presented to validate a perspective: the control strategy proposed by this paper has a better performance than the conventional PI control strategy under transient and steady-state condition. [ABSTRACT FROM AUTHOR]

The paper presents the measurement study of a double channel pHEMT device. Its focus is on examining impacts of several parameters including probe pitch size, position and the applied pressure on the measurements. The impact of probe pitch size, position and applying suitable amount of pressure and more pressure than required on the measuring perspective of a double channel pHEMT was investigated. As noted from the collected data, these impacts are most likely related to the stability factor, current gain and maximum available gain of the studied microwave device. The measurement was done using two probes with pitch sizes of 200 µm and 150 µm, and the probes were placed in the middle of the device's contact pads while exerting appropriate pressure. For double channel pHEMT on wafer, the outcome can be deemed similar for both pitch sizes. On the other hand, the probe with pitch size of 200 µm is utilised for applying more pressure than required where the probe occupied the entire pads of the device and the findings are skewed. Finally, it was found that the RF measurement is frequently affected by these conditions while the DC measurements are unaffected or have a minor effect. [ABSTRACT FROM AUTHOR]

The presence of turning points (stationary points like maxima and minima) in the Parameter-versus-state map (PSM) curve of a memristor can be beneficial in several memristive uses like multi-level logic design, multi-bit memories, and chaos generation circuits. Surprisingly the memristors with these types of PSM curves exhibit multiple crossing points in the transient input v-i contours. In this paper, the memductance model has been derived for such non-linear memristors exhibiting multi-cross-over characteristics. In the presented framework, the coefficients-related condition for the multi-turning point PSM curve has been derived, a necessary condition for the multi-crossing v-i contour. The condition related to the memristor operating parameters has also been reported taking both input signal and initial states into consideration. To realise the derived memductance model corresponding to the three cross-over memristive behaviour, an OTA-based memristor emulator has been developed. Unlike some existing fractional order non-symmetric multi-crossing memristor emulators, the proposed emulator circuit realises an integer order memristor function operating at moderate frequencies. The realised emulator uses only four OTAs and three grounded passive circuit elements with no external multiplier. For the CMOS implementation of employed OTA, the simulation results are obtained to verify the three pinch-off behaviour. [ABSTRACT FROM AUTHOR]

This paper presents a novel low-voltage low power fully differential class AB current output stage with high linearity and unique current drive capability. The proposed circuit is based on a simple and efficient structure to obtain high linearity by minimising the channel length modulation effect and also avoids cascade structure to act best in low-voltage applications. Giving the complete analyses and equations of the circuit, its properties are verified by Cadence using TSMC 0.18 µm CMOS parameters. In order to study its performance at the presence of non-idealities, Pre-layout and Post-layout both plus Monte–Carlo simulations are also performed. Under±0.9 V supply and 35 µA output bias current, it can deliver the ever high output current of ±350 mA with THD of −49 dB and output impedance of 2.8 MΩ, which leads to a unique high current drive ratio (Ioutmax/Ibias) of 10,000 and low consumed power of 150 µw in pre-layout simulation. In post-layout plus Monte–Carlo simulation, the results will be as ±320 mA output current, −42 dB THD, 2.2 MΩ output impedance, 40 µA DC current of the output branch, 8000 current drive ratio and 160 µw consumed power. These remarkable results prove the proposed novel COS not only as the unique one in the world but Longley ahead of the yet second rank COS by some unbeatable ratios as 11300×,14×,4× and3× in FT, Ioutmax, (Ioutmax/power), and current drive, respectively, that promise to keep it as the lead one for many years in low-voltage/power ultra-high current applications. [ABSTRACT FROM AUTHOR]