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Mutual coupling effect and degrees of freedom (DOFs) play a crucial role in the sparse array design. In this paper, we judiciously configure the dense subarray and sparse subarray of the nested coprime array with displaced subarrays (NCADiS) to obtain an improved NCADiS (INCADiS). Then, the dense subarray of the INCADiS is split into two parts and rearranged on the left and right sides of the sparse subarray of the INCADiS to structure an augmented nested coprime array with displaced subarrays (ANCADiS). We also derive the closed-form expressions for the element locations and the number of uniform DOFs (uDOFs) of the ANCADiS configurations with any number of elements. The proposed array configuration has the same uDOFs as the INCADiS and the prototype optimised NCADiS (PNCADiS), and at the same time achieves reduced mutual coupling. Some theoretical properties are proved, and numerical simulations are included to verify the superiority of the proposed configuration. [ABSTRACT FROM AUTHOR]

Synthetic aperture radar (SAR) imaging systems are a complement to passive remote sensing. However, the process of image formation is so complex that the final image in the system is formed only after three basic steps: raw data acquisition, forming the signal and the image space. In addition, there are various factors that are involved in the information recorded by SAR within the system and outside the system, such as radar, platform, processing algorithm, imaging region and channel. Each of these factors has been formed by many parameters and this issue adds to the complexity of the behaviour of SAR. Therefore, due to the complexity, providing a model that describes how the SAR imaging system works is highly important. In this paper, the performance of SAR in the image formation section is analytically modelled at first, and then implemented as software. Raw data acquisition is performed in CST software and the signal and image formation are performed in MATLAB software. This implementation provides many abilities, such as better interpretation of SAR images, simulating the effect of the important parameters in SAR images, etc. [ABSTRACT FROM PUBLISHER]

Cognitive radio (CR) is a promising technology to improve the utilisation of wireless spectrum resources. Spectrum sensing is the core functionality in CR networks (CRN). When there exist malicious users (MUs) in CRN and MUs start to attack the network after accumulating reputation to some extent, the performance is deteriorated. In this paper, a scheme is proposed by employing Orthogonalized Gnanadesikan–Kettenring (OGK) to mitigate the effect of MUs without the assistance of trusted nodes, and it can improve the robustness of CRN. Simulations verify the effectiveness of the proposed scheme. [ABSTRACT FROM AUTHOR]

This paper has discussed the study of the performance of dynamic voltage restorer (DVR) taking different voltage sag conditions in the supply voltage of the distribution system for linear and non-linear load. DVR is employed to mitigate the voltage sag. Proportional and integral (PI) controller is used for the control of DVR to mitigate the voltage sag. Synchronous reference frame theorybased control algorithm has been implemented for generating reference voltages. In this paper, an efficient improved particle swarm optimisation technique for optimizing the gain parameters of the PI controller has been proposed. The performance and suitability of DVR is validated through MATLAB simulation results and use of Sim Power Systems Blocksets. Integral squared error is implemented to check the performance and suitability of DVR. Extensive results of the proposed method are presented and compared with conventional Ziegler Nichols and genetic algorithm methods of tuning gain parameters of PI controllers. [ABSTRACT FROM AUTHOR]

There must be a non-negligible communication time-delay in the transmission process of wide area information through the power system. Communication time-delay will reduce the system stability or even cause system instability, and also there exists an identification error problem in the model identification. Therefore, the identification error will make model parameters not accurate enough, and it cannot ensure the control effect of the power system time-delay damping controller. Aiming at the problem of communication time-delay and identification error in the power system, firstly, a closed-loop time-delay model of the power system is described in this paper. Secondly, a design method of iterative identification damping controller of the power system considering the time-delay (constant delay and time-varying delay) is proposed. In addition, the whole step of the proposed method and a mathematical calculation method of the exact time-delay controller model are given. Finally, the four-machine two-area system model is taken as an example in this paper. Simulation results show that the response of both angle and active power of motor can stabilize within 8 seconds. The designed controller in this paper can effectively suppress low frequency oscillation and ensure the stability of power system. [ABSTRACT FROM AUTHOR]

A false target deceptive jamming method for countering ultra-wideband synthetic aperture radar (UWB-SAR) is proposed in this paper, which is based on dechirp processing to intercepted UWB-SAR signal and inverse dechirp to jamming signal. The jammer quadrature down-converts and dechirps the intercepted UWB-SAR signal using a linear frequency modulation (LFM) signal oscillator, which could reduce the bandwidth and sample rate of analog-to-digital converter. Then, the jammer utilises the azimuth direction Doppler frequency phase between the false target and the jammer, and backward reflection coefficient template to modulate the phase of the intercepted UWB-SAR signal, and then delayed the modulated phase and also modulated the range direction Doppler frequency phase to the that. Finally, the jammer uses LFM signal oscillator to up-convert the narrowband jamming signal in order to recover the bandwidth of the signal. Parameter errors analysis and simulation results have shown that the detected parameters and motion characteristic errors reduce the resolution and offset the expected position of the false target, but it still could obtain an expected false target image. Theoretical analysis and simulation results indicated that the jamming signal proposed in this paper could produce a false target in the UWB-SAR image, which provide a feasible method for countering UWB-SAR in real time. [ABSTRACT FROM AUTHOR]

In this paper, we first propose a novel sparse array (NSA) composed of three adjoined sparse subarrays, among which the first and third ones can form the prototype coprime array (CA), and the second one is nested to them. When deploying NSA for direction of arrival (DOA) estimation, two virtual CAs with larger apertures than the physical ones can be generated by vectorising the covariance matrices corresponding to specific subarray pairs. Accordingly, improved DOA estimation performance can be achieved. Afterwards, to enhance the DOA estimation of noncircular sources, four improved NSAs are designed, which have minimised redundancy between the difference and sum coarrays. Hence, they have larger utilised apertures than NSA. In addition, due to the larger physical aperture and inter-element spacing, all the five proposed arrays have less mutual coupling and better DOA estimation performance than the prototype CA. Numerical simulations confirm their effectiveness and superiority. [ABSTRACT FROM AUTHOR]

This paper proposes a dual-bridge LLC series resonant converter with hybrid-rectifier for achieving extended charging voltage range of 50–420 V for on-board battery charger of plug-in electric vehicle for normal and deeply depleted battery charging. Depending upon the configuration of primary switching network and secondary rectifier, the proposed topology has three operating modes as half-bridge with bridge rectifier (HBBR), full-bridge with bridge rectifier (FBBR) and full-bridge with voltage doubler (FBVD). HBBR, FBBR and FBVD operating modes of converter achieve 50–125, 125–250 and 250–420 V voltage ranges, respectively. For voltage above 62 V, the converter operates below resonance frequency zero voltage switching region with narrow switching frequency range for soft commutation of secondary diodes and low turn-off current of MOSFETs to reduce switching losses. The proposed converter is simulated using MATLAB Simulink and a 1.5 kW laboratory prototype is also built to validate the operation of proposed topology. Simulation and experimental results show that the converter meets all the charging requirements for deeply depleted to fully charged battery using constant current-constant voltage charging method with fixed 400 V DC input and achieves 96.22% peak efficiency. [ABSTRACT FROM PUBLISHER]

IEEE 802.15.4 is a popular standard for personal area networks used in different low-rate short-range applications. This paper examines the error rate performance of 802.15.4 in fading wireless channel. An analytical model is formulated for evaluating frame error rate (FER); first, for direct single-hop transmission between two sensor nodes, and second, for dual-hop (DH) transmission using an in-between relay node. During modeling the transceiver design parameters are chosen according to the specifications set for both the 2.45 GHz and 868/915 MHz bands. We have also developed a simulation test bed for evaluating FER. Some results showed expected trends, such as FER is higher for larger payloads. Other observations are not that intuitive. It is interesting to note that the error rates are significantly higher for the DH case and demands a signal-to-noise ratio (SNR) penalty of about 7 dB. Also, the FER shoots from zero to one within a very small range of SNR. [ABSTRACT FROM AUTHOR]

In this paper, direction of arrival (DOA) estimation of multiple signals with coprime array is investigated and signal subspace fitting (SSF) method is linked to the coprime array, which achieves a better DOA estimation performance than the traditional uniform array. While the SSF method requires expensive computational cost in the case of multiple signals due to the multidimensional global angular searching, we propose a successive SSF (S-SSF) algorithm from a computationally efficient perspective. In the proposed algorithm, we employ rotational invariance and coprime property to obtain the initial estimates. Then, via a successive scheme, we transform the traditional multidimensional global angular searching problem into one-dimensional partial angular searching one. Consequently, the computational complexity has been significantly reduced. Specifically, the proposed S-SSF algorithm can obtain almost the same DOA estimation performance as SSF but with remarkably lower complexity. Finally, Cramer-Rao Bound (CRB) is provided and numerical simulations demonstrate the effectiveness of the proposed algorithm. [ABSTRACT FROM AUTHOR]

This paper presents a novel design method of bandstop filters (BSFs) and dual-band bandstop filter (DBBSF) with completely controlled bandwidth and centre frequency, high rejection levels at mid-stopband and compact sizes. First, bandstop units with simple structures are proposed. Through theoretical analysis, the centre frequency and bandwidth of the bandstop units can be independently controlled by tuning the parameters of the loaded stubs. Then, single-band, dual-band bandstop units and compact J-inverters are adopted to design the filters. Finally, to demonstrate the proposed design method, 2-order, 3-order and dual-band BSFs are fabricated and measured. From the experimental results, the maximum rejection levels at mid-stopband of 2- and 3-order are around 50 dB and 70 dB, respectively. The two stopbands of the DBBSF can be fully controlled. The measured maximum rejection levels at the two mid-stopbands are both around 60 dB. Furthermore, all the simulation and measurement show good agreement. [ABSTRACT FROM PUBLISHER]

By combining Spatial modulation (SM) with cooperative communication, the diversity gain brought by cooperative relaying and high rate of SM can be obtained. In this paper, considering amplify-and-forward (AF) protocol, the performance of cooperative SM system with imperfect channel state information (CSI) over Rayleigh channel is analyzed. According to the performance analysis, the moment generating functions (MGFs) of effective signal-to-noise ratios (SNRs) are derived. With the MGFs, closed-form expressions of the error probability of antenna index detection and the error probability of symbol detection for imperfect CSI are achieved. Thereby, the approximate overall average bit error ratio (BER) is obtained, and these theoretical expressions include those under perfect CSI as special cases. Besides, the asymptotically approximate BER for large SNR is also derived. Based on this, a suboptimal power allocation (PA) scheme is developed, and the corresponding PA coefficients are attained by minimizing the asymptotical BER. As a result, closed-form PA can be attained for the system with multiple receive antennas. Computer simulations show that the theoretical BERs are close to the corresponding simulated results, which illustrates the effectiveness of the derived theoretical expressions. Compared with the conventional equal PA scheme, the proposed PA scheme enhances the BER performance efficiently. [ABSTRACT FROM AUTHOR]

In this paper, a blind signal separation (BSS) methodology for simultaneously received multisystem frequency-overlapped signals in a single-channel (SC) electromagnetic surveillance system is proposed using fast independent component analysis (FastICA) in a dynamical embedding (DE) framework. Firstly, an appropriate DE matrix is constructed out of a series of delay vectors from the SC recording. The lag-time and the dimensional of embedding matrix setting principal are introduced in details. Next, multiple independent components (ICs) are calculated by decomposing the embedding matrix through FastICA algorithm, and ICs can be regarded as a convenient expansion basis of the original signals. Then, these ICs are projected back into the measurement space. After that, these projected ICs are classified and used for recovering the sources of interest based on their independent nature and their power density spectrum. Numerical simulation results obtained in evaluating the proposed methodology’s performance confirmed the effectiveness of the proposed algorithm. [ABSTRACT FROM PUBLISHER]

Most of the research on identifying and classifying signal models is limited to single signals such as AM, QAM or PSK, and there is a lack of research on the parameters of the identified signals. To make up for this deficiency, an OA (Optimality Confidence and Amplitude Ratio factor) algorithm model is proposed to identify and classify 13 kinds of modulation signals, including 2 kinds of analogue modulation signals (AM and FM), 11 kinds of signal digital modulation (M-SK and M-QAM). Based on the characteristics of the constellation diagram, Confidence and Amplitude Ratio factors are constructed to identify and classify signals with different parameters such as 'Format", "Centre Frequency" and "Sample Rate' and different modulation types. In addition, because of the mis-judgement and confusion problems in identifying classification signals, a three-layer optimisation algorithm is proposed to optimise the OA algorithm model. Numerical simulation results show that the comprehensive identification efficiency of the proposed optimisation algorithm is increased by 18.84%. [ABSTRACT FROM AUTHOR]

This paper investigates a novel structure for the Winograd number theoretic transform algorithm (WNTA) to reduce the computation load. The proposed computing structure exploits the multiple constant multiplication to replace the standard multiplication, then, the multiplication of the WNTA can be realised in a shift-add way, which definitely decreases the complexity of WNTA and maintains the computing accuracy. Typical applications, such as the convolution and the filtering operation, are tested by computer simulations, while the result demonstrates that the proposed scheme is superior to conventional schemes in terms of the trade-off between the complexity. [ABSTRACT FROM AUTHOR]

In this paper, the design of all two-input logic gates is presented by only a single-stage single electron box (SEB) for the first time. All gates are constructed based on a same circuit. We have used unique periodic characteristics of SEB to design these gates and present all two-input logic gates (monotonic/non-monotonic, symmetric/non-symmetric) by a single-stage design. In conventional monotonic devices, such as MOSFETs, implementing non-monotonic logic gates such as XOR and XNOR is impossible by only a single-stage design, and a multistage design is required which leads to more complexity, higher power consumption and less speed of the gates. We present qualitative design at first and then detailed designs are investigated and optimised by using our previous works. All designs are verified by a single electron simulator which shows correct operation of the gates. [ABSTRACT FROM AUTHOR]

In this paper, a novel erasure-based scheme which uses long Reed-Solomon (RS) codes over GF(65537) is proposed for the reduction of the peak-to-average power ratio (PAPR) in coded orthogonal frequency division multiplexing (OFDM). The motivation for using the field GF(65537) is to generate long code words (up to 65536 symbols in just one code word). Using long codes results in greater flexibility to search for low PAPR OFDM frames within the subsets of symbols of a code word because RS codes are maximum distance separable and any subset of a high enough number of symbols is sufficient for the recovery of data. Over this field, the lengths of code words are exponents of 2. Hence, low-complexity radix-2 fast Fourier transform can be exploited. RS codes are deployed for both PAPR reduction and error correction. Simulation results show that in similar PAPR reduction performances, the proposed scheme outperforms the previously reported work with RS codes in both error correction and computation complexity. The proposed scheme can be applied to both single-input single-output and multi-input multi-output systems. [ABSTRACT FROM AUTHOR]

Generally, a coprime L-shaped array (CLsA) is composed of two uniform L-shaped subarrays with larger spacing among inter-element to accomplish the improved direction of arrival (DOA) estimation performance. In this paper, the two subarrays are unfolded to extend the array aperture and the performance of the unfolded CLsA (UCLsA) for two-dimensional (2D) DOA estimation is investigated. In addition, an all array multiple signals classification (AA-MUSIC) algorithm is proposed for the UCLsA. By stacking the received signals of the two subarrays, the ambiguity problem can be avoided on the basis of the coprime property. Simultaneously, due to the combination of the cross-correlation and auto-correlation, the proposed AA-MUSIC algorithm can achieve the full degrees of freedom (DOFs) and obtain more accurate DOA estimates, nevertheless, the expensive total spectral search is entailed. Consequently, a reduced complexity MUSIC (RC-MUSIC) algorithm is proposed to relieve the computational burden. The Cramer-Rao Bounds (CRBs) are utilised as a theoretical benchmark for the lower bound of unbiased estimate. Furthermore, numerical simulations verify the effectiveness and superiority of the AA-MUSIC algorithm and RC-MUSIC method for the UCLsA. [ABSTRACT FROM AUTHOR]

In this paper, the modelling, analysis and the power electronics simulator (PSIM) simulations of the fractional order Buck–Boost converter operating in continuous conduction mode (CCM) operation are investigated. Based on the three-terminal switch device method, the average circuit model of the fractional order Buck–Boost converter is established, and the corresponding DC equivalent circuit model and AC small signal equivalent circuit model are presented. And then, the equilibrium point and the transfer functions are derived. It is found that the equilibrium point is not influenced by the inductor’s or the capacitor’s order, but both these orders are included in the derived transfer functions. Finally, the comparisons between the theoretical analysis and the PSIM simulations are given for confirmation. [ABSTRACT FROM AUTHOR]

P4 polyphase code is well known in pulse compression technique. For P4 code with length 1000, peak sidelobe level (PSL) and integrated sidelobe level (ISL) are −36dB and −16dB, respectively. In order to increase the performance, there are different reduction techniques to reduce the sidelobes of P4 code. This paper presents a novel sidelobe reduction technique that reduces the PSL and ISL to −127dB and −104dB, respectively. Also, other sidelobe reduction techniques such as Woo filter are investigated and compared with the novel proposed technique. Simulations and results show that the proposed technique produces a better peak side lobe ratio (PSL) and integrated side lobe ratio (ISL) than other techniques. [ABSTRACT FROM AUTHOR]

In this paper, we propose a systematic design methodology in the category of hybrid-CMOS logic style. A huge library of circuits appropriate for low-power and high-speed applications can be obtained by employing the proposed design methodology. The methodology is before used for designing XOR/XNOR and demonstrates the excellence of the new design features. The question of whether the method can be taken advantage to design the function of Carry and its complement (Carry and InverseCarry), as the third important module of a full adder, and what to extend the answer contributes to move towards the general systematic design. All the presented designs as before have high driving capability, balanced full-swing outputs with less glitches and small number of transistors. Also these only consist of one pass-transistor in the critical path, which causes low propagation delay and high drivability. As known, hybrid-CMOS full adders can be divided into three modules, e.g., SUM, Carry and XOR. Optimising these modules has reduced power consumption, delay and the number of transistors of full adders. Therefore by embedding the balanced full-swing circuits in carry module, it can be expected that 11 new full adder circuits will possess high performance. Simulation results show that the proposed circuits exhibit better performances compared to previously suggested circuits in the proposed realistic test bench. These circuits, outperform their counterparts, are showing 24–126% improvement in the power-delay product (PDP) and 57–82% improvement in the area. All simulations have been performed with TSMC 0.13-μm technology in new full adder test bench, using HSPISE to achieve the minimum PDP. [ABSTRACT FROM AUTHOR]

Based on a memristive diode bridge cascaded with series resistor and inductor filter, a modified memristive canonical Chua’s circuit is presented in this paper. With the modelling of the memristive circuit, a normalised system model is built. Stability analyses of the equilibrium points are performed and bifurcation behaviours are investigated by numerical simulations and hardware experiments. Most extraordinary in the memristive circuit is that within a parameter region, coexisting phenomenon of multiple bifurcation modes is emerged under six sets of different initial values, resulting in the coexistence of four sets of topologically different and disconnected attractors. These coexisting attractors are easily captured by repeatedly switching on and off the circuit power supplies, which well verify the numerical simulations. [ABSTRACT FROM AUTHOR]

A low-voltage feedforward ring voltage-controlled oscillator (FRVCO) withstanding process variation and supply-voltage noise is proposed in this paper. In this design, the variation of transistors’ threshold voltages and supply voltage noise are detected by a compensating voltage generated circuit, and the load capacitance of the FRVCO is tuned by the compensating voltage to reduce the variation of oscillating frequency. Simulation results demonstrate that the centre oscillating frequency difference between ‘FF’ and ‘SS’ corners is reduced from 38.3% to 1.5% by tuning the voltage from 0 to 650 mV. Moreover, with a supply voltage change of ±0.5%, the frequency variation is smaller than ±0.06%. The 0.65-V 600-MHz FRVCO has been fabricated using the TSMC 130-nm CMOS process. [ABSTRACT FROM AUTHOR]

A robust time delay estimation (TDE)-based direction-finding method for multipath signals in the presence of impulsive noise is proposed in this paper. Compared to traditional algorithms, developed for Gaussian distribution, this method performs more robust in the presence of non-Gaussian noise. The robust TDE is first obtained by utilising the matched filtering in-space which is less sensitive to outliers. Then direction-of-arrival (DOA) is estimated by ‘steering vector fitting’ approach based on the delay estimates. An iterative approach is employed to estimate each multipath component separately and improve the estimation accuracy. The method is developed in-space, which minimises the-norm of residual fitting error vector instead of the Frobenius norm. The number of antennas required can be less than that of the sources. Simulation results show that the method outperforms several outliers-resistant algorithms both in cases of impulsive noise and Gaussian distribution noise. [ABSTRACT FROM AUTHOR]

In this paper, four immittance function simulators consisting of a single modified current follower with single Z− terminal and a minimum number of passive components are proposed. The first proposed circuit can provide +Lparallel with +Rand the second proposed one can realise −Lparallel with −R. The third proposed structure can provide +Lseries with +Rand the fourth proposed one can realise −Lseries with −R. However, all the proposed immittance function simulators need a single resistive matching constraint. Parasitic impedance effects on all the proposed immittance function simulators are investigated. A second-order current-mode (CM) high-pass filter derived from the first proposed immittance function simulator is given as an application example. Also, a second-order CM low-pass filter derived from the third proposed immittance function simulator is given as an application example. A number of simulation results based on SPICE programme and an experimental test result are given to verify the theory. [ABSTRACT FROM AUTHOR]

In this paper, a robust non-linear controller based on the uncertainty and disturbance estimator (UDE) scheme is successfully developed and implemented for the output voltage regulation of the DC–DC boost converter. System uncertainties, external disturbances and unknown non-linear dynamics are lumped as a signal that is accurately estimated using a low-pass filter and their effects are cancelled by the controller. This methodology forms the basis of the UDE-based controller. A simple procedure is also developed that systematically determines the parameters of the controller to meet certain specifications. Using simulation, the effectiveness of the proposed controller is compared against the sliding-mode control (SMC). Experimental tests also show that the proposed controller is robust to system uncertainties, large input and load perturbations. [ABSTRACT FROM PUBLISHER]

There is no doubt that complementary metal-oxide semiconductor (CMOS) circuits with wide fan-in suffers from the relatively sluggish operation. In this paper, a circuit that contains a gang of capacitors sharing their charge with each other is proposed as an alternative to long N-channel MOS and P-channel MOS stacks. The proposed scheme is investigated quantitatively and verified by simulation using the 45-nm CMOS technology withVDD = 1 V. The time delay, area and power consumption of the proposed scheme are investigated and compared with the conventional static CMOS logic circuit. It is verified that the proposed scheme achieves 52% saving in the average propagation delay for eight inputs and that it has a smaller area compared to the conventional CMOS logic when the number of inputs exceeds three and a smaller power consumption for a number of inputs exceeding two. The impacts of process variations, component mismatches and technology scaling on the proposed scheme are also investigated. [ABSTRACT FROM AUTHOR]

This paper presents a comparison among mathematical models used in the simulation of solar photovoltaic modules that can be easily integrated with power electronic converters. In order to perform the analysis, three models available in literature and also the physical model of the module in software PSIM® are used. Some results regarding the respective I × V and P × V curves are presented, while some advantages and eventual limitations are discussed. Besides, a DC–DC buck converter performs maximum power point tracking by using perturb and observe method, while the performance of each one of the aforementioned models is investigated. [ABSTRACT FROM PUBLISHER]

This paper develops a deep insight into the behaviour of high-k dielectric-based field plate on Ni/4H-SiC Schottky diode. It tries to explain the mechanism by which high-k materials outperform silicon dioxide, when used under the field plate. Phenomena like modulation of field enhancement factor, reshaping of equipotential contours and expansion of depletion region while maintaining fixed depletion ratio (length/width = 2.3) helps to understand the electrical behaviour of high-k dielectric-based field plate. High-k materials relaxed the equipotential contours under the field plate edge which resulted in electric field reduction up to 88% and significant drop from 6.6 to 2.2 in field enhancement factor at device edges. The study considers the field plate of different dielectrics (SiO2, Si3N4, Al203, HfO2) and in each case, analytically explores the optimisation of field plate parameters (overlap length and dielectric thickness, dielectric constant). All the investigations have been done using numerical simulations on calibrated setup. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a two-dimensional direction of arrival (2D-DOA) estimation algorithm for uniform rectangular array via noncircular-parallel factor (NC-PARAFAC) method. Compared to the conventional parallel factor (PARAFAC) algorithm, the proposed algorithm exploits the property of noncircular signals to double the array aperture. Therefore, the angle estimation performance of the proposed algorithm is better than the conventional PARAFAC method. The proposed algorithm achieves automatically paired two-dimensional angle estimates, and has better 2D-DOA estimation performance than some conventional algorithms, which include estimation of signal parameters via rotational invariance technique (ESPRIT), propagator method (PM), PARAFAC algorithm, noncircular-ESPRIT (NC-ESPRIT) and noncircular-PM (NC-PM). We also derive the Cramér–Rao bound for the 2D-DOA estimation of noncircular signals with uniform rectangular array. Simulation results verify the effectiveness and improvement of the proposed algorithm. [ABSTRACT FROM PUBLISHER]

Network-on-chip (NoC) is one of critical communication architectures for the scaling of future many-core processors. The challenge for on-chip network is reducing design complexity to save both area and power while providing high performance such as low latency and high throughput. Especially, with increase of network size, both design complexity and power consumption have become the bottlenecks preventing proper network scaling. Moreover, as technology continuously scales down, leakage power takes up a larger fraction of total NoC power. It is increasingly important for a power-efficient NoC design to reduce the increasing leakage power. Power-gating, as a representative low-power technique, can be applied to an on-chip network for mitigating leakage power. In this paper, we propose a low-cost and low-power router architecture for the unidirectional torus network, and adopt an improved corner buffer structure for the inoffensive power-gating, which has minimal impact on network performance. Besides, an explicit starvation avoidance mechanism is introduced to guarantee injection fairness while decreasing its negative impact on network throughput. Simulation results with synthetic traffic show that our design can improve network throughput by 11.3% on average and achieve significant power-saving in low- and medium-load regions. In the SPLASH-2 workload simulation, our design can save on average 27.2% of total power compared to the baseline, and decrease 42.8% average latency compared to the baseline with power-gating. [ABSTRACT FROM AUTHOR]

In this paper, we investigate joint design of quasi-cyclic low-density-parity-check (QC-LDPC) codes for coded cooperation system with joint iterative decoding in the destination. First, QC-LDPC codes based on the base matrix and exponent matrix are introduced, and then we describe two types of girth-4 cycles in QC-LDPC codes employed by the source and relay. In the equivalent parity-check matrix corresponding to the jointly designed QC-LDPC codes employed by the source and relay, all girth-4 cycles including both type I and type II are cancelled. Theoretical analysis and numerical simulations show that the jointly designed QC-LDPC coded cooperation well combines cooperation gain and channel coding gain, and outperforms the coded non-cooperation under the same conditions. Furthermore, the bit error rate performance of the coded cooperation employing jointly designed QC-LDPC codes is better than those of random LDPC codes and separately designed QC-LDPC codes over AWGN channels. [ABSTRACT FROM PUBLISHER]

A low-power hybrid digital pulse width modulator (DPWM) is proposed in the paper. Owing to the piecewise calibration scheme, the delay time of delay line is locked to target frequency. The delay line consists of two piecewise lines with different control codes. The delay time of each cell in one sub-delay-line is longer than the last significant bit (LSB) of DPWM, while the delay time of each cell in the other sub-delay-line is shorter than LSB. Optimum linearity is realised with minimum standard cells. Simulation results show that the differential nonlinearity and integral nonlinearity are improved from 5.1 to 0.4 and from 5 to 1.3, respectively. The DPWM is fully synthesised and fabricated in a 90-nm CMOS process. The proposed DPWM occupies a silicon area of 0.01 mm2, with 31.5 μw core power consumption. Experimental results are shown to demonstrate the 2-MHz, 10-bit resolution implementation. Pulse width histogram is firstly introduced to characterise the linearity of the DPWM. [ABSTRACT FROM PUBLISHER]

In this paper, an enhanced Z-source inverter (ZSI) is introduced for controlling the speed of permanent magnet brushless DC motor (PMBLDCM) drive. It is the extension of the conventional ZSI and the elements used in the circuit are the same as those of the conventional ZSI, except that the position of Inverter Bridge and diode would be exchanged from the classical circuit diagram. This exchanged circuit avoids the startup path of the inrush current and hence reduces the inrush current and improves the motor efficiency. Different modes of enhanced ZSI are studied with PMBLDCM. The voltage polarity of Z-source capacitors in the proposed circuit is the same as that of the input voltage polarity. Furthermore, to get the same voltage boost, the capacitor voltage stress is reduced to a significant extent. The speed control capability of the proposed brushless DC motor drive is compared with that of the conventional ZSI. The proposed ZSI is implemented in MATLAB/Simulink working platform and the output performance is evaluated. Also, the performance of voltage ratio is analysed both by simulation and mathematical models. All these analyses are known to express the innovative features of the proposed system. [ABSTRACT FROM PUBLISHER]

This paper studies the frequency offset correction technique which can be applied in optical OFDM systems. Through theoretical analysis and computer simulations, we can observe that our proposed scheme named pilot self-coding (PSC) has a distinct influence for rectifying the frequency offset, which could mitigate the OFDM performance deterioration because of inter-carrier interference and common phase error. The main approach is to assign a pilot subcarrier before data subcarriers and copy this subcarrier sequence to the symmetric side. The simulation results verify that our proposed PSC is indeed effective against the high degree of frequency offset. [ABSTRACT FROM AUTHOR]

We investigate the issue of direction of arrival (DOA) estimation of noncircular signals for coprime linear array (CLA). The noncircular property enhances the degree of freedom and improves angle estimation performance, but it leads to a more complex angle ambiguity problem. To eliminate ambiguity, we theoretically prove that the actual DOAs of noncircular signals can be uniquely estimated by finding the coincide results from the two decomposed subarrays based on the coprimeness. We propose a locally reduced-dimensional (RD) Capon algorithm for DOA estimation of noncircular signals for CLA. The RD processing is used in the proposed algorithm to avoid two dimensional (2D) spectral peak search, and coprimeness is employed to avoid the global spectral peak search. The proposed algorithm requires one-dimensional locally spectral peak search, and it has very low computational complexity. Furthermore, the proposed algorithm needs no prior knowledge of the number of sources. We also derive the Crámer-Rao bound of DOA estimation of noncircular signals in CLA. Numerical simulation results demonstrate the effectiveness and superiority of the algorithm. [ABSTRACT FROM AUTHOR]

To increase the bandwidth of Extended Interaction Klystron (EIK) at 0.34 THz, the method of staggered tuning on cavities’ configurations is proposed. Based on the analysis of phase relationship between gap voltage and the bunched beam, the buncher cavities in EIK are reasonably staggered-tuned to achieve various resonance frequencies, which is helpful to flat the gain response of the whole device. The characteristics of output cavities with different numbers of gaps are then researched and the issue of start current for the self-oscillation mode is also involved, leading to the optimum number of gaps to enhance the interaction and avoid the instability. By comparing the performances of various typical stagger-tuned models, the final configuration is accordingly confirmed. Particle-in-cell simulation is eventually applied to study performance of the optimised structure, whose gain is 34.8 dB in peak and −3 dB bandwidth reaches about 500 MHz, which is double that of the synchronous-tuned structure. [ABSTRACT FROM AUTHOR]

Three-phase converters using diode or silicon-controlled rectifier (SCR) are widely employed to convert the commercial AC supply to DC. Such converters inject harmonics into the power supply system and thereby distort supply system voltage waveform. A simple input current wave-shape improvement technique using a shunt-connected harmonic current compensator is presented in this work, intended to reduce the total harmonic distortion (THD) of input current of three-phase diode and SCR phase-controlled rectifiers operating with inductive loads, by matching them to the specific converter as a combined package. The compensator proposed here comprises of a three-limb voltage source converter using insulated-gate bipolar transistor, working on instantaneous current and voltage measurements of the compensator only and not of the load. The technique uses a simple feedforward control for AC source current harmonic compensation of rectifiers without monitoring the AC line currents, i.e. use of online computation. The proposed system is simulated and tested on a laboratory prototype. The measured input current THD values without additional line filters are found to be below 8.3%, which is within acceptable limits, proving that the new technique is capable of compensating predetermined current harmonics of diode or SCRs. [ABSTRACT FROM PUBLISHER]

A broadband high-gain planar-printed end-fire antenna is presented for microwave imaging application. The proposed antenna consists of a conventional Vivaldi antenna (CVA) with slot edges (SEs) and a planar phase compensation lens (PCL). Taking into account the actual phase error along E-plane direction at antenna aperture, a more precise and detailed analysis for the printed antenna with PCL is carried out. The PCL with specific layout of rectangular patches is utilised to enhance antenna gain especially at high frequencies, while the SE technique is employed to further improve directivity at low frequencies. The final design combining PCL and SE develops an expected high-flat-gain Vivaldi antenna over the entire operating range. The CVA and the proposed antenna are fabricated and measured. The measured results agree with the simulated ones well. The proposed antenna provides a high gain of 10–11.7 dBi in the range, which corresponds to a gain increase of 0.9–3.2 dBi compared to the CVA. [ABSTRACT FROM PUBLISHER]

A combined analysis of transient simulation and statistical method is proposed for comparative study of signalling methods applied to high-speed backplane transceivers. This method enables fast and accurate signal-to-noise ratio and symbol error rate estimation of a serial link based on a four-dimension design space, including channel characteristics, noise scenarios, equalisation schemes, and signalling methods. The proposed combined analysis method chooses an efficient sampling size for performance evaluation. A comparative study of non-return-to-zero (NRZ), PAM-4, and four-phase shifted sinusoid symbol (PSS-4) using parameterised behaviour-level simulation shows PAM-4 and PSS-4 has substantial advantages over conventional NRZ in most of the cases. A comparison between PAM-4 and PSS-4 shows PAM-4 gets significant bit error rate degradation when noise level is enhanced. [ABSTRACT FROM PUBLISHER]

In single-ended digital audio class D amplifiers (CDAs), the errors caused by power supply noise in the power stages degrade the output performance seriously. In this article, a novel power supply error correction method is proposed. This method introduces the power supply noise of the power stage into the digital signal processing block and builds a power supply error corrector between the interpolation filter and the uniform-sampling pulse width modulation (UPWM) lineariser to pre-correct the power supply error in the single-ended digital audio CDA. The theoretical analysis and implementation of the method are also presented. To verify the effectiveness of the method, a two-channel single-ended digital audio CDA with different power supply error correction methods is designed, simulated, implemented and tested. The simulation and test results obtained show that the method can greatly reduce the error caused by the power supply noise with low hardware cost, and that the CDA with the proposed method can achieve a total harmonic distortion + noise (THD + N) of 0.058% for a –3 dBFS, 1 kHz input when a 55 V linear unregulated direct current (DC) power supply (with the –51 dBFS, 100 Hz power supply noise) is used in the power stages. [ABSTRACT FROM PUBLISHER]

New exact critical conditions for predicting subharmonic instability in switching regulators are approximated by simple design-oriented expressions valid under practical conditions. These simplified expressions contain the ripple and slope information of the feedback control signal. Depending on the converter topology, the controller used and values of parasitic parameters, either the slope or the ripple can be dominant in predicting instability. A discussion on the validity of this interpretation is illustrated through six different examples of switching regulators using the concept of the spectral radius and the relative degree of the system loop. Using this approach, the boundary between the desired stable region and the subharmonic instability can be easily obtained. The theoretical results are validated by means of numerical simulations. [ABSTRACT FROM PUBLISHER]

For ultra-wideband (UWB) ranging, TOA estimation with the energy detection (ED) receiver is to detect the energy sample that contains the first path (FP) signal in dense multipath. Threshold crossing (TC) is used frequently. However, it is difficult to determine the threshold. Some threshold setting methods are based on constant false alarm rate (CFAR) and the chi-squared distribution. However, the distribution is complicated. Moreover, it depends on the degree of freedom (DOF). If the DOF used is wrong, it will degrade the detection performance. The study bypasses the distribution. We first examine the distribution of the output of the ED receiver after power transformation. Based on the new characteristics of the transformed data and approximate distributions, we propose some practical TOA estimation methods. Similarly, the moments of the output of the ED receiver, such as the second or one-third order moments, are also analysed and used. The proposed methods are easy to implement and can achieve about the same ranging performance with methods based on the chi-squared distribution. We provide both theoretical and simulation results to prove their effectiveness. [ABSTRACT FROM AUTHOR]

We introduce a new time-division multiplex wireless power transfer (TDM-WPT) scheme for charging multiple devices with a single transmitter. More specifically, our proposed scheme adopts the intermediate energy storage (IES) circuit which enables storing the received energy from the source temporarily and then supplying it to the load. Thus, by adopting the IES, the receiver can charge the battery with the stored energy in the IES even while the receiver is not performing the direct charging process (from the transmitter). This allows charging multiple receivers simultaneously in a virtual manner, and it eventually leads to the reduction of overall charging time. For the theoretical verification, we analyse the performance of our proposed scheme based on the identical environment and in some selected results. We show that with our proposed scheme the required total charging time can be reduced compared to the conventional TDM-WPT. We also consider practical load (battery charger) requirements which change continuously. We present the simple guidelines for some key design parameters such as the optimal capacity of the IES and the proper number of receivers. Note that we additionally present the sample IES circuit and the related circuit simulation to show the detailed operation and the feasibility of the proposed scheme. [ABSTRACT FROM AUTHOR]

The application of high-resolution space-borne Synthetic Aperture Radar (SAR) becomes more and more popular because of its all-weather and all-time data acquisition capability. However, the interpretation of SAR image can be rather difficult since there are tremendous differences between SAR images and optical images. SAR image simulation is helpful for interpreting SAR images. In this article, a practical approach of SAR image simulation is proposed for urban structures based on Incremental Length Diffraction Coefficients and Shooting and Bouncing Rays (SBR). SBR adopts both GO (Geometrical Optics) and PO (Physical Optics) to calculate the scattered field of targets. Models of buildings with slope roof and flat roof are simulated and inversed. Inversion results coincide well with models and verify the high precision of our approach. [ABSTRACT FROM PUBLISHER]

Design and implementation of a high-speed multiplexer-based fine-grain pipelined architecture for a general digital fuzzy logic controller has been presented. All the operators have been designed at gate level. For the multiplication, a multiplexer-based modified Wallace tree multiplier has been designed, and for the division and addition multiplexer-based non-restoring parallel divider and multiplexer-based Manchester adder have been used, respectively. To further increase the processing speed, fine-grain pipelining technique has been employed. By using this technique, the critical path of the circuit is broken into finer pieces. Based on the proposed architecture, and by using Quartus II 9.1, a sample two-input, one-output digital fuzzy logic controller with eight rules has been successfully synthesised and implemented on Stratix II field programmable gate array. Simulations were carried out using DSP Builder in the MATLAB/Simulink tool at a maximum clock rate of 301.84 MHz. [ABSTRACT FROM PUBLISHER]

A novel structure such as nanoscale silicon-on-insulator (SOI) MOSFET with silicon embedded layer (SEL-SOI) is proposed to reduce self-heating effects (SHEs) successfully. The SEL as a useful heat sink with high thermal conductivity is inserted inside the buried oxide. The SEL acts like a heat sink and is therefore easily able to distribute the lattice heat throughout the device. We noticed excellent improvement in the thermal performance of the device using two-dimensional and two-carrier device simulation. Our simulation results show that SHE has been dramatically reduced in the proposed structure. In regard to the simulated results, the SEL-SOI structure has shown good performance in comparison with the conventional SOI (C-SOI) structure when utilised in the high temperature applications. [ABSTRACT FROM PUBLISHER]