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In this paper, novel voltage-mode (VM) n-channel metal-oxide semiconductor (NMOS) transistor-based analogue adder and subtractor circuits, which, respectively, performV1+V2andV1−V2operations, are presented. The most important feature of the proposed circuits is their extremely simple structures containing only six NMOS transistors. Further, the presented adder and subtractor circuits have high input and low output impedances, resulting in easy cascadability. The post-layout simulations of the proposed circuits have been executed using TSMC 0.25 µm process parameters with ±1.25 V. The area of the suggested circuits is approximately 30 × 13 µm2. Moreover, the topology of a generalised mutator, a versatile 4-port built with an adder and a subtractor, which acts as an ordinary mutator when properly reduced to a 2-port, is offered. A table for simulating lossless inductance, memristor, meminductor, memcapacitor and other elements under suitable termination of the 4-port is given, and three of these elements’ simulations with SPICE are also presented. [ABSTRACT FROM AUTHOR]

In this work, a very compact, rail-to-rail, high-speed buffer amplifier for liquid crystal display (LCD) applications is proposed. Compared to other buffer amplifiers, the proposed circuit has a very simple architecture, occupies a small number of transistors and also has a large driving capacity with very low quiescent current. It is composed of two complementary differential input stages to provide rail-to-rail driving capacity. The push–pull transistors are directly connected to the differential input stage, and the output is taken from an inverter. The proposed buffer circuit is laid out using Mentor Graphics IC Station layout editor using AMS 0.35 μm process parameters. It is shown by post-layout simulations that the proposed buffer can drive a 1 nF capacitive load within a small settling time under a full voltage swing, while drawing only 1.6 μA quiescent current from a 3.3 V power supply. [ABSTRACT FROM AUTHOR]

In this article, a universal nth-order current-mode filter employing electronically tunable second-generation current conveyors (ECCIIs) and grounded passive elements is proposed. As the current gain of the ECCII can be controlled electronically by adjusting the ratio of its DC bias currents, it is possible to tune all the coefficients of the transfer function independently. SPICE simulation results using TSMC 0.35 μm CMOS process model are included to verify the theory. Furthermore, a design example of a fourth-order video band filter is given to illustrate the application of the introduced topology in analog circuit design. [ABSTRACT FROM AUTHOR]

In this paper a new floating inductance simulator employing only active elements is proposed. The proposed circuit uses one internally compensated operational amplifier and one dual output current controlled conveyor (CCCII). The simulated inductance value can be controlled electronically by adjusting the bias current of the CCCII. No component matching constraints are imposed for the simulator and all active sensitivities are low. The performance of the circuit is demonstrated on a fourth-order elliptic filter using a SPICE simulation program. [ABSTRACT FROM AUTHOR]